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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "qemu/qemu-print.h"
23#include "cpu.h"
24
25static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
26{
27 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
28
29 cpu->env.pc = value;
30 cpu->env.dflag = 0;
31}
32
33static bool openrisc_cpu_has_work(CPUState *cs)
34{
35 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
36 CPU_INTERRUPT_TIMER);
37}
38
39static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
40{
41 info->print_insn = print_insn_or1k;
42}
43
44
45static void openrisc_cpu_reset(CPUState *s)
46{
47 OpenRISCCPU *cpu = OPENRISC_CPU(s);
48 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
49
50 occ->parent_reset(s);
51
52 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
53
54 cpu->env.pc = 0x100;
55 cpu->env.sr = SR_FO | SR_SM;
56 cpu->env.lock_addr = -1;
57 s->exception_index = -1;
58
59 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
60 UPR_PMP;
61 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
62 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
63 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
64 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
65
66#ifndef CONFIG_USER_ONLY
67 cpu->env.picmr = 0x00000000;
68 cpu->env.picsr = 0x00000000;
69
70 cpu->env.ttmr = 0x00000000;
71#endif
72}
73
74static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
75{
76 CPUState *cs = CPU(dev);
77 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
78 Error *local_err = NULL;
79
80 cpu_exec_realizefn(cs, &local_err);
81 if (local_err != NULL) {
82 error_propagate(errp, local_err);
83 return;
84 }
85
86 qemu_init_vcpu(cs);
87 cpu_reset(cs);
88
89 occ->parent_realize(dev, errp);
90}
91
92static void openrisc_cpu_initfn(Object *obj)
93{
94 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
95
96 cpu_set_cpustate_pointers(cpu);
97}
98
99
100
101static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
102{
103 ObjectClass *oc;
104 char *typename;
105
106 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
107 oc = object_class_by_name(typename);
108 g_free(typename);
109 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
110 object_class_is_abstract(oc))) {
111 return NULL;
112 }
113 return oc;
114}
115
116static void or1200_initfn(Object *obj)
117{
118 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
119
120 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
121 CPUCFGR_EVBARP;
122}
123
124static void openrisc_any_initfn(Object *obj)
125{
126 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
127
128 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
129}
130
131static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
132{
133 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
134 CPUClass *cc = CPU_CLASS(occ);
135 DeviceClass *dc = DEVICE_CLASS(oc);
136
137 device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
138 &occ->parent_realize);
139 occ->parent_reset = cc->reset;
140 cc->reset = openrisc_cpu_reset;
141
142 cc->class_by_name = openrisc_cpu_class_by_name;
143 cc->has_work = openrisc_cpu_has_work;
144 cc->do_interrupt = openrisc_cpu_do_interrupt;
145 cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
146 cc->dump_state = openrisc_cpu_dump_state;
147 cc->set_pc = openrisc_cpu_set_pc;
148 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
149 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
150 cc->tlb_fill = openrisc_cpu_tlb_fill;
151#ifndef CONFIG_USER_ONLY
152 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
153 dc->vmsd = &vmstate_openrisc_cpu;
154#endif
155 cc->gdb_num_core_regs = 32 + 3;
156 cc->tcg_initialize = openrisc_translate_init;
157 cc->disas_set_info = openrisc_disas_set_info;
158}
159
160
161static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
162{
163 ObjectClass *class_a = (ObjectClass *)a;
164 ObjectClass *class_b = (ObjectClass *)b;
165 const char *name_a, *name_b;
166
167 name_a = object_class_get_name(class_a);
168 name_b = object_class_get_name(class_b);
169 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
170 return 1;
171 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
172 return -1;
173 } else {
174 return strcmp(name_a, name_b);
175 }
176}
177
178static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
179{
180 ObjectClass *oc = data;
181 const char *typename;
182 char *name;
183
184 typename = object_class_get_name(oc);
185 name = g_strndup(typename,
186 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
187 qemu_printf(" %s\n", name);
188 g_free(name);
189}
190
191void cpu_openrisc_list(void)
192{
193 GSList *list;
194
195 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
196 list = g_slist_sort(list, openrisc_cpu_list_compare);
197 qemu_printf("Available CPUs:\n");
198 g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
199 g_slist_free(list);
200}
201
202#define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
203 { \
204 .parent = TYPE_OPENRISC_CPU, \
205 .instance_init = initfn, \
206 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
207 }
208
209static const TypeInfo openrisc_cpus_type_infos[] = {
210 {
211 .name = TYPE_OPENRISC_CPU,
212 .parent = TYPE_CPU,
213 .instance_size = sizeof(OpenRISCCPU),
214 .instance_init = openrisc_cpu_initfn,
215 .abstract = true,
216 .class_size = sizeof(OpenRISCCPUClass),
217 .class_init = openrisc_cpu_class_init,
218 },
219 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
220 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
221};
222
223DEFINE_TYPES(openrisc_cpus_type_infos)
224