LXR qemu/target/ppc/cpu.h

   1/*
   2 *  PowerPC emulation cpu definitions for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_CPU_H
  21#define PPC_CPU_H
  22
  23#include "qemu/int128.h"
  24#include "exec/cpu-defs.h"
  25#include "cpu-qom.h"
  26#include "exec/cpu-defs.h"
  27#include "cpu-qom.h"
  28
  29/* #define PPC_EMULATE_32BITS_HYPV */
  30
  31#define TCG_GUEST_DEFAULT_MO 0
  32
  33#define TARGET_PAGE_BITS_64K 16
  34#define TARGET_PAGE_BITS_16M 24
  35
  36#if defined(TARGET_PPC64)
  37#define PPC_ELF_MACHINE     EM_PPC64
  38#else
  39#define PPC_ELF_MACHINE     EM_PPC
  40#endif
  41
  42#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
  43#define PPC_BIT32(bit)          (0x80000000 >> (bit))
  44#define PPC_BIT8(bit)           (0x80 >> (bit))
  45#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  46#define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  47                                 PPC_BIT32(bs))
  48#define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  49
  50/*****************************************************************************/
  51/* Exception vectors definitions                                             */
  52enum {
  53    POWERPC_EXCP_NONE    = -1,
  54    /* The 64 first entries are used by the PowerPC embedded specification   */
  55    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  56    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  57    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  58    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  59    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  60    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  61    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  62    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  63    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
  64    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
  65    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
  66    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
  67    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
  68    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
  69    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
  70    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
  71    /* Vectors 16 to 31 are reserved                                         */
  72    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
  73    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
  74    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
  75    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
  76    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
  77    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
  78    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
  79    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
  80    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
  81    /* Vectors 42 to 63 are reserved                                         */
  82    /* Exceptions defined in the PowerPC server specification                */
  83    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
  84    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
  85    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
  86    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
  87    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
  88    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
  89    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
  90    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
  91    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
  92    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
  93    /* 40x specific exceptions                                               */
  94    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
  95    /* 601 specific exceptions                                               */
  96    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
  97    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
  98    /* 602 specific exceptions                                               */
  99    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 100    /* 602/603 specific exceptions                                           */
 101    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 102    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 103    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 104    /* Exceptions available on most PowerPC                                  */
 105    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 106    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 107    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 108    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 109    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 110    /* 7xx/74xx specific exceptions                                          */
 111    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 112    /* 74xx specific exceptions                                              */
 113    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 114    /* 970FX specific exceptions                                             */
 115    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 116    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 117    /* Freescale embedded cores specific exceptions                          */
 118    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 119    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 120    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 121    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 122    /* VSX Unavailable (Power ISA 2.06 and later)                            */
 123    POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 124    POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 125    /* Additional ISA 2.06 and later server exceptions                       */
 126    POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 127    POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 128    POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 129    /* Server doorbell variants */
 130    POWERPC_EXCP_SDOOR    = 99,
 131    POWERPC_EXCP_SDOOR_HV = 100,
 132    /* ISA 3.00 additions */
 133    POWERPC_EXCP_HVIRT    = 101,
 134    /* EOL                                                                   */
 135    POWERPC_EXCP_NB       = 102,
 136    /* QEMU exceptions: used internally during code translation              */
 137    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 138    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 139    /* QEMU exceptions: special cases we want to stop translation            */
 140    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 141    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 142};
 143
 144/* Exceptions error codes                                                    */
 145enum {
 146    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 147    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 148    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 149    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 150    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 151    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 152    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 153    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 154    /* FP exceptions                                                         */
 155    POWERPC_EXCP_FP            = 0x10,
 156    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 157    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 158    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 159    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 160    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 161    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 162    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 163    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 164    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 165    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 166    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 167    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 168    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 169    /* Invalid instruction                                                   */
 170    POWERPC_EXCP_INVAL         = 0x20,
 171    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 172    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 173    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 174    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 175    /* Privileged instruction                                                */
 176    POWERPC_EXCP_PRIV          = 0x30,
 177    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 178    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 179    /* Trap                                                                  */
 180    POWERPC_EXCP_TRAP          = 0x40,
 181};
 182
 183#define PPC_INPUT(env) (env->bus_model)
 184
 185/*****************************************************************************/
 186typedef struct opc_handler_t opc_handler_t;
 187
 188/*****************************************************************************/
 189/* Types used to describe some PowerPC registers etc. */
 190typedef struct DisasContext DisasContext;
 191typedef struct ppc_spr_t ppc_spr_t;
 192typedef union ppc_tlb_t ppc_tlb_t;
 193typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 194
 195/* SPR access micro-ops generations callbacks */
 196struct ppc_spr_t {
 197    void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 198    void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 199#if !defined(CONFIG_USER_ONLY)
 200    void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 201    void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 202    void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 203    void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 204    unsigned int gdb_id;
 205#endif
 206    const char *name;
 207    target_ulong default_value;
 208#ifdef CONFIG_KVM
 209    /*
 210     * We (ab)use the fact that all the SPRs will have ids for the
 211     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 212     * don't sync this
 213     */
 214    uint64_t one_reg_id;
 215#endif
 216};
 217
 218/* VSX/Altivec registers (128 bits) */
 219typedef union _ppc_vsr_t {
 220    uint8_t u8[16];
 221    uint16_t u16[8];
 222    uint32_t u32[4];
 223    uint64_t u64[2];
 224    int8_t s8[16];
 225    int16_t s16[8];
 226    int32_t s32[4];
 227    int64_t s64[2];
 228    float32 f32[4];
 229    float64 f64[2];
 230    float128 f128;
 231#ifdef CONFIG_INT128
 232    __uint128_t u128;
 233#endif
 234    Int128  s128;
 235} ppc_vsr_t;
 236
 237typedef ppc_vsr_t ppc_avr_t;
 238
 239#if !defined(CONFIG_USER_ONLY)
 240/* Software TLB cache */
 241typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 242struct ppc6xx_tlb_t {
 243    target_ulong pte0;
 244    target_ulong pte1;
 245    target_ulong EPN;
 246};
 247
 248typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 249struct ppcemb_tlb_t {
 250    uint64_t RPN;
 251    target_ulong EPN;
 252    target_ulong PID;
 253    target_ulong size;
 254    uint32_t prot;
 255    uint32_t attr; /* Storage attributes */
 256};
 257
 258typedef struct ppcmas_tlb_t {
 259     uint32_t mas8;
 260     uint32_t mas1;
 261     uint64_t mas2;
 262     uint64_t mas7_3;
 263} ppcmas_tlb_t;
 264
 265union ppc_tlb_t {
 266    ppc6xx_tlb_t *tlb6;
 267    ppcemb_tlb_t *tlbe;
 268    ppcmas_tlb_t *tlbm;
 269};
 270
 271/* possible TLB variants */
 272#define TLB_NONE               0
 273#define TLB_6XX                1
 274#define TLB_EMB                2
 275#define TLB_MAS                3
 276#endif
 277
 278typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
 279
 280typedef struct ppc_slb_t ppc_slb_t;
 281struct ppc_slb_t {
 282    uint64_t esid;
 283    uint64_t vsid;
 284    const PPCHash64SegmentPageSizes *sps;
 285};
 286
 287#define MAX_SLB_ENTRIES         64
 288#define SEGMENT_SHIFT_256M      28
 289#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 290
 291#define SEGMENT_SHIFT_1T        40
 292#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 293
 294typedef struct ppc_v3_pate_t {
 295    uint64_t dw0;
 296    uint64_t dw1;
 297} ppc_v3_pate_t;
 298
 299/*****************************************************************************/
 300/* Machine state register bits definition                                    */
 301#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 302#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 303#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 304#define MSR_SHV  60 /* hypervisor state                               hflags */
 305#define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 306#define MSR_TS1  33
 307#define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 308#define MSR_CM   31 /* Computation mode for BookE                     hflags */
 309#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 310#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 311#define MSR_GS   28 /* guest state for BookE                                 */
 312#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 313#define MSR_VR   25 /* altivec available                            x hflags */
 314#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 315#define MSR_AP   23 /* Access privilege state on 602                  hflags */
 316#define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 317#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 318#define MSR_KEY  19 /* key bit on 603e                                       */
 319#define MSR_POW  18 /* Power management                                      */
 320#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 321#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 322#define MSR_ILE  16 /* Interrupt little-endian mode                          */
 323#define MSR_EE   15 /* External interrupt enable                             */
 324#define MSR_PR   14 /* Problem state                                  hflags */
 325#define MSR_FP   13 /* Floating point available                       hflags */
 326#define MSR_ME   12 /* Machine check interrupt enable                        */
 327#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 328#define MSR_SE   10 /* Single-step trace enable                     x hflags */
 329#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 330#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 331#define MSR_BE   9  /* Branch trace enable                          x hflags */
 332#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 333#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 334#define MSR_AL   7  /* AL bit on POWER                                       */
 335#define MSR_EP   6  /* Exception prefix on 601                               */
 336#define MSR_IR   5  /* Instruction relocate                                  */
 337#define MSR_DR   4  /* Data relocate                                         */
 338#define MSR_IS   5  /* Instruction address space (BookE)                     */
 339#define MSR_DS   4  /* Data address space (BookE)                            */
 340#define MSR_PE   3  /* Protection enable on 403                              */
 341#define MSR_PX   2  /* Protection exclusive on 403                  x        */
 342#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 343#define MSR_RI   1  /* Recoverable interrupt                        1        */
 344#define MSR_LE   0  /* Little-endian mode                           1 hflags */
 345
 346/* LPCR bits */
 347#define LPCR_VPM0         PPC_BIT(0)
 348#define LPCR_VPM1         PPC_BIT(1)
 349#define LPCR_ISL          PPC_BIT(2)
 350#define LPCR_KBV          PPC_BIT(3)
 351#define LPCR_DPFD_SHIFT   (63 - 11)
 352#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 353#define LPCR_VRMASD_SHIFT (63 - 16)
 354#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 355/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 356#define LPCR_PECE_U_SHIFT (63 - 19)
 357#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 358#define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 359#define LPCR_RMLS_SHIFT   (63 - 37)
 360#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 361#define LPCR_ILE          PPC_BIT(38)
 362#define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 363#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 364#define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 365#define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 366#define LPCR_HR           PPC_BIT(43) /* Host Radix */
 367#define LPCR_ONL          PPC_BIT(45)
 368#define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 369#define LPCR_P7_PECE0     PPC_BIT(49)
 370#define LPCR_P7_PECE1     PPC_BIT(50)
 371#define LPCR_P7_PECE2     PPC_BIT(51)
 372#define LPCR_P8_PECE0     PPC_BIT(47)
 373#define LPCR_P8_PECE1     PPC_BIT(48)
 374#define LPCR_P8_PECE2     PPC_BIT(49)
 375#define LPCR_P8_PECE3     PPC_BIT(50)
 376#define LPCR_P8_PECE4     PPC_BIT(51)
 377/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 378#define LPCR_PECE_L_SHIFT (63 - 51)
 379#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 380#define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 381#define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 382#define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 383#define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 384#define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 385#define LPCR_MER          PPC_BIT(52)
 386#define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 387#define LPCR_TC           PPC_BIT(54)
 388#define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 389#define LPCR_LPES0        PPC_BIT(60)
 390#define LPCR_LPES1        PPC_BIT(61)
 391#define LPCR_RMI          PPC_BIT(62)
 392#define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 393#define LPCR_HDICE        PPC_BIT(63)
 394
 395/* PSSCR bits */
 396#define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
 397#define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
 398
 399#define msr_sf   ((env->msr >> MSR_SF)   & 1)
 400#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 401#define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 402#define msr_cm   ((env->msr >> MSR_CM)   & 1)
 403#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 404#define msr_thv  ((env->msr >> MSR_THV)  & 1)
 405#define msr_gs   ((env->msr >> MSR_GS)   & 1)
 406#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 407#define msr_vr   ((env->msr >> MSR_VR)   & 1)
 408#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 409#define msr_ap   ((env->msr >> MSR_AP)   & 1)
 410#define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 411#define msr_sa   ((env->msr >> MSR_SA)   & 1)
 412#define msr_key  ((env->msr >> MSR_KEY)  & 1)
 413#define msr_pow  ((env->msr >> MSR_POW)  & 1)
 414#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 415#define msr_ce   ((env->msr >> MSR_CE)   & 1)
 416#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 417#define msr_ee   ((env->msr >> MSR_EE)   & 1)
 418#define msr_pr   ((env->msr >> MSR_PR)   & 1)
 419#define msr_fp   ((env->msr >> MSR_FP)   & 1)
 420#define msr_me   ((env->msr >> MSR_ME)   & 1)
 421#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 422#define msr_se   ((env->msr >> MSR_SE)   & 1)
 423#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 424#define msr_uble ((env->msr >> MSR_UBLE) & 1)
 425#define msr_be   ((env->msr >> MSR_BE)   & 1)
 426#define msr_de   ((env->msr >> MSR_DE)   & 1)
 427#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 428#define msr_al   ((env->msr >> MSR_AL)   & 1)
 429#define msr_ep   ((env->msr >> MSR_EP)   & 1)
 430#define msr_ir   ((env->msr >> MSR_IR)   & 1)
 431#define msr_dr   ((env->msr >> MSR_DR)   & 1)
 432#define msr_is   ((env->msr >> MSR_IS)   & 1)
 433#define msr_ds   ((env->msr >> MSR_DS)   & 1)
 434#define msr_pe   ((env->msr >> MSR_PE)   & 1)
 435#define msr_px   ((env->msr >> MSR_PX)   & 1)
 436#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 437#define msr_ri   ((env->msr >> MSR_RI)   & 1)
 438#define msr_le   ((env->msr >> MSR_LE)   & 1)
 439#define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 440#define msr_tm   ((env->msr >> MSR_TM)   & 1)
 441
 442#define DBCR0_ICMP (1 << 27)
 443#define DBCR0_BRT (1 << 26)
 444#define DBSR_ICMP (1 << 27)
 445#define DBSR_BRT (1 << 26)
 446
 447/* Hypervisor bit is more specific */
 448#if defined(TARGET_PPC64)
 449#define MSR_HVB (1ULL << MSR_SHV)
 450#define msr_hv  msr_shv
 451#else
 452#if defined(PPC_EMULATE_32BITS_HYPV)
 453#define MSR_HVB (1ULL << MSR_THV)
 454#define msr_hv  msr_thv
 455#else
 456#define MSR_HVB (0ULL)
 457#define msr_hv  (0)
 458#endif
 459#endif
 460
 461/* DSISR */
 462#define DSISR_NOPTE              0x40000000
 463/* Not permitted by access authority of encoded access authority */
 464#define DSISR_PROTFAULT          0x08000000
 465#define DSISR_ISSTORE            0x02000000
 466/* Not permitted by virtual page class key protection */
 467#define DSISR_AMR                0x00200000
 468/* Unsupported Radix Tree Configuration */
 469#define DSISR_R_BADCONFIG        0x00080000
 470
 471/* SRR1 error code fields */
 472
 473#define SRR1_NOPTE               DSISR_NOPTE
 474/* Not permitted due to no-execute or guard bit set */
 475#define SRR1_NOEXEC_GUARD        0x10000000
 476#define SRR1_PROTFAULT           DSISR_PROTFAULT
 477#define SRR1_IAMR                DSISR_AMR
 478
 479/* Facility Status and Control (FSCR) bits */
 480#define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 481#define FSCR_TAR        (63 - 55) /* Target Address Register */
 482/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 483#define FSCR_IC_MASK    (0xFFULL)
 484#define FSCR_IC_POS     (63 - 7)
 485#define FSCR_IC_DSCR_SPR3   2
 486#define FSCR_IC_PMU         3
 487#define FSCR_IC_BHRB        4
 488#define FSCR_IC_TM          5
 489#define FSCR_IC_EBB         7
 490#define FSCR_IC_TAR         8
 491
 492/* Exception state register bits definition                                  */
 493#define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 494#define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 495#define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 496#define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 497#define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 498#define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 499#define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 500#define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 501#define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 502#define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 503#define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 504#define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 505#define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 506#define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 507#define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 508#define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 509
 510/* Transaction EXception And Summary Register bits                           */
 511#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 512#define TEXASR_DISALLOWED                        (63 - 8)
 513#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 514#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 515#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 516#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 517#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 518#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 519#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 520#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 521#define TEXASR_ABORT                             (63 - 31)
 522#define TEXASR_SUSPENDED                         (63 - 32)
 523#define TEXASR_PRIVILEGE_HV                      (63 - 34)
 524#define TEXASR_PRIVILEGE_PR                      (63 - 35)
 525#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 526#define TEXASR_TFIAR_EXACT                       (63 - 37)
 527#define TEXASR_ROT                               (63 - 38)
 528#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 529
 530enum {
 531    POWERPC_FLAG_NONE     = 0x00000000,
 532    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 533    POWERPC_FLAG_SPE      = 0x00000001,
 534    POWERPC_FLAG_VRE      = 0x00000002,
 535    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 536    POWERPC_FLAG_TGPR     = 0x00000004,
 537    POWERPC_FLAG_CE       = 0x00000008,
 538    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 539    POWERPC_FLAG_SE       = 0x00000010,
 540    POWERPC_FLAG_DWE      = 0x00000020,
 541    POWERPC_FLAG_UBLE     = 0x00000040,
 542    /* Flag for MSR bit 9 signification (BE/DE)                              */
 543    POWERPC_FLAG_BE       = 0x00000080,
 544    POWERPC_FLAG_DE       = 0x00000100,
 545    /* Flag for MSR bit 2 signification (PX/PMM)                             */
 546    POWERPC_FLAG_PX       = 0x00000200,
 547    POWERPC_FLAG_PMM      = 0x00000400,
 548    /* Flag for special features                                             */
 549    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 550    POWERPC_FLAG_RTC_CLK  = 0x00010000,
 551    POWERPC_FLAG_BUS_CLK  = 0x00020000,
 552    /* Has CFAR                                                              */
 553    POWERPC_FLAG_CFAR     = 0x00040000,
 554    /* Has VSX                                                               */
 555    POWERPC_FLAG_VSX      = 0x00080000,
 556    /* Has Transaction Memory (ISA 2.07)                                     */
 557    POWERPC_FLAG_TM       = 0x00100000,
 558};
 559
 560/*****************************************************************************/
 561/* Floating point status and control register                                */
 562#define FPSCR_FX     31 /* Floating-point exception summary                  */
 563#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 564#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 565#define FPSCR_OX     28 /* Floating-point overflow exception                 */
 566#define FPSCR_UX     27 /* Floating-point underflow exception                */
 567#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 568#define FPSCR_XX     25 /* Floating-point inexact exception                  */
 569#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 570#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 571#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 572#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 573#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 574#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 575#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 576#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 577#define FPSCR_C      16 /* Floating-point result class descriptor            */
 578#define FPSCR_FL     15 /* Floating-point less than or negative              */
 579#define FPSCR_FG     14 /* Floating-point greater than or negative           */
 580#define FPSCR_FE     13 /* Floating-point equal or zero                      */
 581#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 582#define FPSCR_FPCC   12 /* Floating-point condition code                     */
 583#define FPSCR_FPRF   12 /* Floating-point result flags                       */
 584#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 585#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 586#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 587#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 588#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 589#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 590#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 591#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 592#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 593#define FPSCR_RN1    1
 594#define FPSCR_RN     0  /* Floating-point rounding control                   */
 595#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 596#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 597#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 598#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 599#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 600#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 601#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 602#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 603#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 604#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 605#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 606#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 607#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 608#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 609#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 610#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 611#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 612#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 613#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 614#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 615#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 616#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 617#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 618/* Invalid operation exception summary */
 619#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 620                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 621                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 622                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 623                                  (1 << FPSCR_VXCVI)))
 624/* exception summary */
 625#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 626/* enabled exception summary */
 627#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 628                   0x1F)
 629
 630#define FP_FX           (1ull << FPSCR_FX)
 631#define FP_FEX          (1ull << FPSCR_FEX)
 632#define FP_VX           (1ull << FPSCR_VX)
 633#define FP_OX           (1ull << FPSCR_OX)
 634#define FP_UX           (1ull << FPSCR_UX)
 635#define FP_ZX           (1ull << FPSCR_ZX)
 636#define FP_XX           (1ull << FPSCR_XX)
 637#define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 638#define FP_VXISI        (1ull << FPSCR_VXISI)
 639#define FP_VXIDI        (1ull << FPSCR_VXIDI)
 640#define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 641#define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 642#define FP_VXVC         (1ull << FPSCR_VXVC)
 643#define FP_FR           (1ull << FSPCR_FR)
 644#define FP_FI           (1ull << FPSCR_FI)
 645#define FP_C            (1ull << FPSCR_C)
 646#define FP_FL           (1ull << FPSCR_FL)
 647#define FP_FG           (1ull << FPSCR_FG)
 648#define FP_FE           (1ull << FPSCR_FE)
 649#define FP_FU           (1ull << FPSCR_FU)
 650#define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 651#define FP_FPRF         (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
 652#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 653#define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 654#define FP_VXCVI        (1ull << FPSCR_VXCVI)
 655#define FP_VE           (1ull << FPSCR_VE)
 656#define FP_OE           (1ull << FPSCR_OE)
 657#define FP_UE           (1ull << FPSCR_UE)
 658#define FP_ZE           (1ull << FPSCR_ZE)
 659#define FP_XE           (1ull << FPSCR_XE)
 660#define FP_NI           (1ull << FPSCR_NI)
 661#define FP_RN1          (1ull << FPSCR_RN1)
 662#define FP_RN           (1ull << FPSCR_RN)
 663
 664/* the exception bits which can be cleared by mcrfs - includes FX */
 665#define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 666                          FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 667                          FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 668                          FP_VXSQRT | FP_VXCVI)
 669
 670/*****************************************************************************/
 671/* Vector status and control register */
 672#define VSCR_NJ         16 /* Vector non-java */
 673#define VSCR_SAT        0 /* Vector saturation */
 674
 675/*****************************************************************************/
 676/* BookE e500 MMU registers */
 677
 678#define MAS0_NV_SHIFT      0
 679#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 680
 681#define MAS0_WQ_SHIFT      12
 682#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 683/* Write TLB entry regardless of reservation */
 684#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 685/* Write TLB entry only already in use */
 686#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 687/* Clear TLB entry */
 688#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 689
 690#define MAS0_HES_SHIFT     14
 691#define MAS0_HES           (1 << MAS0_HES_SHIFT)
 692
 693#define MAS0_ESEL_SHIFT    16
 694#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 695
 696#define MAS0_TLBSEL_SHIFT  28
 697#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 698#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 699#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 700#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 701#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 702
 703#define MAS0_ATSEL_SHIFT   31
 704#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 705#define MAS0_ATSEL_TLB     0
 706#define MAS0_ATSEL_LRAT    MAS0_ATSEL
 707
 708#define MAS1_TSIZE_SHIFT   7
 709#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 710
 711#define MAS1_TS_SHIFT      12
 712#define MAS1_TS            (1 << MAS1_TS_SHIFT)
 713
 714#define MAS1_IND_SHIFT     13
 715#define MAS1_IND           (1 << MAS1_IND_SHIFT)
 716
 717#define MAS1_TID_SHIFT     16
 718#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 719
 720#define MAS1_IPROT_SHIFT   30
 721#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 722
 723#define MAS1_VALID_SHIFT   31
 724#define MAS1_VALID         0x80000000
 725
 726#define MAS2_EPN_SHIFT     12
 727#define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 728
 729#define MAS2_ACM_SHIFT     6
 730#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 731
 732#define MAS2_VLE_SHIFT     5
 733#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 734
 735#define MAS2_W_SHIFT       4
 736#define MAS2_W             (1 << MAS2_W_SHIFT)
 737
 738#define MAS2_I_SHIFT       3
 739#define MAS2_I             (1 << MAS2_I_SHIFT)
 740
 741#define MAS2_M_SHIFT       2
 742#define MAS2_M             (1 << MAS2_M_SHIFT)
 743
 744#define MAS2_G_SHIFT       1
 745#define MAS2_G             (1 << MAS2_G_SHIFT)
 746
 747#define MAS2_E_SHIFT       0
 748#define MAS2_E             (1 << MAS2_E_SHIFT)
 749
 750#define MAS3_RPN_SHIFT     12
 751#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 752
 753#define MAS3_U0                 0x00000200
 754#define MAS3_U1                 0x00000100
 755#define MAS3_U2                 0x00000080
 756#define MAS3_U3                 0x00000040
 757#define MAS3_UX                 0x00000020
 758#define MAS3_SX                 0x00000010
 759#define MAS3_UW                 0x00000008
 760#define MAS3_SW                 0x00000004
 761#define MAS3_UR                 0x00000002
 762#define MAS3_SR                 0x00000001
 763#define MAS3_SPSIZE_SHIFT       1
 764#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 765
 766#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 767#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 768#define MAS4_TIDSELD_MASK       0x00030000
 769#define MAS4_TIDSELD_PID0       0x00000000
 770#define MAS4_TIDSELD_PID1       0x00010000
 771#define MAS4_TIDSELD_PID2       0x00020000
 772#define MAS4_TIDSELD_PIDZ       0x00030000
 773#define MAS4_INDD               0x00008000      /* Default IND */
 774#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 775#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 776#define MAS4_ACMD               0x00000040
 777#define MAS4_VLED               0x00000020
 778#define MAS4_WD                 0x00000010
 779#define MAS4_ID                 0x00000008
 780#define MAS4_MD                 0x00000004
 781#define MAS4_GD                 0x00000002
 782#define MAS4_ED                 0x00000001
 783#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 784#define MAS4_WIMGED_SHIFT       0
 785
 786#define MAS5_SGS                0x80000000
 787#define MAS5_SLPID_MASK         0x00000fff
 788
 789#define MAS6_SPID0              0x3fff0000
 790#define MAS6_SPID1              0x00007ffe
 791#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 792#define MAS6_SAS                0x00000001
 793#define MAS6_SPID               MAS6_SPID0
 794#define MAS6_SIND               0x00000002      /* Indirect page */
 795#define MAS6_SIND_SHIFT         1
 796#define MAS6_SPID_MASK          0x3fff0000
 797#define MAS6_SPID_SHIFT         16
 798#define MAS6_ISIZE_MASK         0x00000f80
 799#define MAS6_ISIZE_SHIFT        7
 800
 801#define MAS7_RPN                0xffffffff
 802
 803#define MAS8_TGS                0x80000000
 804#define MAS8_VF                 0x40000000
 805#define MAS8_TLBPID             0x00000fff
 806
 807/* Bit definitions for MMUCFG */
 808#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 809#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 810#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 811#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 812#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 813#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 814#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 815#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 816#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 817
 818/* Bit definitions for MMUCSR0 */
 819#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 820#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 821#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 822#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 823#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 824                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 825#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 826#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 827#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 828#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 829
 830/* TLBnCFG encoding */
 831#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 832#define TLBnCFG_HES             0x00002000      /* HW select supported */
 833#define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 834#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 835#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 836#define TLBnCFG_IND             0x00020000      /* IND entries supported */
 837#define TLBnCFG_PT              0x00040000      /* Can load from page table */
 838#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 839#define TLBnCFG_MINSIZE_SHIFT   20
 840#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 841#define TLBnCFG_MAXSIZE_SHIFT   16
 842#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 843#define TLBnCFG_ASSOC_SHIFT     24
 844
 845/* TLBnPS encoding */
 846#define TLBnPS_4K               0x00000004
 847#define TLBnPS_8K               0x00000008
 848#define TLBnPS_16K              0x00000010
 849#define TLBnPS_32K              0x00000020
 850#define TLBnPS_64K              0x00000040
 851#define TLBnPS_128K             0x00000080
 852#define TLBnPS_256K             0x00000100
 853#define TLBnPS_512K             0x00000200
 854#define TLBnPS_1M               0x00000400
 855#define TLBnPS_2M               0x00000800
 856#define TLBnPS_4M               0x00001000
 857#define TLBnPS_8M               0x00002000
 858#define TLBnPS_16M              0x00004000
 859#define TLBnPS_32M              0x00008000
 860#define TLBnPS_64M              0x00010000
 861#define TLBnPS_128M             0x00020000
 862#define TLBnPS_256M             0x00040000
 863#define TLBnPS_512M             0x00080000
 864#define TLBnPS_1G               0x00100000
 865#define TLBnPS_2G               0x00200000
 866#define TLBnPS_4G               0x00400000
 867#define TLBnPS_8G               0x00800000
 868#define TLBnPS_16G              0x01000000
 869#define TLBnPS_32G              0x02000000
 870#define TLBnPS_64G              0x04000000
 871#define TLBnPS_128G             0x08000000
 872#define TLBnPS_256G             0x10000000
 873
 874/* tlbilx action encoding */
 875#define TLBILX_T_ALL                    0
 876#define TLBILX_T_TID                    1
 877#define TLBILX_T_FULLMATCH              3
 878#define TLBILX_T_CLASS0                 4
 879#define TLBILX_T_CLASS1                 5
 880#define TLBILX_T_CLASS2                 6
 881#define TLBILX_T_CLASS3                 7
 882
 883/* BookE 2.06 helper defines */
 884
 885#define BOOKE206_FLUSH_TLB0    (1 << 0)
 886#define BOOKE206_FLUSH_TLB1    (1 << 1)
 887#define BOOKE206_FLUSH_TLB2    (1 << 2)
 888#define BOOKE206_FLUSH_TLB3    (1 << 3)
 889
 890/* number of possible TLBs */
 891#define BOOKE206_MAX_TLBN      4
 892
 893#define EPID_EPID_SHIFT 0x0
 894#define EPID_EPID 0xFF
 895#define EPID_ELPID_SHIFT 0x10
 896#define EPID_ELPID 0x3F0000
 897#define EPID_EGS 0x20000000
 898#define EPID_EGS_SHIFT 29
 899#define EPID_EAS 0x40000000
 900#define EPID_EAS_SHIFT 30
 901#define EPID_EPR 0x80000000
 902#define EPID_EPR_SHIFT 31
 903/* We don't support EGS and ELPID */
 904#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
 905
 906/*****************************************************************************/
 907/* Server and Embedded Processor Control */
 908
 909#define DBELL_TYPE_SHIFT               27
 910#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 911#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 912#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 913#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 914#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 915#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 916
 917#define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
 918
 919#define DBELL_BRDCAST                  PPC_BIT(37)
 920#define DBELL_LPIDTAG_SHIFT            14
 921#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 922#define DBELL_PIRTAG_MASK              0x3fff
 923
 924#define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
 925
 926#define PPC_PAGE_SIZES_MAX_SZ   8
 927
 928struct ppc_radix_page_info {
 929    uint32_t count;
 930    uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
 931};
 932
 933/*****************************************************************************/
 934/* The whole PowerPC CPU context */
 935
 936/*
 937 * PowerPC needs eight modes for different hypervisor/supervisor/guest
 938 * + real/paged mode combinations. The other two modes are for
 939 * external PID load/store.
 940 */
 941#define MMU_MODE8_SUFFIX _epl
 942#define MMU_MODE9_SUFFIX _eps
 943#define PPC_TLB_EPID_LOAD 8
 944#define PPC_TLB_EPID_STORE 9
 945
 946#define PPC_CPU_OPCODES_LEN          0x40
 947#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 948
 949struct CPUPPCState {
 950    /*
 951     * First are the most commonly used resources during translated
 952     * code execution
 953     */
 954    /* general purpose registers */
 955    target_ulong gpr[32];
 956    /* Storage for GPR MSB, used by the SPE extension */
 957    target_ulong gprh[32];
 958    /* LR */
 959    target_ulong lr;
 960    /* CTR */
 961    target_ulong ctr;
 962    /* condition register */
 963    uint32_t crf[8];
 964#if defined(TARGET_PPC64)
 965    /* CFAR */
 966    target_ulong cfar;
 967#endif
 968    /* XER (with SO, OV, CA split out) */
 969    target_ulong xer;
 970    target_ulong so;
 971    target_ulong ov;
 972    target_ulong ca;
 973    target_ulong ov32;
 974    target_ulong ca32;
 975    /* Reservation address */
 976    target_ulong reserve_addr;
 977    /* Reservation value */
 978    target_ulong reserve_val;
 979    target_ulong reserve_val2;
 980
 981    /* Those ones are used in supervisor mode only */
 982    /* machine state register */
 983    target_ulong msr;
 984    /* temporary general purpose registers */
 985    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 986
 987    /* Floating point execution context */
 988    float_status fp_status;
 989    /* floating point status and control register */
 990    target_ulong fpscr;
 991
 992    /* Next instruction pointer */
 993    target_ulong nip;
 994
 995    /* High part of 128-bit helper return.  */
 996    uint64_t retxh;
 997
 998    /* when a memory exception occurs, the access type is stored here */
 999    int access_type;
1000

1001    /* MMU context - only relevant for full system emulation */
1002#if !defined(CONFIG_USER_ONLY)
1003#if defined(TARGET_PPC64)
1004    /* PowerPC 64 SLB area */
1005    ppc_slb_t slb[MAX_SLB_ENTRIES];
1006    /* tcg TLB needs flush (deferred slb inval instruction typically) */
1007#endif
1008    /* segment registers */
1009    target_ulong sr[32];
1010    /* BATs */
1011    uint32_t nb_BATs;
1012    target_ulong DBAT[2][8];
1013    target_ulong IBAT[2][8];
1014    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1015    int32_t nb_tlb;      /* Total number of TLB                              */
1016    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1017    int nb_ways;     /* Number of ways in the TLB set                        */
1018    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1019    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1020    int nb_pids;     /* Number of available PID registers                    */
1021    int tlb_type;    /* Type of TLB we're dealing with                       */
1022    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1023    /* 403 dedicated access protection registers */
1024    target_ulong pb[4];
1025    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1026    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1027    uint32_t tlb_need_flush; /* Delayed flush needed */
1028#define TLB_NEED_LOCAL_FLUSH   0x1
1029#define TLB_NEED_GLOBAL_FLUSH  0x2
1030#endif
1031
1032    /* Other registers */
1033    /* Special purpose registers */
1034    target_ulong spr[1024];
1035    ppc_spr_t spr_cb[1024];
1036    /* Vector status and control register, minus VSCR_SAT.  */
1037    uint32_t vscr;
1038    /* VSX registers (including FP and AVR) */
1039    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1040    /* Non-zero if and only if VSCR_SAT should be set.  */
1041    ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1042    /* SPE registers */
1043    uint64_t spe_acc;
1044    uint32_t spe_fscr;
1045    /*
1046     * SPE and Altivec can share a status since they will never be
1047     * used simultaneously
1048     */
1049    float_status vec_status;
1050
1051    /* Internal devices resources */
1052    /* Time base and decrementer */
1053    ppc_tb_t *tb_env;
1054    /* Device control registers */
1055    ppc_dcr_t *dcr_env;
1056
1057    int dcache_line_size;
1058    int icache_line_size;
1059
1060    /* Those resources are used during exception processing */
1061    /* CPU model definition */
1062    target_ulong msr_mask;
1063    powerpc_mmu_t mmu_model;
1064    powerpc_excp_t excp_model;
1065    powerpc_input_t bus_model;
1066    int bfd_mach;
1067    uint32_t flags;
1068    uint64_t insns_flags;
1069    uint64_t insns_flags2;
1070#if defined(TARGET_PPC64)
1071    ppc_slb_t vrma_slb;
1072    target_ulong rmls;
1073#endif
1074
1075    int error_code;
1076    uint32_t pending_interrupts;
1077#if !defined(CONFIG_USER_ONLY)
1078    /*
1079     * This is the IRQ controller, which is implementation dependent
1080     * and only relevant when emulating a complete machine.
1081     */
1082    uint32_t irq_input_state;
1083    void **irq_inputs;
1084    /* Exception vectors */
1085    target_ulong excp_vectors[POWERPC_EXCP_NB];
1086    target_ulong excp_prefix;
1087    target_ulong ivor_mask;
1088    target_ulong ivpr_mask;
1089    target_ulong hreset_vector;
1090    hwaddr mpic_iack;
1091    /* true when the external proxy facility mode is enabled */
1092    bool mpic_proxy;
1093    /*
1094     * set when the processor has an HV mode, thus HV priv
1095     * instructions and SPRs are diallowed if MSR:HV is 0
1096     */
1097    bool has_hv_mode;
1098
1099    /*
1100     * On P7/P8/P9, set when in PM state, we need to handle resume in
1101     * a special way (such as routing some resume causes to 0x100, ie,
1102     * sreset), so flag this here.
1103     */
1104    bool resume_as_sreset;
1105#endif
1106
1107    /* Those resources are used only during code translation */
1108    /* opcode handlers */
1109    opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1110
1111    /* Those resources are used only in QEMU core */
1112    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1113    target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1114    int immu_idx;         /* precomputed MMU index to speed up insn access */
1115    int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1116
1117    /* Power management */
1118    int (*check_pow)(CPUPPCState *env);
1119
1120#if !defined(CONFIG_USER_ONLY)
1121    void *load_info;    /* Holds boot loading state.  */
1122#endif
1123
1124    /* booke timers */
1125
1126    /*
1127     * Specifies bit locations of the Time Base used to signal a fixed
1128     * timer exception on a transition from 0 to 1. (watchdog or
1129     * fixed-interval timer)
1130     *
1131     * 0 selects the least significant bit.
1132     * 63 selects the most significant bit.
1133     */
1134    uint8_t fit_period[4];
1135    uint8_t wdt_period[4];
1136
1137    /* Transactional memory state */
1138    target_ulong tm_gpr[32];
1139    ppc_avr_t tm_vsr[64];
1140    uint64_t tm_cr;
1141    uint64_t tm_lr;
1142    uint64_t tm_ctr;
1143    uint64_t tm_fpscr;
1144    uint64_t tm_amr;
1145    uint64_t tm_ppr;
1146    uint64_t tm_vrsave;
1147    uint32_t tm_vscr;
1148    uint64_t tm_dscr;
1149    uint64_t tm_tar;
1150};
1151
1152#define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1153do {                                            \
1154    env->fit_period[0] = (a_);                  \
1155    env->fit_period[1] = (b_);                  \
1156    env->fit_period[2] = (c_);                  \
1157    env->fit_period[3] = (d_);                  \
1158 } while (0)
1159
1160#define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1161do {                                            \
1162    env->wdt_period[0] = (a_);                  \
1163    env->wdt_period[1] = (b_);                  \
1164    env->wdt_period[2] = (c_);                  \
1165    env->wdt_period[3] = (d_);                  \
1166 } while (0)
1167
1168typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1169typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1170
1171/**
1172 * PowerPCCPU:
1173 * @env: #CPUPPCState
1174 * @vcpu_id: vCPU identifier given to KVM
1175 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1176 *
1177 * A PowerPC CPU.
1178 */
1179struct PowerPCCPU {
1180    /*< private >*/
1181    CPUState parent_obj;
1182    /*< public >*/
1183
1184    CPUNegativeOffsetState neg;
1185    CPUPPCState env;
1186
1187    int vcpu_id;
1188    uint32_t compat_pvr;
1189    PPCVirtualHypervisor *vhyp;
1190    void *machine_data;
1191    int32_t node_id; /* NUMA node this CPU belongs to */
1192    PPCHash64Options *hash64_opts;
1193
1194    /* Fields related to migration compatibility hacks */
1195    bool pre_2_8_migration;
1196    target_ulong mig_msr_mask;
1197    uint64_t mig_insns_flags;
1198    uint64_t mig_insns_flags2;
1199    uint32_t mig_nb_BATs;
1200    bool pre_2_10_migration;
1201    bool pre_3_0_migration;
1202    int32_t mig_slb_nr;
1203};
1204
1205
1206PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1207PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1208PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1209
1210struct PPCVirtualHypervisor {
1211    Object parent;
1212};
1213
1214struct PPCVirtualHypervisorClass {
1215    InterfaceClass parent;
1216    void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1217    hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1218    const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1219                                         hwaddr ptex, int n);
1220    void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1221                        const ppc_hash_pte64_t *hptes,
1222                        hwaddr ptex, int n);
1223    void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1224    void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1225    void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1226    target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1227};
1228
1229#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1230#define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1231    OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1232#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1233    OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1234                       TYPE_PPC_VIRTUAL_HYPERVISOR)
1235#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1236    OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1237                     TYPE_PPC_VIRTUAL_HYPERVISOR)
1238
1239void ppc_cpu_do_interrupt(CPUState *cpu);
1240bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1241void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1242void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
1243hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1244int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1245int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1246int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1247int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1248#ifndef CONFIG_USER_ONLY
1249void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1250const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1251#endif
1252int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1253                               int cpuid, void *opaque);
1254int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1255                               int cpuid, void *opaque);
1256#ifndef CONFIG_USER_ONLY
1257void ppc_cpu_do_system_reset(CPUState *cs);
1258extern const struct VMStateDescription vmstate_ppc_cpu;
1259#endif
1260
1261/*****************************************************************************/
1262void ppc_translate_init(void);
1263/*
1264 * you can call this signal handler from your SIGBUS and SIGSEGV
1265 * signal handlers to inform the virtual CPU of exceptions. non zero
1266 * is returned if the signal was handled by the virtual CPU.
1267 */
1268int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
1269bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1270                      MMUAccessType access_type, int mmu_idx,
1271                      bool probe, uintptr_t retaddr);
1272
1273#if !defined(CONFIG_USER_ONLY)
1274void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1275void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1276#endif /* !defined(CONFIG_USER_ONLY) */
1277void ppc_store_msr(CPUPPCState *env, target_ulong value);
1278
1279void ppc_cpu_list(void);
1280
1281/* Time-base and decrementer management */
1282#ifndef NO_CPU_IO_DEFS
1283uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1284uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1285void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1286void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1287uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1288uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1289void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1290void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1291bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1292target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1293void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1294target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1295void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1296uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1297uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1298uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1299#if !defined(CONFIG_USER_ONLY)
1300void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1301void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1302target_ulong load_40x_pit(CPUPPCState *env);
1303void store_40x_pit(CPUPPCState *env, target_ulong val);
1304void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1305void store_40x_sler(CPUPPCState *env, uint32_t val);
1306void store_booke_tcr(CPUPPCState *env, target_ulong val);
1307void store_booke_tsr(CPUPPCState *env, target_ulong val);
1308void ppc_tlb_invalidate_all(CPUPPCState *env);
1309void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1310void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1311#endif
1312#endif
1313
1314void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1315
1316static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1317{
1318    uint64_t gprv;
1319
1320    gprv = env->gpr[gprn];
1321    if (env->flags & POWERPC_FLAG_SPE) {
1322        /*
1323         * If the CPU implements the SPE extension, we have to get the
1324         * high bits of the GPR from the gprh storage area
1325         */
1326        gprv &= 0xFFFFFFFFULL;
1327        gprv |= (uint64_t)env->gprh[gprn] << 32;
1328    }
1329
1330    return gprv;
1331}
1332
1333/* Device control registers */
1334int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1335int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1336
1337#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1338#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1339#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1340
1341#define cpu_signal_handler cpu_ppc_signal_handler
1342#define cpu_list ppc_cpu_list
1343
1344/* MMU modes definitions */
1345#define MMU_USER_IDX 0
1346static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1347{
1348    return ifetch ? env->immu_idx : env->dmmu_idx;
1349}
1350
1351/* Compatibility modes */
1352#if defined(TARGET_PPC64)
1353bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1354                      uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1355bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1356                           uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1357
1358void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1359
1360#if !defined(CONFIG_USER_ONLY)
1361void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1362#endif
1363int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1364void ppc_compat_add_property(Object *obj, const char *name,
1365                             uint32_t *compat_pvr, const char *basedesc,
1366                             Error **errp);
1367#endif /* defined(TARGET_PPC64) */
1368
1369typedef CPUPPCState CPUArchState;
1370typedef PowerPCCPU ArchCPU;
1371
1372#include "exec/cpu-all.h"
1373
1374/*****************************************************************************/
1375/* CRF definitions */
1376#define CRF_LT_BIT    3
1377#define CRF_GT_BIT    2
1378#define CRF_EQ_BIT    1
1379#define CRF_SO_BIT    0
1380#define CRF_LT        (1 << CRF_LT_BIT)
1381#define CRF_GT        (1 << CRF_GT_BIT)
1382#define CRF_EQ        (1 << CRF_EQ_BIT)
1383#define CRF_SO        (1 << CRF_SO_BIT)
1384/* For SPE extensions */
1385#define CRF_CH        (1 << CRF_LT_BIT)
1386#define CRF_CL        (1 << CRF_GT_BIT)
1387#define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1388#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1389
1390/* XER definitions */
1391#define XER_SO  31
1392#define XER_OV  30
1393#define XER_CA  29
1394#define XER_OV32  19
1395#define XER_CA32  18
1396#define XER_CMP  8
1397#define XER_BC   0
1398#define xer_so  (env->so)
1399#define xer_ov  (env->ov)
1400#define xer_ca  (env->ca)
1401#define xer_ov32  (env->ov)
1402#define xer_ca32  (env->ca)
1403#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1404#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1405
1406/* SPR definitions */
1407#define SPR_MQ                (0x000)
1408#define SPR_XER               (0x001)
1409#define SPR_601_VRTCU         (0x004)
1410#define SPR_601_VRTCL         (0x005)
1411#define SPR_601_UDECR         (0x006)
1412#define SPR_LR                (0x008)
1413#define SPR_CTR               (0x009)
1414#define SPR_UAMR              (0x00D)
1415#define SPR_DSCR              (0x011)
1416#define SPR_DSISR             (0x012)
1417#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1418#define SPR_601_RTCU          (0x014)
1419#define SPR_601_RTCL          (0x015)
1420#define SPR_DECR              (0x016)
1421#define SPR_SDR1              (0x019)
1422#define SPR_SRR0              (0x01A)
1423#define SPR_SRR1              (0x01B)
1424#define SPR_CFAR              (0x01C)
1425#define SPR_AMR               (0x01D)
1426#define SPR_ACOP              (0x01F)
1427#define SPR_BOOKE_PID         (0x030)
1428#define SPR_BOOKS_PID         (0x030)
1429#define SPR_BOOKE_DECAR       (0x036)
1430#define SPR_BOOKE_CSRR0       (0x03A)
1431#define SPR_BOOKE_CSRR1       (0x03B)
1432#define SPR_BOOKE_DEAR        (0x03D)
1433#define SPR_IAMR              (0x03D)
1434#define SPR_BOOKE_ESR         (0x03E)
1435#define SPR_BOOKE_IVPR        (0x03F)
1436#define SPR_MPC_EIE           (0x050)
1437#define SPR_MPC_EID           (0x051)
1438#define SPR_MPC_NRI           (0x052)
1439#define SPR_TFHAR             (0x080)
1440#define SPR_TFIAR             (0x081)
1441#define SPR_TEXASR            (0x082)
1442#define SPR_TEXASRU           (0x083)
1443#define SPR_UCTRL             (0x088)
1444#define SPR_TIDR              (0x090)
1445#define SPR_MPC_CMPA          (0x090)
1446#define SPR_MPC_CMPB          (0x091)
1447#define SPR_MPC_CMPC          (0x092)
1448#define SPR_MPC_CMPD          (0x093)
1449#define SPR_MPC_ECR           (0x094)
1450#define SPR_MPC_DER           (0x095)
1451#define SPR_MPC_COUNTA        (0x096)
1452#define SPR_MPC_COUNTB        (0x097)
1453#define SPR_CTRL              (0x098)
1454#define SPR_MPC_CMPE          (0x098)
1455#define SPR_MPC_CMPF          (0x099)
1456#define SPR_FSCR              (0x099)
1457#define SPR_MPC_CMPG          (0x09A)
1458#define SPR_MPC_CMPH          (0x09B)
1459#define SPR_MPC_LCTRL1        (0x09C)
1460#define SPR_MPC_LCTRL2        (0x09D)
1461#define SPR_UAMOR             (0x09D)
1462#define SPR_MPC_ICTRL         (0x09E)
1463#define SPR_MPC_BAR           (0x09F)
1464#define SPR_PSPB              (0x09F)
1465#define SPR_DAWR              (0x0B4)
1466#define SPR_RPR               (0x0BA)
1467#define SPR_CIABR             (0x0BB)
1468#define SPR_DAWRX             (0x0BC)
1469#define SPR_HFSCR             (0x0BE)
1470#define SPR_VRSAVE            (0x100)
1471#define SPR_USPRG0            (0x100)
1472#define SPR_USPRG1            (0x101)
1473#define SPR_USPRG2            (0x102)
1474#define SPR_USPRG3            (0x103)
1475#define SPR_USPRG4            (0x104)
1476#define SPR_USPRG5            (0x105)
1477#define SPR_USPRG6            (0x106)
1478#define SPR_USPRG7            (0x107)
1479#define SPR_VTBL              (0x10C)
1480#define SPR_VTBU              (0x10D)
1481#define SPR_SPRG0             (0x110)
1482#define SPR_SPRG1             (0x111)
1483#define SPR_SPRG2             (0x112)
1484#define SPR_SPRG3             (0x113)
1485#define SPR_SPRG4             (0x114)
1486#define SPR_SCOMC             (0x114)
1487#define SPR_SPRG5             (0x115)
1488#define SPR_SCOMD             (0x115)
1489#define SPR_SPRG6             (0x116)
1490#define SPR_SPRG7             (0x117)
1491#define SPR_ASR               (0x118)
1492#define SPR_EAR               (0x11A)
1493#define SPR_TBL               (0x11C)
1494#define SPR_TBU               (0x11D)
1495#define SPR_TBU40             (0x11E)
1496#define SPR_SVR               (0x11E)
1497#define SPR_BOOKE_PIR         (0x11E)
1498#define SPR_PVR               (0x11F)
1499#define SPR_HSPRG0            (0x130)
1500#define SPR_BOOKE_DBSR        (0x130)
1501#define SPR_HSPRG1            (0x131)
1502#define SPR_HDSISR            (0x132)
1503#define SPR_HDAR              (0x133)
1504#define SPR_BOOKE_EPCR        (0x133)
1505#define SPR_SPURR             (0x134)
1506#define SPR_BOOKE_DBCR0       (0x134)
1507#define SPR_IBCR              (0x135)
1508#define SPR_PURR              (0x135)
1509#define SPR_BOOKE_DBCR1       (0x135)
1510#define SPR_DBCR              (0x136)
1511#define SPR_HDEC              (0x136)
1512#define SPR_BOOKE_DBCR2       (0x136)
1513#define SPR_HIOR              (0x137)
1514#define SPR_MBAR              (0x137)
1515#define SPR_RMOR              (0x138)
1516#define SPR_BOOKE_IAC1        (0x138)
1517#define SPR_HRMOR             (0x139)
1518#define SPR_BOOKE_IAC2        (0x139)
1519#define SPR_HSRR0             (0x13A)
1520#define SPR_BOOKE_IAC3        (0x13A)
1521#define SPR_HSRR1             (0x13B)
1522#define SPR_BOOKE_IAC4        (0x13B)
1523#define SPR_BOOKE_DAC1        (0x13C)
1524#define SPR_MMCRH             (0x13C)
1525#define SPR_DABR2             (0x13D)
1526#define SPR_BOOKE_DAC2        (0x13D)
1527#define SPR_TFMR              (0x13D)
1528#define SPR_BOOKE_DVC1        (0x13E)
1529#define SPR_LPCR              (0x13E)
1530#define SPR_BOOKE_DVC2        (0x13F)
1531#define SPR_LPIDR             (0x13F)
1532#define SPR_BOOKE_TSR         (0x150)
1533#define SPR_HMER              (0x150)
1534#define SPR_HMEER             (0x151)
1535#define SPR_PCR               (0x152)
1536#define SPR_BOOKE_LPIDR       (0x152)
1537#define SPR_BOOKE_TCR         (0x154)
1538#define SPR_BOOKE_TLB0PS      (0x158)
1539#define SPR_BOOKE_TLB1PS      (0x159)
1540#define SPR_BOOKE_TLB2PS      (0x15A)
1541#define SPR_BOOKE_TLB3PS      (0x15B)
1542#define SPR_AMOR              (0x15D)
1543#define SPR_BOOKE_MAS7_MAS3   (0x174)
1544#define SPR_BOOKE_IVOR0       (0x190)
1545#define SPR_BOOKE_IVOR1       (0x191)
1546#define SPR_BOOKE_IVOR2       (0x192)
1547#define SPR_BOOKE_IVOR3       (0x193)
1548#define SPR_BOOKE_IVOR4       (0x194)
1549#define SPR_BOOKE_IVOR5       (0x195)
1550#define SPR_BOOKE_IVOR6       (0x196)
1551#define SPR_BOOKE_IVOR7       (0x197)
1552#define SPR_BOOKE_IVOR8       (0x198)
1553#define SPR_BOOKE_IVOR9       (0x199)
1554#define SPR_BOOKE_IVOR10      (0x19A)
1555#define SPR_BOOKE_IVOR11      (0x19B)
1556#define SPR_BOOKE_IVOR12      (0x19C)
1557#define SPR_BOOKE_IVOR13      (0x19D)
1558#define SPR_BOOKE_IVOR14      (0x19E)
1559#define SPR_BOOKE_IVOR15      (0x19F)
1560#define SPR_BOOKE_IVOR38      (0x1B0)
1561#define SPR_BOOKE_IVOR39      (0x1B1)
1562#define SPR_BOOKE_IVOR40      (0x1B2)
1563#define SPR_BOOKE_IVOR41      (0x1B3)
1564#define SPR_BOOKE_IVOR42      (0x1B4)
1565#define SPR_BOOKE_GIVOR2      (0x1B8)
1566#define SPR_BOOKE_GIVOR3      (0x1B9)
1567#define SPR_BOOKE_GIVOR4      (0x1BA)
1568#define SPR_BOOKE_GIVOR8      (0x1BB)
1569#define SPR_BOOKE_GIVOR13     (0x1BC)
1570#define SPR_BOOKE_GIVOR14     (0x1BD)
1571#define SPR_TIR               (0x1BE)
1572#define SPR_PTCR              (0x1D0)
1573#define SPR_BOOKE_SPEFSCR     (0x200)
1574#define SPR_Exxx_BBEAR        (0x201)
1575#define SPR_Exxx_BBTAR        (0x202)
1576#define SPR_Exxx_L1CFG0       (0x203)
1577#define SPR_Exxx_L1CFG1       (0x204)
1578#define SPR_Exxx_NPIDR        (0x205)
1579#define SPR_ATBL              (0x20E)
1580#define SPR_ATBU              (0x20F)
1581#define SPR_IBAT0U            (0x210)
1582#define SPR_BOOKE_IVOR32      (0x210)
1583#define SPR_RCPU_MI_GRA       (0x210)
1584#define SPR_IBAT0L            (0x211)
1585#define SPR_BOOKE_IVOR33      (0x211)
1586#define SPR_IBAT1U            (0x212)
1587#define SPR_BOOKE_IVOR34      (0x212)
1588#define SPR_IBAT1L            (0x213)
1589#define SPR_BOOKE_IVOR35      (0x213)
1590#define SPR_IBAT2U            (0x214)
1591#define SPR_BOOKE_IVOR36      (0x214)
1592#define SPR_IBAT2L            (0x215)
1593#define SPR_BOOKE_IVOR37      (0x215)
1594#define SPR_IBAT3U            (0x216)
1595#define SPR_IBAT3L            (0x217)
1596#define SPR_DBAT0U            (0x218)
1597#define SPR_RCPU_L2U_GRA      (0x218)
1598#define SPR_DBAT0L            (0x219)
1599#define SPR_DBAT1U            (0x21A)
1600#define SPR_DBAT1L            (0x21B)
1601#define SPR_DBAT2U            (0x21C)
1602#define SPR_DBAT2L            (0x21D)
1603#define SPR_DBAT3U            (0x21E)
1604#define SPR_DBAT3L            (0x21F)
1605#define SPR_IBAT4U            (0x230)
1606#define SPR_RPCU_BBCMCR       (0x230)
1607#define SPR_MPC_IC_CST        (0x230)
1608#define SPR_Exxx_CTXCR        (0x230)
1609#define SPR_IBAT4L            (0x231)
1610#define SPR_MPC_IC_ADR        (0x231)
1611#define SPR_Exxx_DBCR3        (0x231)
1612#define SPR_IBAT5U            (0x232)
1613#define SPR_MPC_IC_DAT        (0x232)
1614#define SPR_Exxx_DBCNT        (0x232)
1615#define SPR_IBAT5L            (0x233)
1616#define SPR_IBAT6U            (0x234)
1617#define SPR_IBAT6L            (0x235)
1618#define SPR_IBAT7U            (0x236)
1619#define SPR_IBAT7L            (0x237)
1620#define SPR_DBAT4U            (0x238)
1621#define SPR_RCPU_L2U_MCR      (0x238)
1622#define SPR_MPC_DC_CST        (0x238)
1623#define SPR_Exxx_ALTCTXCR     (0x238)
1624#define SPR_DBAT4L            (0x239)
1625#define SPR_MPC_DC_ADR        (0x239)
1626#define SPR_DBAT5U            (0x23A)
1627#define SPR_BOOKE_MCSRR0      (0x23A)
1628#define SPR_MPC_DC_DAT        (0x23A)
1629#define SPR_DBAT5L            (0x23B)
1630#define SPR_BOOKE_MCSRR1      (0x23B)
1631#define SPR_DBAT6U            (0x23C)
1632#define SPR_BOOKE_MCSR        (0x23C)
1633#define SPR_DBAT6L            (0x23D)
1634#define SPR_Exxx_MCAR         (0x23D)
1635#define SPR_DBAT7U            (0x23E)
1636#define SPR_BOOKE_DSRR0       (0x23E)
1637#define SPR_DBAT7L            (0x23F)
1638#define SPR_BOOKE_DSRR1       (0x23F)
1639#define SPR_BOOKE_SPRG8       (0x25C)
1640#define SPR_BOOKE_SPRG9       (0x25D)
1641#define SPR_BOOKE_MAS0        (0x270)
1642#define SPR_BOOKE_MAS1        (0x271)
1643#define SPR_BOOKE_MAS2        (0x272)
1644#define SPR_BOOKE_MAS3        (0x273)
1645#define SPR_BOOKE_MAS4        (0x274)
1646#define SPR_BOOKE_MAS5        (0x275)
1647#define SPR_BOOKE_MAS6        (0x276)
1648#define SPR_BOOKE_PID1        (0x279)
1649#define SPR_BOOKE_PID2        (0x27A)
1650#define SPR_MPC_DPDR          (0x280)
1651#define SPR_MPC_IMMR          (0x288)
1652#define SPR_BOOKE_TLB0CFG     (0x2B0)
1653#define SPR_BOOKE_TLB1CFG     (0x2B1)
1654#define SPR_BOOKE_TLB2CFG     (0x2B2)
1655#define SPR_BOOKE_TLB3CFG     (0x2B3)
1656#define SPR_BOOKE_EPR         (0x2BE)
1657#define SPR_PERF0             (0x300)
1658#define SPR_RCPU_MI_RBA0      (0x300)
1659#define SPR_MPC_MI_CTR        (0x300)
1660#define SPR_POWER_USIER       (0x300)
1661#define SPR_PERF1             (0x301)
1662#define SPR_RCPU_MI_RBA1      (0x301)
1663#define SPR_POWER_UMMCR2      (0x301)
1664#define SPR_PERF2             (0x302)
1665#define SPR_RCPU_MI_RBA2      (0x302)
1666#define SPR_MPC_MI_AP         (0x302)
1667#define SPR_POWER_UMMCRA      (0x302)
1668#define SPR_PERF3             (0x303)
1669#define SPR_RCPU_MI_RBA3      (0x303)
1670#define SPR_MPC_MI_EPN        (0x303)
1671#define SPR_POWER_UPMC1       (0x303)
1672#define SPR_PERF4             (0x304)
1673#define SPR_POWER_UPMC2       (0x304)
1674#define SPR_PERF5             (0x305)
1675#define SPR_MPC_MI_TWC        (0x305)
1676#define SPR_POWER_UPMC3       (0x305)
1677#define SPR_PERF6             (0x306)
1678#define SPR_MPC_MI_RPN        (0x306)
1679#define SPR_POWER_UPMC4       (0x306)
1680#define SPR_PERF7             (0x307)
1681#define SPR_POWER_UPMC5       (0x307)
1682#define SPR_PERF8             (0x308)
1683#define SPR_RCPU_L2U_RBA0     (0x308)
1684#define SPR_MPC_MD_CTR        (0x308)
1685#define SPR_POWER_UPMC6       (0x308)
1686#define SPR_PERF9             (0x309)
1687#define SPR_RCPU_L2U_RBA1     (0x309)
1688#define SPR_MPC_MD_CASID      (0x309)
1689#define SPR_970_UPMC7         (0X309)
1690#define SPR_PERFA             (0x30A)
1691#define SPR_RCPU_L2U_RBA2     (0x30A)
1692#define SPR_MPC_MD_AP         (0x30A)
1693#define SPR_970_UPMC8         (0X30A)
1694#define SPR_PERFB             (0x30B)
1695#define SPR_RCPU_L2U_RBA3     (0x30B)
1696#define SPR_MPC_MD_EPN        (0x30B)
1697#define SPR_POWER_UMMCR0      (0X30B)
1698#define SPR_PERFC             (0x30C)
1699#define SPR_MPC_MD_TWB        (0x30C)
1700#define SPR_POWER_USIAR       (0X30C)
1701#define SPR_PERFD             (0x30D)
1702#define SPR_MPC_MD_TWC        (0x30D)
1703#define SPR_POWER_USDAR       (0X30D)
1704#define SPR_PERFE             (0x30E)
1705#define SPR_MPC_MD_RPN        (0x30E)
1706#define SPR_POWER_UMMCR1      (0X30E)
1707#define SPR_PERFF             (0x30F)
1708#define SPR_MPC_MD_TW         (0x30F)
1709#define SPR_UPERF0            (0x310)
1710#define SPR_POWER_SIER        (0x310)
1711#define SPR_UPERF1            (0x311)
1712#define SPR_POWER_MMCR2       (0x311)
1713#define SPR_UPERF2            (0x312)
1714#define SPR_POWER_MMCRA       (0X312)
1715#define SPR_UPERF3            (0x313)
1716#define SPR_POWER_PMC1        (0X313)
1717#define SPR_UPERF4            (0x314)
1718#define SPR_POWER_PMC2        (0X314)
1719#define SPR_UPERF5            (0x315)
1720#define SPR_POWER_PMC3        (0X315)
1721#define SPR_UPERF6            (0x316)
1722#define SPR_POWER_PMC4        (0X316)
1723#define SPR_UPERF7            (0x317)
1724#define SPR_POWER_PMC5        (0X317)
1725#define SPR_UPERF8            (0x318)
1726#define SPR_POWER_PMC6        (0X318)
1727#define SPR_UPERF9            (0x319)
1728#define SPR_970_PMC7          (0X319)
1729#define SPR_UPERFA            (0x31A)
1730#define SPR_970_PMC8          (0X31A)
1731#define SPR_UPERFB            (0x31B)
1732#define SPR_POWER_MMCR0       (0X31B)
1733#define SPR_UPERFC            (0x31C)
1734#define SPR_POWER_SIAR        (0X31C)
1735#define SPR_UPERFD            (0x31D)
1736#define SPR_POWER_SDAR        (0X31D)
1737#define SPR_UPERFE            (0x31E)
1738#define SPR_POWER_MMCR1       (0X31E)
1739#define SPR_UPERFF            (0x31F)
1740#define SPR_RCPU_MI_RA0       (0x320)
1741#define SPR_MPC_MI_DBCAM      (0x320)
1742#define SPR_BESCRS            (0x320)
1743#define SPR_RCPU_MI_RA1       (0x321)
1744#define SPR_MPC_MI_DBRAM0     (0x321)
1745#define SPR_BESCRSU           (0x321)
1746#define SPR_RCPU_MI_RA2       (0x322)
1747#define SPR_MPC_MI_DBRAM1     (0x322)
1748#define SPR_BESCRR            (0x322)
1749#define SPR_RCPU_MI_RA3       (0x323)
1750#define SPR_BESCRRU           (0x323)
1751#define SPR_EBBHR             (0x324)
1752#define SPR_EBBRR             (0x325)
1753#define SPR_BESCR             (0x326)
1754#define SPR_RCPU_L2U_RA0      (0x328)
1755#define SPR_MPC_MD_DBCAM      (0x328)
1756#define SPR_RCPU_L2U_RA1      (0x329)
1757#define SPR_MPC_MD_DBRAM0     (0x329)
1758#define SPR_RCPU_L2U_RA2      (0x32A)
1759#define SPR_MPC_MD_DBRAM1     (0x32A)
1760#define SPR_RCPU_L2U_RA3      (0x32B)
1761#define SPR_TAR               (0x32F)
1762#define SPR_IC                (0x350)
1763#define SPR_VTB               (0x351)
1764#define SPR_MMCRC             (0x353)
1765#define SPR_PSSCR             (0x357)
1766#define SPR_440_INV0          (0x370)
1767#define SPR_440_INV1          (0x371)
1768#define SPR_440_INV2          (0x372)
1769#define SPR_440_INV3          (0x373)
1770#define SPR_440_ITV0          (0x374)
1771#define SPR_440_ITV1          (0x375)
1772#define SPR_440_ITV2          (0x376)
1773#define SPR_440_ITV3          (0x377)
1774#define SPR_440_CCR1          (0x378)
1775#define SPR_TACR              (0x378)
1776#define SPR_TCSCR             (0x379)
1777#define SPR_CSIGR             (0x37a)
1778#define SPR_DCRIPR            (0x37B)
1779#define SPR_POWER_SPMC1       (0x37C)
1780#define SPR_POWER_SPMC2       (0x37D)
1781#define SPR_POWER_MMCRS       (0x37E)
1782#define SPR_WORT              (0x37F)
1783#define SPR_PPR               (0x380)
1784#define SPR_750_GQR0          (0x390)
1785#define SPR_440_DNV0          (0x390)
1786#define SPR_750_GQR1          (0x391)
1787#define SPR_440_DNV1          (0x391)
1788#define SPR_750_GQR2          (0x392)
1789#define SPR_440_DNV2          (0x392)
1790#define SPR_750_GQR3          (0x393)
1791#define SPR_440_DNV3          (0x393)
1792#define SPR_750_GQR4          (0x394)
1793#define SPR_440_DTV0          (0x394)
1794#define SPR_750_GQR5          (0x395)
1795#define SPR_440_DTV1          (0x395)
1796#define SPR_750_GQR6          (0x396)
1797#define SPR_440_DTV2          (0x396)
1798#define SPR_750_GQR7          (0x397)
1799#define SPR_440_DTV3          (0x397)
1800#define SPR_750_THRM4         (0x398)
1801#define SPR_750CL_HID2        (0x398)
1802#define SPR_440_DVLIM         (0x398)
1803#define SPR_750_WPAR          (0x399)
1804#define SPR_440_IVLIM         (0x399)
1805#define SPR_TSCR              (0x399)
1806#define SPR_750_DMAU          (0x39A)
1807#define SPR_750_DMAL          (0x39B)
1808#define SPR_440_RSTCFG        (0x39B)
1809#define SPR_BOOKE_DCDBTRL     (0x39C)
1810#define SPR_BOOKE_DCDBTRH     (0x39D)
1811#define SPR_BOOKE_ICDBTRL     (0x39E)
1812#define SPR_BOOKE_ICDBTRH     (0x39F)
1813#define SPR_74XX_UMMCR2       (0x3A0)
1814#define SPR_7XX_UPMC5         (0x3A1)
1815#define SPR_7XX_UPMC6         (0x3A2)
1816#define SPR_UBAMR             (0x3A7)
1817#define SPR_7XX_UMMCR0        (0x3A8)
1818#define SPR_7XX_UPMC1         (0x3A9)
1819#define SPR_7XX_UPMC2         (0x3AA)
1820#define SPR_7XX_USIAR         (0x3AB)
1821#define SPR_7XX_UMMCR1        (0x3AC)
1822#define SPR_7XX_UPMC3         (0x3AD)
1823#define SPR_7XX_UPMC4         (0x3AE)
1824#define SPR_USDA              (0x3AF)
1825#define SPR_40x_ZPR           (0x3B0)
1826#define SPR_BOOKE_MAS7        (0x3B0)
1827#define SPR_74XX_MMCR2        (0x3B0)
1828#define SPR_7XX_PMC5          (0x3B1)
1829#define SPR_40x_PID           (0x3B1)
1830#define SPR_7XX_PMC6          (0x3B2)
1831#define SPR_440_MMUCR         (0x3B2)
1832#define SPR_4xx_CCR0          (0x3B3)
1833#define SPR_BOOKE_EPLC        (0x3B3)
1834#define SPR_405_IAC3          (0x3B4)
1835#define SPR_BOOKE_EPSC        (0x3B4)
1836#define SPR_405_IAC4          (0x3B5)
1837#define SPR_405_DVC1          (0x3B6)
1838#define SPR_405_DVC2          (0x3B7)
1839#define SPR_BAMR              (0x3B7)
1840#define SPR_7XX_MMCR0         (0x3B8)
1841#define SPR_7XX_PMC1          (0x3B9)
1842#define SPR_40x_SGR           (0x3B9)
1843#define SPR_7XX_PMC2          (0x3BA)
1844#define SPR_40x_DCWR          (0x3BA)
1845#define SPR_7XX_SIAR          (0x3BB)
1846#define SPR_405_SLER          (0x3BB)
1847#define SPR_7XX_MMCR1         (0x3BC)
1848#define SPR_405_SU0R          (0x3BC)
1849#define SPR_401_SKR           (0x3BC)
1850#define SPR_7XX_PMC3          (0x3BD)
1851#define SPR_405_DBCR1         (0x3BD)
1852#define SPR_7XX_PMC4          (0x3BE)
1853#define SPR_SDA               (0x3BF)
1854#define SPR_403_VTBL          (0x3CC)
1855#define SPR_403_VTBU          (0x3CD)
1856#define SPR_DMISS             (0x3D0)
1857#define SPR_DCMP              (0x3D1)
1858#define SPR_HASH1             (0x3D2)
1859#define SPR_HASH2             (0x3D3)
1860#define SPR_BOOKE_ICDBDR      (0x3D3)
1861#define SPR_TLBMISS           (0x3D4)
1862#define SPR_IMISS             (0x3D4)
1863#define SPR_40x_ESR           (0x3D4)
1864#define SPR_PTEHI             (0x3D5)
1865#define SPR_ICMP              (0x3D5)
1866#define SPR_40x_DEAR          (0x3D5)
1867#define SPR_PTELO             (0x3D6)
1868#define SPR_RPA               (0x3D6)
1869#define SPR_40x_EVPR          (0x3D6)
1870#define SPR_L3PM              (0x3D7)
1871#define SPR_403_CDBCR         (0x3D7)
1872#define SPR_L3ITCR0           (0x3D8)
1873#define SPR_TCR               (0x3D8)
1874#define SPR_40x_TSR           (0x3D8)
1875#define SPR_IBR               (0x3DA)
1876#define SPR_40x_TCR           (0x3DA)
1877#define SPR_ESASRR            (0x3DB)
1878#define SPR_40x_PIT           (0x3DB)
1879#define SPR_403_TBL           (0x3DC)
1880#define SPR_403_TBU           (0x3DD)
1881#define SPR_SEBR              (0x3DE)
1882#define SPR_40x_SRR2          (0x3DE)
1883#define SPR_SER               (0x3DF)
1884#define SPR_40x_SRR3          (0x3DF)
1885#define SPR_L3OHCR            (0x3E8)
1886#define SPR_L3ITCR1           (0x3E9)
1887#define SPR_L3ITCR2           (0x3EA)
1888#define SPR_L3ITCR3           (0x3EB)
1889#define SPR_HID0              (0x3F0)
1890#define SPR_40x_DBSR          (0x3F0)
1891#define SPR_HID1              (0x3F1)
1892#define SPR_IABR              (0x3F2)
1893#define SPR_40x_DBCR0         (0x3F2)
1894#define SPR_601_HID2          (0x3F2)
1895#define SPR_Exxx_L1CSR0       (0x3F2)
1896#define SPR_ICTRL             (0x3F3)
1897#define SPR_HID2              (0x3F3)
1898#define SPR_750CL_HID4        (0x3F3)
1899#define SPR_Exxx_L1CSR1       (0x3F3)
1900#define SPR_440_DBDR          (0x3F3)
1901#define SPR_LDSTDB            (0x3F4)
1902#define SPR_750_TDCL          (0x3F4)
1903#define SPR_40x_IAC1          (0x3F4)
1904#define SPR_MMUCSR0           (0x3F4)
1905#define SPR_970_HID4          (0x3F4)
1906#define SPR_DABR              (0x3F5)
1907#define DABR_MASK (~(target_ulong)0x7)
1908#define SPR_Exxx_BUCSR        (0x3F5)
1909#define SPR_40x_IAC2          (0x3F5)
1910#define SPR_601_HID5          (0x3F5)
1911#define SPR_40x_DAC1          (0x3F6)
1912#define SPR_MSSCR0            (0x3F6)
1913#define SPR_970_HID5          (0x3F6)
1914#define SPR_MSSSR0            (0x3F7)
1915#define SPR_MSSCR1            (0x3F7)
1916#define SPR_DABRX             (0x3F7)
1917#define SPR_40x_DAC2          (0x3F7)
1918#define SPR_MMUCFG            (0x3F7)
1919#define SPR_LDSTCR            (0x3F8)
1920#define SPR_L2PMCR            (0x3F8)
1921#define SPR_750FX_HID2        (0x3F8)
1922#define SPR_Exxx_L1FINV0      (0x3F8)
1923#define SPR_L2CR              (0x3F9)
1924#define SPR_L3CR              (0x3FA)
1925#define SPR_750_TDCH          (0x3FA)
1926#define SPR_IABR2             (0x3FA)
1927#define SPR_40x_DCCR          (0x3FA)
1928#define SPR_ICTC              (0x3FB)
1929#define SPR_40x_ICCR          (0x3FB)
1930#define SPR_THRM1             (0x3FC)
1931#define SPR_403_PBL1          (0x3FC)
1932#define SPR_SP                (0x3FD)
1933#define SPR_THRM2             (0x3FD)
1934#define SPR_403_PBU1          (0x3FD)
1935#define SPR_604_HID13         (0x3FD)
1936#define SPR_LT                (0x3FE)
1937#define SPR_THRM3             (0x3FE)
1938#define SPR_RCPU_FPECR        (0x3FE)
1939#define SPR_403_PBL2          (0x3FE)
1940#define SPR_PIR               (0x3FF)
1941#define SPR_403_PBU2          (0x3FF)
1942#define SPR_601_HID15         (0x3FF)
1943#define SPR_604_HID15         (0x3FF)
1944#define SPR_E500_SVR          (0x3FF)
1945
1946/* Disable MAS Interrupt Updates for Hypervisor */
1947#define EPCR_DMIUH            (1 << 22)
1948/* Disable Guest TLB Management Instructions */
1949#define EPCR_DGTMI            (1 << 23)
1950/* Guest Interrupt Computation Mode */
1951#define EPCR_GICM             (1 << 24)
1952/* Interrupt Computation Mode */
1953#define EPCR_ICM              (1 << 25)
1954/* Disable Embedded Hypervisor Debug */
1955#define EPCR_DUVD             (1 << 26)
1956/* Instruction Storage Interrupt Directed to Guest State */
1957#define EPCR_ISIGS            (1 << 27)
1958/* Data Storage Interrupt Directed to Guest State */
1959#define EPCR_DSIGS            (1 << 28)
1960/* Instruction TLB Error Interrupt Directed to Guest State */
1961#define EPCR_ITLBGS           (1 << 29)
1962/* Data TLB Error Interrupt Directed to Guest State */
1963#define EPCR_DTLBGS           (1 << 30)
1964/* External Input Interrupt Directed to Guest State */
1965#define EPCR_EXTGS            (1 << 31)
1966
1967#define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
1968#define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
1969#define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
1970#define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
1971#define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
1972
1973#define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
1974#define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
1975#define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
1976#define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
1977#define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
1978
1979/* HID0 bits */
1980#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1981#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1982#define HID0_NAP            (1 << 22)           /* pre-2.06 */
1983#define HID0_HILE           PPC_BIT(19) /* POWER8 */
1984#define HID0_POWER9_HILE    PPC_BIT(4)
1985
1986/*****************************************************************************/
1987/* PowerPC Instructions types definitions                                    */
1988enum {
1989    PPC_NONE           = 0x0000000000000000ULL,
1990    /* PowerPC base instructions set                                         */
1991    PPC_INSNS_BASE     = 0x0000000000000001ULL,
1992    /*   integer operations instructions                                     */
1993#define PPC_INTEGER PPC_INSNS_BASE
1994    /*   flow control instructions                                           */
1995#define PPC_FLOW    PPC_INSNS_BASE
1996    /*   virtual memory instructions                                         */
1997#define PPC_MEM     PPC_INSNS_BASE
1998    /*   ld/st with reservation instructions                                 */
1999#define PPC_RES     PPC_INSNS_BASE
2000    /*   spr/msr access instructions                                         */

2001#define PPC_MISC    PPC_INSNS_BASE
2002    /* Deprecated instruction sets                                           */
2003    /*   Original POWER instruction set                                      */
2004    PPC_POWER          = 0x0000000000000002ULL,
2005    /*   POWER2 instruction set extension                                    */
2006    PPC_POWER2         = 0x0000000000000004ULL,
2007    /*   Power RTC support                                                   */
2008    PPC_POWER_RTC      = 0x0000000000000008ULL,
2009    /*   Power-to-PowerPC bridge (601)                                       */
2010    PPC_POWER_BR       = 0x0000000000000010ULL,
2011    /* 64 bits PowerPC instruction set                                       */
2012    PPC_64B            = 0x0000000000000020ULL,
2013    /*   New 64 bits extensions (PowerPC 2.0x)                               */
2014    PPC_64BX           = 0x0000000000000040ULL,
2015    /*   64 bits hypervisor extensions                                       */
2016    PPC_64H            = 0x0000000000000080ULL,
2017    /*   New wait instruction (PowerPC 2.0x)                                 */
2018    PPC_WAIT           = 0x0000000000000100ULL,
2019    /*   Time base mftb instruction                                          */
2020    PPC_MFTB           = 0x0000000000000200ULL,
2021
2022    /* Fixed-point unit extensions                                           */
2023    /*   PowerPC 602 specific                                                */
2024    PPC_602_SPEC       = 0x0000000000000400ULL,
2025    /*   isel instruction                                                    */
2026    PPC_ISEL           = 0x0000000000000800ULL,
2027    /*   popcntb instruction                                                 */
2028    PPC_POPCNTB        = 0x0000000000001000ULL,
2029    /*   string load / store                                                 */
2030    PPC_STRING         = 0x0000000000002000ULL,
2031    /*   real mode cache inhibited load / store                              */
2032    PPC_CILDST         = 0x0000000000004000ULL,
2033
2034    /* Floating-point unit extensions                                        */
2035    /*   Optional floating point instructions                                */
2036    PPC_FLOAT          = 0x0000000000010000ULL,
2037    /* New floating-point extensions (PowerPC 2.0x)                          */
2038    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2039    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2040    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2041    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2042    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2043    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2044    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2045
2046    /* Vector/SIMD extensions                                                */
2047    /*   Altivec support                                                     */
2048    PPC_ALTIVEC        = 0x0000000001000000ULL,
2049    /*   PowerPC 2.03 SPE extension                                          */
2050    PPC_SPE            = 0x0000000002000000ULL,
2051    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2052    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2053    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2054    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2055
2056    /* Optional memory control instructions                                  */
2057    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2058    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2059    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2060    /*   sync instruction                                                    */
2061    PPC_MEM_SYNC       = 0x0000000080000000ULL,
2062    /*   eieio instruction                                                   */
2063    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2064
2065    /* Cache control instructions                                            */
2066    PPC_CACHE          = 0x0000000200000000ULL,
2067    /*   icbi instruction                                                    */
2068    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2069    /*   dcbz instruction                                                    */
2070    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2071    /*   dcba instruction                                                    */
2072    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2073    /*   Freescale cache locking instructions                                */
2074    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2075
2076    /* MMU related extensions                                                */
2077    /*   external control instructions                                       */
2078    PPC_EXTERN         = 0x0000010000000000ULL,
2079    /*   segment register access instructions                                */
2080    PPC_SEGMENT        = 0x0000020000000000ULL,
2081    /*   PowerPC 6xx TLB management instructions                             */
2082    PPC_6xx_TLB        = 0x0000040000000000ULL,
2083    /* PowerPC 74xx TLB management instructions                              */
2084    PPC_74xx_TLB       = 0x0000080000000000ULL,
2085    /*   PowerPC 40x TLB management instructions                             */
2086    PPC_40x_TLB        = 0x0000100000000000ULL,
2087    /*   segment register access instructions for PowerPC 64 "bridge"        */
2088    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2089    /*   SLB management                                                      */
2090    PPC_SLBI           = 0x0000400000000000ULL,
2091
2092    /* Embedded PowerPC dedicated instructions                               */
2093    PPC_WRTEE          = 0x0001000000000000ULL,
2094    /* PowerPC 40x exception model                                           */
2095    PPC_40x_EXCP       = 0x0002000000000000ULL,
2096    /* PowerPC 405 Mac instructions                                          */
2097    PPC_405_MAC        = 0x0004000000000000ULL,
2098    /* PowerPC 440 specific instructions                                     */
2099    PPC_440_SPEC       = 0x0008000000000000ULL,
2100    /* BookE (embedded) PowerPC specification                                */
2101    PPC_BOOKE          = 0x0010000000000000ULL,
2102    /* mfapidi instruction                                                   */
2103    PPC_MFAPIDI        = 0x0020000000000000ULL,
2104    /* tlbiva instruction                                                    */
2105    PPC_TLBIVA         = 0x0040000000000000ULL,
2106    /* tlbivax instruction                                                   */
2107    PPC_TLBIVAX        = 0x0080000000000000ULL,
2108    /* PowerPC 4xx dedicated instructions                                    */
2109    PPC_4xx_COMMON     = 0x0100000000000000ULL,
2110    /* PowerPC 40x ibct instructions                                         */
2111    PPC_40x_ICBT       = 0x0200000000000000ULL,
2112    /* rfmci is not implemented in all BookE PowerPC                         */
2113    PPC_RFMCI          = 0x0400000000000000ULL,
2114    /* rfdi instruction                                                      */
2115    PPC_RFDI           = 0x0800000000000000ULL,
2116    /* DCR accesses                                                          */
2117    PPC_DCR            = 0x1000000000000000ULL,
2118    /* DCR extended accesse                                                  */
2119    PPC_DCRX           = 0x2000000000000000ULL,
2120    /* user-mode DCR access, implemented in PowerPC 460                      */
2121    PPC_DCRUX          = 0x4000000000000000ULL,
2122    /* popcntw and popcntd instructions                                      */
2123    PPC_POPCNTWD       = 0x8000000000000000ULL,
2124
2125#define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2126                        | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2127                        | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2128                        | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2129                        | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2130                        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2131                        | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2132                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2133                        | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2134                        | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2135                        | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2136                        | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2137                        | PPC_CACHE | PPC_CACHE_ICBI \
2138                        | PPC_CACHE_DCBZ \
2139                        | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2140                        | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2141                        | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2142                        | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2143                        | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2144                        | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2145                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2146                        | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2147                        | PPC_POPCNTWD | PPC_CILDST)
2148
2149    /* extended type values */
2150
2151    /* BookE 2.06 PowerPC specification                                      */
2152    PPC2_BOOKE206      = 0x0000000000000001ULL,
2153    /* VSX (extensions to Altivec / VMX)                                     */
2154    PPC2_VSX           = 0x0000000000000002ULL,
2155    /* Decimal Floating Point (DFP)                                          */
2156    PPC2_DFP           = 0x0000000000000004ULL,
2157    /* Embedded.Processor Control                                            */
2158    PPC2_PRCNTL        = 0x0000000000000008ULL,
2159    /* Byte-reversed, indexed, double-word load and store                    */
2160    PPC2_DBRX          = 0x0000000000000010ULL,
2161    /* Book I 2.05 PowerPC specification                                     */
2162    PPC2_ISA205        = 0x0000000000000020ULL,
2163    /* VSX additions in ISA 2.07                                             */
2164    PPC2_VSX207        = 0x0000000000000040ULL,
2165    /* ISA 2.06B bpermd                                                      */
2166    PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2167    /* ISA 2.06B divide extended variants                                    */
2168    PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2169    /* ISA 2.06B larx/stcx. instructions                                     */
2170    PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2171    /* ISA 2.06B floating point integer conversion                           */
2172    PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2173    /* ISA 2.06B floating point test instructions                            */
2174    PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2175    /* ISA 2.07 bctar instruction                                            */
2176    PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2177    /* ISA 2.07 load/store quadword                                          */
2178    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2179    /* ISA 2.07 Altivec                                                      */
2180    PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2181    /* PowerISA 2.07 Book3s specification                                    */
2182    PPC2_ISA207S       = 0x0000000000008000ULL,
2183    /* Double precision floating point conversion for signed integer 64      */
2184    PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2185    /* Transactional Memory (ISA 2.07, Book II)                              */
2186    PPC2_TM            = 0x0000000000020000ULL,
2187    /* Server PM instructgions (ISA 2.06, Book III)                          */
2188    PPC2_PM_ISA206     = 0x0000000000040000ULL,
2189    /* POWER ISA 3.0                                                         */
2190    PPC2_ISA300        = 0x0000000000080000ULL,
2191
2192#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2193                        PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2194                        PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2195                        PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2196                        PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2197                        PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2198                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2199                        PPC2_ISA300)
2200};
2201
2202/*****************************************************************************/
2203/*
2204 * Memory access type :
2205 * may be needed for precise access rights control and precise exceptions.
2206 */
2207enum {
2208    /* 1 bit to define user level / supervisor access */
2209    ACCESS_USER  = 0x00,
2210    ACCESS_SUPER = 0x01,
2211    /* Type of instruction that generated the access */
2212    ACCESS_CODE  = 0x10, /* Code fetch access                */
2213    ACCESS_INT   = 0x20, /* Integer load/store access        */
2214    ACCESS_FLOAT = 0x30, /* floating point load/store access */
2215    ACCESS_RES   = 0x40, /* load/store with reservation      */
2216    ACCESS_EXT   = 0x50, /* external access                  */
2217    ACCESS_CACHE = 0x60, /* Cache manipulation               */
2218};
2219
2220/*
2221 * Hardware interrupt sources:
2222 *   all those exception can be raised simulteaneously
2223 */
2224/* Input pins definitions */
2225enum {
2226    /* 6xx bus input pins */
2227    PPC6xx_INPUT_HRESET     = 0,
2228    PPC6xx_INPUT_SRESET     = 1,
2229    PPC6xx_INPUT_CKSTP_IN   = 2,
2230    PPC6xx_INPUT_MCP        = 3,
2231    PPC6xx_INPUT_SMI        = 4,
2232    PPC6xx_INPUT_INT        = 5,
2233    PPC6xx_INPUT_TBEN       = 6,
2234    PPC6xx_INPUT_WAKEUP     = 7,
2235    PPC6xx_INPUT_NB,
2236};
2237
2238enum {
2239    /* Embedded PowerPC input pins */
2240    PPCBookE_INPUT_HRESET     = 0,
2241    PPCBookE_INPUT_SRESET     = 1,
2242    PPCBookE_INPUT_CKSTP_IN   = 2,
2243    PPCBookE_INPUT_MCP        = 3,
2244    PPCBookE_INPUT_SMI        = 4,
2245    PPCBookE_INPUT_INT        = 5,
2246    PPCBookE_INPUT_CINT       = 6,
2247    PPCBookE_INPUT_NB,
2248};
2249
2250enum {
2251    /* PowerPC E500 input pins */
2252    PPCE500_INPUT_RESET_CORE = 0,
2253    PPCE500_INPUT_MCK        = 1,
2254    PPCE500_INPUT_CINT       = 3,
2255    PPCE500_INPUT_INT        = 4,
2256    PPCE500_INPUT_DEBUG      = 6,
2257    PPCE500_INPUT_NB,
2258};
2259
2260enum {
2261    /* PowerPC 40x input pins */
2262    PPC40x_INPUT_RESET_CORE = 0,
2263    PPC40x_INPUT_RESET_CHIP = 1,
2264    PPC40x_INPUT_RESET_SYS  = 2,
2265    PPC40x_INPUT_CINT       = 3,
2266    PPC40x_INPUT_INT        = 4,
2267    PPC40x_INPUT_HALT       = 5,
2268    PPC40x_INPUT_DEBUG      = 6,
2269    PPC40x_INPUT_NB,
2270};
2271
2272enum {
2273    /* RCPU input pins */
2274    PPCRCPU_INPUT_PORESET   = 0,
2275    PPCRCPU_INPUT_HRESET    = 1,
2276    PPCRCPU_INPUT_SRESET    = 2,
2277    PPCRCPU_INPUT_IRQ0      = 3,
2278    PPCRCPU_INPUT_IRQ1      = 4,
2279    PPCRCPU_INPUT_IRQ2      = 5,
2280    PPCRCPU_INPUT_IRQ3      = 6,
2281    PPCRCPU_INPUT_IRQ4      = 7,
2282    PPCRCPU_INPUT_IRQ5      = 8,
2283    PPCRCPU_INPUT_IRQ6      = 9,
2284    PPCRCPU_INPUT_IRQ7      = 10,
2285    PPCRCPU_INPUT_NB,
2286};
2287
2288#if defined(TARGET_PPC64)
2289enum {
2290    /* PowerPC 970 input pins */
2291    PPC970_INPUT_HRESET     = 0,
2292    PPC970_INPUT_SRESET     = 1,
2293    PPC970_INPUT_CKSTP      = 2,
2294    PPC970_INPUT_TBEN       = 3,
2295    PPC970_INPUT_MCP        = 4,
2296    PPC970_INPUT_INT        = 5,
2297    PPC970_INPUT_THINT      = 6,
2298    PPC970_INPUT_NB,
2299};
2300
2301enum {
2302    /* POWER7 input pins */
2303    POWER7_INPUT_INT        = 0,
2304    /*
2305     * POWER7 probably has other inputs, but we don't care about them
2306     * for any existing machine.  We can wire these up when we need
2307     * them
2308     */
2309    POWER7_INPUT_NB,
2310};
2311
2312enum {
2313    /* POWER9 input pins */
2314    POWER9_INPUT_INT        = 0,
2315    POWER9_INPUT_HINT       = 1,
2316    POWER9_INPUT_NB,
2317};
2318#endif
2319
2320/* Hardware exceptions definitions */
2321enum {
2322    /* External hardware exception sources */
2323    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2324    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2325    PPC_INTERRUPT_MCK,            /* Machine check exception              */
2326    PPC_INTERRUPT_EXT,            /* External interrupt                   */
2327    PPC_INTERRUPT_SMI,            /* System management interrupt          */
2328    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2329    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2330    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2331    /* Internal hardware exception sources */
2332    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2333    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2334    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2335    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2336    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2337    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2338    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2339    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2340    PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2341    PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2342    PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
2343};
2344
2345/* Processor Compatibility mask (PCR) */
2346enum {
2347    PCR_COMPAT_2_05     = PPC_BIT(62),
2348    PCR_COMPAT_2_06     = PPC_BIT(61),
2349    PCR_COMPAT_2_07     = PPC_BIT(60),
2350    PCR_COMPAT_3_00     = PPC_BIT(59),
2351    PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2352    PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2353    PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2354};
2355
2356/* HMER/HMEER */
2357enum {
2358    HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2359    HMER_PROC_RECV_DONE         = PPC_BIT(2),
2360    HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2361    HMER_TFAC_ERROR             = PPC_BIT(4),
2362    HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2363    HMER_XSCOM_FAIL             = PPC_BIT(8),
2364    HMER_XSCOM_DONE             = PPC_BIT(9),
2365    HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2366    HMER_WARN_RISE              = PPC_BIT(14),
2367    HMER_WARN_FALL              = PPC_BIT(15),
2368    HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2369    HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2370    HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2371    HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2372};
2373
2374/* Alternate Interrupt Location (AIL) */
2375enum {
2376    AIL_NONE                = 0,
2377    AIL_RESERVED            = 1,
2378    AIL_0001_8000           = 2,
2379    AIL_C000_0000_0000_4000 = 3,
2380};
2381
2382/*****************************************************************************/
2383
2384#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2385target_ulong cpu_read_xer(CPUPPCState *env);
2386void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2387
2388/*
2389 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2390 * have PPC_SEGMENT_64B.
2391 */
2392#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2393
2394static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2395                                        target_ulong *cs_base, uint32_t *flags)
2396{
2397    *pc = env->nip;
2398    *cs_base = 0;
2399    *flags = env->hflags;
2400}
2401
2402void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2403void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2404                                      uintptr_t raddr);
2405void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2406                                       uint32_t error_code);
2407void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2408                                          uint32_t error_code, uintptr_t raddr);
2409
2410#if !defined(CONFIG_USER_ONLY)
2411static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2412{
2413    uintptr_t tlbml = (uintptr_t)tlbm;
2414    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2415
2416    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2417}
2418
2419static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2420{
2421    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2422    int r = tlbncfg & TLBnCFG_N_ENTRY;
2423    return r;
2424}
2425
2426static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2427{
2428    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2429    int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2430    return r;
2431}
2432
2433static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2434{
2435    int id = booke206_tlbm_id(env, tlbm);
2436    int end = 0;
2437    int i;
2438
2439    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2440        end += booke206_tlb_size(env, i);
2441        if (id < end) {
2442            return i;
2443        }
2444    }
2445
2446    cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2447    return 0;
2448}
2449
2450static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2451{
2452    int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2453    int tlbid = booke206_tlbm_id(env, tlb);
2454    return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2455}
2456
2457static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2458                                              target_ulong ea, int way)
2459{
2460    int r;
2461    uint32_t ways = booke206_tlb_ways(env, tlbn);
2462    int ways_bits = ctz32(ways);
2463    int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2464    int i;
2465
2466    way &= ways - 1;
2467    ea >>= MAS2_EPN_SHIFT;
2468    ea &= (1 << (tlb_bits - ways_bits)) - 1;
2469    r = (ea << ways_bits) | way;
2470
2471    if (r >= booke206_tlb_size(env, tlbn)) {
2472        return NULL;
2473    }
2474
2475    /* bump up to tlbn index */
2476    for (i = 0; i < tlbn; i++) {
2477        r += booke206_tlb_size(env, i);
2478    }
2479
2480    return &env->tlb.tlbm[r];
2481}
2482
2483/* returns bitmap of supported page sizes for a given TLB */
2484static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2485{
2486    uint32_t ret = 0;
2487
2488    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2489        /* MAV2 */
2490        ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2491    } else {
2492        uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2493        uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2494        uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2495        int i;
2496        for (i = min; i <= max; i++) {
2497            ret |= (1 << (i << 1));
2498        }
2499    }
2500
2501    return ret;
2502}
2503
2504static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2505                                            ppcmas_tlb_t *tlb)
2506{
2507    uint8_t i;
2508    int32_t tsize = -1;
2509
2510    for (i = 0; i < 32; i++) {
2511        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2512            if (tsize == -1) {
2513                tsize = i;
2514            } else {
2515                return;
2516            }
2517        }
2518    }
2519
2520    /* TLBnPS unimplemented? Odd.. */
2521    assert(tsize != -1);
2522    tlb->mas1 &= ~MAS1_TSIZE_MASK;
2523    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2524}
2525
2526#endif
2527
2528static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2529{
2530    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2531        return msr & (1ULL << MSR_CM);
2532    }
2533
2534    return msr & (1ULL << MSR_SF);
2535}
2536
2537/**
2538 * Check whether register rx is in the range between start and
2539 * start + nregs (as needed by the LSWX and LSWI instructions)
2540 */
2541static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2542{
2543    return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2544           (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2545}
2546
2547/* Accessors for FP, VMX and VSX registers */
2548#if defined(HOST_WORDS_BIGENDIAN)
2549#define VsrB(i) u8[i]
2550#define VsrSB(i) s8[i]
2551#define VsrH(i) u16[i]
2552#define VsrSH(i) s16[i]
2553#define VsrW(i) u32[i]
2554#define VsrSW(i) s32[i]
2555#define VsrD(i) u64[i]
2556#define VsrSD(i) s64[i]
2557#else
2558#define VsrB(i) u8[15 - (i)]
2559#define VsrSB(i) s8[15 - (i)]
2560#define VsrH(i) u16[7 - (i)]
2561#define VsrSH(i) s16[7 - (i)]
2562#define VsrW(i) u32[3 - (i)]
2563#define VsrSW(i) s32[3 - (i)]
2564#define VsrD(i) u64[1 - (i)]
2565#define VsrSD(i) s64[1 - (i)]
2566#endif
2567
2568static inline int vsr64_offset(int i, bool high)
2569{
2570    return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2571}
2572
2573static inline int vsr_full_offset(int i)
2574{
2575    return offsetof(CPUPPCState, vsr[i].u64[0]);
2576}
2577
2578static inline int fpr_offset(int i)
2579{
2580    return vsr64_offset(i, true);
2581}
2582
2583static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2584{
2585    return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2586}
2587
2588static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2589{
2590    return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2591}
2592
2593static inline long avr64_offset(int i, bool high)
2594{
2595    return vsr64_offset(i + 32, high);
2596}
2597
2598static inline int avr_full_offset(int i)
2599{
2600    return vsr_full_offset(i + 32);
2601}
2602
2603static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2604{
2605    return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2606}
2607
2608void dump_mmu(CPUPPCState *env);
2609
2610void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2611#endif /* PPC_CPU_H */
2612