1#ifndef MMU_HASH64_H
2#define MMU_HASH64_H
3
4#ifndef CONFIG_USER_ONLY
5
6#ifdef TARGET_PPC64
7void dump_slb(PowerPCCPU *cpu);
8int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
9 target_ulong esid, target_ulong vsid);
10hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
11int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
12 int mmu_idx);
13void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
14 target_ulong pte_index,
15 target_ulong pte0, target_ulong pte1);
16unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
17 uint64_t pte0, uint64_t pte1);
18void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
19void ppc_hash64_init(PowerPCCPU *cpu);
20void ppc_hash64_finalize(PowerPCCPU *cpu);
21void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
22 bool (*cb)(void *, uint32_t, uint32_t),
23 void *opaque);
24#endif
25
26
27
28
29
30
31#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
32#define SLB_ESID_V 0x0000000008000000ULL
33
34
35#define SLB_VSID_SHIFT 12
36#define SLB_VSID_SHIFT_1T 24
37#define SLB_VSID_SSIZE_SHIFT 62
38#define SLB_VSID_B 0xc000000000000000ULL
39#define SLB_VSID_B_256M 0x0000000000000000ULL
40#define SLB_VSID_B_1T 0x4000000000000000ULL
41#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
42#define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
43#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
44#define SLB_VSID_KS 0x0000000000000800ULL
45#define SLB_VSID_KP 0x0000000000000400ULL
46#define SLB_VSID_N 0x0000000000000200ULL
47#define SLB_VSID_L 0x0000000000000100ULL
48#define SLB_VSID_C 0x0000000000000080ULL
49#define SLB_VSID_LP 0x0000000000000030ULL
50#define SLB_VSID_ATTR 0x0000000000000FFFULL
51#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
52#define SLB_VSID_4K 0x0000000000000000ULL
53#define SLB_VSID_64K 0x0000000000000110ULL
54#define SLB_VSID_16M 0x0000000000000100ULL
55#define SLB_VSID_16G 0x0000000000000120ULL
56
57
58
59
60
61#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
62#define SDR_64_HTABSIZE 0x000000000000001FULL
63
64#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
65#define HPTES_PER_GROUP 8
66#define HASH_PTE_SIZE_64 16
67#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
68
69#define HPTE64_V_SSIZE SLB_VSID_B
70#define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
71#define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
72#define HPTE64_V_SSIZE_SHIFT 62
73#define HPTE64_V_AVPN_SHIFT 7
74#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
75#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
76#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
77#define HPTE64_V_BOLTED 0x0000000000000010ULL
78#define HPTE64_V_LARGE 0x0000000000000004ULL
79#define HPTE64_V_SECONDARY 0x0000000000000002ULL
80#define HPTE64_V_VALID 0x0000000000000001ULL
81
82#define HPTE64_R_PP0 0x8000000000000000ULL
83#define HPTE64_R_TS 0x4000000000000000ULL
84#define HPTE64_R_KEY_HI 0x3000000000000000ULL
85#define HPTE64_R_RPN_SHIFT 12
86#define HPTE64_R_RPN 0x0ffffffffffff000ULL
87#define HPTE64_R_FLAGS 0x00000000000003ffULL
88#define HPTE64_R_PP 0x0000000000000003ULL
89#define HPTE64_R_N 0x0000000000000004ULL
90#define HPTE64_R_G 0x0000000000000008ULL
91#define HPTE64_R_M 0x0000000000000010ULL
92#define HPTE64_R_I 0x0000000000000020ULL
93#define HPTE64_R_W 0x0000000000000040ULL
94#define HPTE64_R_WIMG 0x0000000000000078ULL
95#define HPTE64_R_C 0x0000000000000080ULL
96#define HPTE64_R_R 0x0000000000000100ULL
97#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
98#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
99 (((x) & HPTE64_R_KEY_LO) >> 9))
100
101#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
102#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
103
104
105#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
106#define HPTE64_R_3_0_SSIZE_SHIFT 58
107#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
108
109struct ppc_hash_pte64 {
110 uint64_t pte0, pte1;
111};
112
113const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
114 hwaddr ptex, int n);
115void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
116 hwaddr ptex, int n);
117
118static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
119 const ppc_hash_pte64_t *hptes, int i)
120{
121 return ldq_p(&(hptes[i].pte0));
122}
123
124static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
125 const ppc_hash_pte64_t *hptes, int i)
126{
127 return ldq_p(&(hptes[i].pte1));
128}
129
130
131
132
133
134struct PPCHash64PageSize {
135 uint32_t page_shift;
136 uint32_t pte_enc;
137};
138typedef struct PPCHash64PageSize PPCHash64PageSize;
139
140struct PPCHash64SegmentPageSizes {
141 uint32_t page_shift;
142 uint32_t slb_enc;
143 PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
144};
145
146struct PPCHash64Options {
147#define PPC_HASH64_1TSEG 0x00001
148#define PPC_HASH64_AMR 0x00002
149#define PPC_HASH64_CI_LARGEPAGE 0x00004
150 unsigned flags;
151 unsigned slb_size;
152 PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
153};
154
155extern const PPCHash64Options ppc_hash64_opts_basic;
156extern const PPCHash64Options ppc_hash64_opts_POWER7;
157
158static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
159{
160 return !!(cpu->hash64_opts->flags & feature);
161}
162
163#endif
164
165#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
166static inline void ppc_hash64_init(PowerPCCPU *cpu)
167{
168}
169static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
170{
171}
172#endif
173
174#endif
175
