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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "internal.h"
24#include "exec/gdbstub.h"
25#include "qemu/timer.h"
26#include "qemu/qemu-print.h"
27#include "hw/s390x/ioinst.h"
28#include "sysemu/hw_accel.h"
29#ifndef CONFIG_USER_ONLY
30#include "sysemu/sysemu.h"
31#include "sysemu/tcg.h"
32#endif
33
34#ifndef CONFIG_USER_ONLY
35void s390x_tod_timer(void *opaque)
36{
37 cpu_inject_clock_comparator((S390CPU *) opaque);
38}
39
40void s390x_cpu_timer(void *opaque)
41{
42 cpu_inject_cpu_timer((S390CPU *) opaque);
43}
44#endif
45
46#ifndef CONFIG_USER_ONLY
47
48hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
49{
50 S390CPU *cpu = S390_CPU(cs);
51 CPUS390XState *env = &cpu->env;
52 target_ulong raddr;
53 int prot;
54 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
55
56
57 if (!(env->psw.mask & PSW_MASK_64)) {
58 vaddr &= 0x7fffffff;
59 }
60
61 if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
62 return -1;
63 }
64 return raddr;
65}
66
67hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
68{
69 hwaddr phys_addr;
70 target_ulong page;
71
72 page = vaddr & TARGET_PAGE_MASK;
73 phys_addr = cpu_get_phys_page_debug(cs, page);
74 phys_addr += (vaddr & ~TARGET_PAGE_MASK);
75
76 return phys_addr;
77}
78
79static inline bool is_special_wait_psw(uint64_t psw_addr)
80{
81
82 return psw_addr == 0xfffUL;
83}
84
85void s390_handle_wait(S390CPU *cpu)
86{
87 CPUState *cs = CPU(cpu);
88
89 if (s390_cpu_halt(cpu) == 0) {
90#ifndef CONFIG_USER_ONLY
91 if (is_special_wait_psw(cpu->env.psw.addr)) {
92 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
93 } else {
94 cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT;
95 qemu_system_guest_panicked(cpu_get_crash_info(cs));
96 }
97#endif
98 }
99}
100
101void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
102{
103 uint64_t old_mask = env->psw.mask;
104
105 env->psw.addr = addr;
106 env->psw.mask = mask;
107
108
109 if (!tcg_enabled()) {
110 return;
111 }
112 env->cc_op = (mask >> 44) & 3;
113
114 if ((old_mask ^ mask) & PSW_MASK_PER) {
115 s390_cpu_recompute_watchpoints(env_cpu(env));
116 }
117
118 if (mask & PSW_MASK_WAIT) {
119 s390_handle_wait(env_archcpu(env));
120 }
121}
122
123uint64_t get_psw_mask(CPUS390XState *env)
124{
125 uint64_t r = env->psw.mask;
126
127 if (tcg_enabled()) {
128 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
129 env->cc_vr);
130
131 r &= ~PSW_MASK_CC;
132 assert(!(env->cc_op & ~3));
133 r |= (uint64_t)env->cc_op << 44;
134 }
135
136 return r;
137}
138
139LowCore *cpu_map_lowcore(CPUS390XState *env)
140{
141 LowCore *lowcore;
142 hwaddr len = sizeof(LowCore);
143
144 lowcore = cpu_physical_memory_map(env->psa, &len, 1);
145
146 if (len < sizeof(LowCore)) {
147 cpu_abort(env_cpu(env), "Could not map lowcore\n");
148 }
149
150 return lowcore;
151}
152
153void cpu_unmap_lowcore(LowCore *lowcore)
154{
155 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
156}
157
158void do_restart_interrupt(CPUS390XState *env)
159{
160 uint64_t mask, addr;
161 LowCore *lowcore;
162
163 lowcore = cpu_map_lowcore(env);
164
165 lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
166 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
167 mask = be64_to_cpu(lowcore->restart_new_psw.mask);
168 addr = be64_to_cpu(lowcore->restart_new_psw.addr);
169
170 cpu_unmap_lowcore(lowcore);
171 env->pending_int &= ~INTERRUPT_RESTART;
172
173 load_psw(env, mask, addr);
174}
175
176void s390_cpu_recompute_watchpoints(CPUState *cs)
177{
178 const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
179 S390CPU *cpu = S390_CPU(cs);
180 CPUS390XState *env = &cpu->env;
181
182
183
184 cpu_watchpoint_remove_all(cs, BP_CPU);
185
186
187 if (!(env->psw.mask & PSW_MASK_PER)) {
188 return;
189 }
190
191
192 if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
193 return;
194 }
195
196 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
197
198
199 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
200 cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
201 } else if (env->cregs[10] > env->cregs[11]) {
202
203 cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
204 wp_flags, NULL);
205 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
206
207 } else {
208
209 cpu_watchpoint_insert(cs, env->cregs[10],
210 env->cregs[11] - env->cregs[10] + 1,
211 wp_flags, NULL);
212 }
213}
214
215typedef struct SigpSaveArea {
216 uint64_t fprs[16];
217 uint64_t grs[16];
218 PSW psw;
219 uint8_t pad_0x0110[0x0118 - 0x0110];
220 uint32_t prefix;
221 uint32_t fpc;
222 uint8_t pad_0x0120[0x0124 - 0x0120];
223 uint32_t todpr;
224 uint64_t cputm;
225 uint64_t ckc;
226 uint8_t pad_0x0138[0x0140 - 0x0138];
227 uint32_t ars[16];
228 uint64_t crs[16];
229} SigpSaveArea;
230QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
231
232int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
233{
234 static const uint8_t ar_id = 1;
235 SigpSaveArea *sa;
236 hwaddr len = sizeof(*sa);
237 int i;
238
239 sa = cpu_physical_memory_map(addr, &len, 1);
240 if (!sa) {
241 return -EFAULT;
242 }
243 if (len != sizeof(*sa)) {
244 cpu_physical_memory_unmap(sa, len, 1, 0);
245 return -EFAULT;
246 }
247
248 if (store_arch) {
249 cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
250 }
251 for (i = 0; i < 16; ++i) {
252 sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i));
253 }
254 for (i = 0; i < 16; ++i) {
255 sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
256 }
257 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
258 sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env));
259 sa->prefix = cpu_to_be32(cpu->env.psa);
260 sa->fpc = cpu_to_be32(cpu->env.fpc);
261 sa->todpr = cpu_to_be32(cpu->env.todpr);
262 sa->cputm = cpu_to_be64(cpu->env.cputm);
263 sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
264 for (i = 0; i < 16; ++i) {
265 sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
266 }
267 for (i = 0; i < 16; ++i) {
268 sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
269 }
270
271 cpu_physical_memory_unmap(sa, len, 1, len);
272
273 return 0;
274}
275
276typedef struct SigpAdtlSaveArea {
277 uint64_t vregs[32][2];
278 uint8_t pad_0x0200[0x0400 - 0x0200];
279 uint64_t gscb[4];
280 uint8_t pad_0x0420[0x1000 - 0x0420];
281} SigpAdtlSaveArea;
282QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
283
284#define ADTL_GS_MIN_SIZE 2048
285int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
286{
287 SigpAdtlSaveArea *sa;
288 hwaddr save = len;
289 int i;
290
291 sa = cpu_physical_memory_map(addr, &save, 1);
292 if (!sa) {
293 return -EFAULT;
294 }
295 if (save != len) {
296 cpu_physical_memory_unmap(sa, len, 1, 0);
297 return -EFAULT;
298 }
299
300 if (s390_has_feat(S390_FEAT_VECTOR)) {
301 for (i = 0; i < 32; i++) {
302 sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]);
303 sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]);
304 }
305 }
306 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
307 for (i = 0; i < 4; i++) {
308 sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
309 }
310 }
311
312 cpu_physical_memory_unmap(sa, len, 1, len);
313 return 0;
314}
315#endif
316
317void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags)
318{
319 S390CPU *cpu = S390_CPU(cs);
320 CPUS390XState *env = &cpu->env;
321 int i;
322
323 if (env->cc_op > 3) {
324 qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
325 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
326 } else {
327 qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
328 env->psw.mask, env->psw.addr, env->cc_op);
329 }
330
331 for (i = 0; i < 16; i++) {
332 qemu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
333 if ((i % 4) == 3) {
334 qemu_fprintf(f, "\n");
335 } else {
336 qemu_fprintf(f, " ");
337 }
338 }
339
340 if (flags & CPU_DUMP_FPU) {
341 if (s390_has_feat(S390_FEAT_VECTOR)) {
342 for (i = 0; i < 32; i++) {
343 qemu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
344 i, env->vregs[i][0], env->vregs[i][1],
345 i % 2 ? '\n' : ' ');
346 }
347 } else {
348 for (i = 0; i < 16; i++) {
349 qemu_fprintf(f, "F%02d=%016" PRIx64 "%c",
350 i, *get_freg(env, i),
351 (i % 4) == 3 ? '\n' : ' ');
352 }
353 }
354 }
355
356#ifndef CONFIG_USER_ONLY
357 for (i = 0; i < 16; i++) {
358 qemu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
359 if ((i % 4) == 3) {
360 qemu_fprintf(f, "\n");
361 } else {
362 qemu_fprintf(f, " ");
363 }
364 }
365#endif
366
367#ifdef DEBUG_INLINE_BRANCHES
368 for (i = 0; i < CC_OP_MAX; i++) {
369 qemu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
370 inline_branch_miss[i], inline_branch_hit[i]);
371 }
372#endif
373
374 qemu_fprintf(f, "\n");
375}
376
377const char *cc_name(enum cc_op cc_op)
378{
379 static const char * const cc_names[] = {
380 [CC_OP_CONST0] = "CC_OP_CONST0",
381 [CC_OP_CONST1] = "CC_OP_CONST1",
382 [CC_OP_CONST2] = "CC_OP_CONST2",
383 [CC_OP_CONST3] = "CC_OP_CONST3",
384 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
385 [CC_OP_STATIC] = "CC_OP_STATIC",
386 [CC_OP_NZ] = "CC_OP_NZ",
387 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
388 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
389 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
390 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
391 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
392 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
393 [CC_OP_ADD_64] = "CC_OP_ADD_64",
394 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
395 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
396 [CC_OP_SUB_64] = "CC_OP_SUB_64",
397 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
398 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
399 [CC_OP_ABS_64] = "CC_OP_ABS_64",
400 [CC_OP_NABS_64] = "CC_OP_NABS_64",
401 [CC_OP_ADD_32] = "CC_OP_ADD_32",
402 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
403 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
404 [CC_OP_SUB_32] = "CC_OP_SUB_32",
405 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
406 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
407 [CC_OP_ABS_32] = "CC_OP_ABS_32",
408 [CC_OP_NABS_32] = "CC_OP_NABS_32",
409 [CC_OP_COMP_32] = "CC_OP_COMP_32",
410 [CC_OP_COMP_64] = "CC_OP_COMP_64",
411 [CC_OP_TM_32] = "CC_OP_TM_32",
412 [CC_OP_TM_64] = "CC_OP_TM_64",
413 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
414 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
415 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
416 [CC_OP_ICM] = "CC_OP_ICM",
417 [CC_OP_SLA_32] = "CC_OP_SLA_32",
418 [CC_OP_SLA_64] = "CC_OP_SLA_64",
419 [CC_OP_FLOGR] = "CC_OP_FLOGR",
420 [CC_OP_LCBB] = "CC_OP_LCBB",
421 [CC_OP_VC] = "CC_OP_VC",
422 };
423
424 return cc_names[cc_op];
425}
426
