LXR qemu/target/sparc/int32

   1/*
   2 * Sparc32 interrupt helpers
   3 *
   4 *  Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "cpu.h"
  22#include "trace.h"
  23#include "sysemu/sysemu.h"
  24#include "exec/log.h"
  25
  26#define DEBUG_PCALL
  27
  28#ifdef DEBUG_PCALL
  29static const char * const excp_names[0x80] = {
  30    [TT_TFAULT] = "Instruction Access Fault",
  31    [TT_ILL_INSN] = "Illegal Instruction",
  32    [TT_PRIV_INSN] = "Privileged Instruction",
  33    [TT_NFPU_INSN] = "FPU Disabled",
  34    [TT_WIN_OVF] = "Window Overflow",
  35    [TT_WIN_UNF] = "Window Underflow",
  36    [TT_UNALIGNED] = "Unaligned Memory Access",
  37    [TT_FP_EXCP] = "FPU Exception",
  38    [TT_DFAULT] = "Data Access Fault",
  39    [TT_TOVF] = "Tag Overflow",
  40    [TT_EXTINT | 0x1] = "External Interrupt 1",
  41    [TT_EXTINT | 0x2] = "External Interrupt 2",
  42    [TT_EXTINT | 0x3] = "External Interrupt 3",
  43    [TT_EXTINT | 0x4] = "External Interrupt 4",
  44    [TT_EXTINT | 0x5] = "External Interrupt 5",
  45    [TT_EXTINT | 0x6] = "External Interrupt 6",
  46    [TT_EXTINT | 0x7] = "External Interrupt 7",
  47    [TT_EXTINT | 0x8] = "External Interrupt 8",
  48    [TT_EXTINT | 0x9] = "External Interrupt 9",
  49    [TT_EXTINT | 0xa] = "External Interrupt 10",
  50    [TT_EXTINT | 0xb] = "External Interrupt 11",
  51    [TT_EXTINT | 0xc] = "External Interrupt 12",
  52    [TT_EXTINT | 0xd] = "External Interrupt 13",
  53    [TT_EXTINT | 0xe] = "External Interrupt 14",
  54    [TT_EXTINT | 0xf] = "External Interrupt 15",
  55    [TT_TOVF] = "Tag Overflow",
  56    [TT_CODE_ACCESS] = "Instruction Access Error",
  57    [TT_DATA_ACCESS] = "Data Access Error",
  58    [TT_DIV_ZERO] = "Division By Zero",
  59    [TT_NCP_INSN] = "Coprocessor Disabled",
  60};
  61#endif
  62
  63void sparc_cpu_do_interrupt(CPUState *cs)
  64{
  65    SPARCCPU *cpu = SPARC_CPU(cs);
  66    CPUSPARCState *env = &cpu->env;
  67    int cwp, intno = cs->exception_index;
  68
  69    /* Compute PSR before exposing state.  */
  70    if (env->cc_op != CC_OP_FLAGS) {
  71        cpu_get_psr(env);
  72    }
  73
  74#ifdef DEBUG_PCALL
  75    if (qemu_loglevel_mask(CPU_LOG_INT)) {
  76        static int count;
  77        const char *name;
  78
  79        if (intno < 0 || intno >= 0x100) {
  80            name = "Unknown";
  81        } else if (intno >= 0x80) {
  82            name = "Trap Instruction";
  83        } else {
  84            name = excp_names[intno];
  85            if (!name) {
  86                name = "Unknown";
  87            }
  88        }
  89
  90        qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
  91        log_cpu_state(cs, 0);
  92#if 0
  93        {
  94            int i;
  95            uint8_t *ptr;
  96
  97            qemu_log("       code=");
  98            ptr = (uint8_t *)env->pc;
  99            for (i = 0; i < 16; i++) {
 100                qemu_log(" %02x", ldub(ptr + i));
 101            }
 102            qemu_log("\n");
 103        }
 104#endif
 105        count++;
 106    }
 107#endif
 108#if !defined(CONFIG_USER_ONLY)
 109    if (env->psret == 0) {
 110        if (cs->exception_index == 0x80 &&
 111            env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
 112            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 113        } else {
 114            cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
 115                      cs->exception_index);
 116        }
 117        return;
 118    }
 119#endif
 120    env->psret = 0;
 121    cwp = cpu_cwp_dec(env, env->cwp - 1);
 122    cpu_set_cwp(env, cwp);
 123    env->regwptr[9] = env->pc;
 124    env->regwptr[10] = env->npc;
 125    env->psrps = env->psrs;
 126    env->psrs = 1;
 127    env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
 128    env->pc = env->tbr;
 129    env->npc = env->pc + 4;
 130    cs->exception_index = -1;
 131
 132#if !defined(CONFIG_USER_ONLY)
 133    /* IRQ acknowledgment */
 134    if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
 135        env->qemu_irq_ack(env, env->irq_manager, intno);
 136    }
 137#endif
 138}
 139
 140#if !defined(CONFIG_USER_ONLY)
 141static void leon3_cache_control_int(CPUSPARCState *env)
 142{
 143    uint32_t state = 0;
 144
 145    if (env->cache_control & CACHE_CTRL_IF) {
 146        /* Instruction cache state */
 147        state = env->cache_control & CACHE_STATE_MASK;
 148        if (state == CACHE_ENABLED) {
 149            state = CACHE_FROZEN;
 150            trace_int_helper_icache_freeze();
 151        }
 152
 153        env->cache_control &= ~CACHE_STATE_MASK;
 154        env->cache_control |= state;
 155    }
 156
 157    if (env->cache_control & CACHE_CTRL_DF) {
 158        /* Data cache state */
 159        state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 160        if (state == CACHE_ENABLED) {
 161            state = CACHE_FROZEN;
 162            trace_int_helper_dcache_freeze();
 163        }
 164
 165        env->cache_control &= ~(CACHE_STATE_MASK << 2);
 166        env->cache_control |= (state << 2);
 167    }
 168}
 169
 170void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
 171{
 172    leon3_irq_ack(irq_manager, intno);
 173    leon3_cache_control_int(env);
 174}
 175#endif
 176