LXR qemu/target/tilegx/cpu.h

   1/*
   2 *  TILE-Gx virtual CPU header
   3 *
   4 *  Copyright (c) 2015 Chen Gang
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef TILEGX_CPU_H
  21#define TILEGX_CPU_H
  22
  23#include "exec/cpu-defs.h"
  24
  25/* TILE-Gx common register alias */
  26#define TILEGX_R_RE    0   /*  0 register, for function/syscall return value */
  27#define TILEGX_R_ERR   1   /*  1 register, for syscall errno flag */
  28#define TILEGX_R_NR    10  /* 10 register, for syscall number */
  29#define TILEGX_R_BP    52  /* 52 register, optional frame pointer */
  30#define TILEGX_R_TP    53  /* TP register, thread local storage data */
  31#define TILEGX_R_SP    54  /* SP register, stack pointer */
  32#define TILEGX_R_LR    55  /* LR register, may save pc, but it is not pc */
  33#define TILEGX_R_COUNT 56  /* Only 56 registers are really useful */
  34#define TILEGX_R_SN    56  /* SN register, obsoleted, it likes zero register */
  35#define TILEGX_R_IDN0  57  /* IDN0 register, cause IDN_ACCESS exception */
  36#define TILEGX_R_IDN1  58  /* IDN1 register, cause IDN_ACCESS exception */
  37#define TILEGX_R_UDN0  59  /* UDN0 register, cause UDN_ACCESS exception */
  38#define TILEGX_R_UDN1  60  /* UDN1 register, cause UDN_ACCESS exception */
  39#define TILEGX_R_UDN2  61  /* UDN2 register, cause UDN_ACCESS exception */
  40#define TILEGX_R_UDN3  62  /* UDN3 register, cause UDN_ACCESS exception */
  41#define TILEGX_R_ZERO  63  /* Zero register, always zero */
  42#define TILEGX_R_NOREG 255 /* Invalid register value */
  43
  44/* TILE-Gx special registers used by outside */
  45enum {
  46    TILEGX_SPR_CMPEXCH = 0,
  47    TILEGX_SPR_CRITICAL_SEC = 1,
  48    TILEGX_SPR_SIM_CONTROL = 2,
  49    TILEGX_SPR_EX_CONTEXT_0_0 = 3,
  50    TILEGX_SPR_EX_CONTEXT_0_1 = 4,
  51    TILEGX_SPR_COUNT
  52};
  53
  54/* Exception numbers */
  55typedef enum {
  56    TILEGX_EXCP_NONE = 0,
  57    TILEGX_EXCP_SYSCALL = 1,
  58    TILEGX_EXCP_SIGNAL = 2,
  59    TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
  60    TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
  61    TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
  62    TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
  63    TILEGX_EXCP_OPCODE_EXCH = 0x105,
  64    TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
  65    TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
  66    TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
  67    TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
  68    TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
  69    TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
  70    TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
  71    TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
  72    TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
  73    TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
  74    TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
  75    TILEGX_EXCP_UNALIGNMENT = 0x201,
  76    TILEGX_EXCP_DBUG_BREAK = 0x301
  77} TileExcp;
  78
  79typedef struct CPUTLGState {
  80    uint64_t regs[TILEGX_R_COUNT];     /* Common used registers by outside */
  81    uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
  82    uint64_t pc;                       /* Current pc */
  83
  84#if defined(CONFIG_USER_ONLY)
  85    uint64_t excaddr;                  /* exception address */
  86    uint64_t atomic_srca;              /* Arguments to atomic "exceptions" */
  87    uint64_t atomic_srcb;
  88    uint32_t atomic_dstr;
  89    uint32_t signo;                    /* Signal number */
  90    uint32_t sigcode;                  /* Signal code */
  91#endif
  92
  93    /* Fields up to this point are cleared by a CPU reset */
  94    struct {} end_reset_fields;
  95} CPUTLGState;
  96
  97#include "qom/cpu.h"
  98
  99#define TYPE_TILEGX_CPU "tilegx-cpu"
 100
 101#define TILEGX_CPU_CLASS(klass) \
 102    OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
 103#define TILEGX_CPU(obj) \
 104    OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
 105#define TILEGX_CPU_GET_CLASS(obj) \
 106    OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
 107
 108/**
 109 * TileGXCPUClass:
 110 * @parent_realize: The parent class' realize handler.
 111 * @parent_reset: The parent class' reset handler.
 112 *
 113 * A Tile-Gx CPU model.
 114 */
 115typedef struct TileGXCPUClass {
 116    /*< private >*/
 117    CPUClass parent_class;
 118    /*< public >*/
 119
 120    DeviceRealize parent_realize;
 121    void (*parent_reset)(CPUState *cpu);
 122} TileGXCPUClass;
 123
 124/**
 125 * TileGXCPU:
 126 * @env: #CPUTLGState
 127 *
 128 * A Tile-GX CPU.
 129 */
 130typedef struct TileGXCPU {
 131    /*< private >*/
 132    CPUState parent_obj;
 133    /*< public >*/
 134
 135    CPUNegativeOffsetState neg;
 136    CPUTLGState env;
 137} TileGXCPU;
 138
 139
 140/* TILE-Gx memory attributes */
 141#define MMU_USER_IDX    0  /* Current memory operation is in user mode */
 142
 143typedef CPUTLGState CPUArchState;
 144typedef TileGXCPU ArchCPU;
 145
 146#include "exec/cpu-all.h"
 147
 148void tilegx_tcg_init(void);
 149int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
 150
 151#define CPU_RESOLVING_TYPE TYPE_TILEGX_CPU
 152
 153#define cpu_signal_handler cpu_tilegx_signal_handler
 154
 155static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
 156                                        target_ulong *cs_base, uint32_t *flags)
 157{
 158    *pc = env->pc;
 159    *cs_base = 0;
 160    *flags = 0;
 161}
 162
 163#endif
 164