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12#ifndef UNICORE32_CPU_H
13#define UNICORE32_CPU_H
14
15#include "cpu-qom.h"
16#include "exec/cpu-defs.h"
17
18typedef struct CPUUniCore32State {
19
20 uint32_t regs[32];
21
22
23
24 uint32_t uncached_asr;
25 uint32_t bsr;
26
27
28 uint32_t banked_bsr[6];
29 uint32_t banked_r29[6];
30 uint32_t banked_r30[6];
31
32
33 uint32_t CF;
34 uint32_t VF;
35 uint32_t NF;
36 uint32_t ZF;
37
38
39 struct {
40 uint32_t c0_cpuid;
41 uint32_t c0_cachetype;
42 uint32_t c1_sys;
43 uint32_t c2_base;
44 uint32_t c3_faultstatus;
45 uint32_t c4_faultaddr;
46 uint32_t c5_cacheop;
47 uint32_t c6_tlbop;
48 } cp0;
49
50
51 struct {
52 float64 regs[16];
53 uint32_t xregs[32];
54 float_status fp_status;
55 } ucf64;
56
57
58 uint32_t features;
59
60} CPUUniCore32State;
61
62
63
64
65
66
67
68struct UniCore32CPU {
69
70 CPUState parent_obj;
71
72
73 CPUNegativeOffsetState neg;
74 CPUUniCore32State env;
75};
76
77
78void uc32_cpu_do_interrupt(CPUState *cpu);
79bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
80void uc32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
81hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
82
83#define ASR_M (0x1f)
84#define ASR_MODE_USER (0x10)
85#define ASR_MODE_INTR (0x12)
86#define ASR_MODE_PRIV (0x13)
87#define ASR_MODE_TRAP (0x17)
88#define ASR_MODE_EXTN (0x1b)
89#define ASR_MODE_SUSR (0x1f)
90#define ASR_I (1 << 7)
91#define ASR_V (1 << 28)
92#define ASR_C (1 << 29)
93#define ASR_Z (1 << 30)
94#define ASR_N (1 << 31)
95#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
96#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
97
98#define UC32_EXCP_PRIV (1)
99#define UC32_EXCP_ITRAP (2)
100#define UC32_EXCP_DTRAP (3)
101#define UC32_EXCP_INTR (4)
102
103
104target_ulong cpu_asr_read(CPUUniCore32State *env1);
105
106void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
107
108
109#define UC32_UCF64_FPSCR (31)
110#define UCF64_FPSCR_MASK (0x27ffffff)
111#define UCF64_FPSCR_RND_MASK (0x7)
112#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
113#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
114#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
115#define UCF64_FPSCR_FLAG_MASK (0x3ff)
116#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
117#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
118#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
119#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
120#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
121#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
122#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
123#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
124#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
125#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
126#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
127
128#define UC32_HWCAP_CMOV 4
129#define UC32_HWCAP_UCF64 8
130
131#define cpu_signal_handler uc32_cpu_signal_handler
132
133int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
134
135
136#define MMU_MODE0_SUFFIX _kernel
137#define MMU_MODE1_SUFFIX _user
138#define MMU_USER_IDX 1
139static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
140{
141 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
142}
143
144typedef CPUUniCore32State CPUArchState;
145typedef UniCore32CPU ArchCPU;
146
147#include "exec/cpu-all.h"
148
149#define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
150#define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX
151#define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU
152
153static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
154 target_ulong *cs_base, uint32_t *flags)
155{
156 *pc = env->regs[31];
157 *cs_base = 0;
158 *flags = 0;
159 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
160 *flags |= (1 << 6);
161 }
162}
163
164bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
165 MMUAccessType access_type, int mmu_idx,
166 bool probe, uintptr_t retaddr);
167void uc32_translate_init(void);
168void switch_mode(CPUUniCore32State *, int);
169
170#endif
171