LXR qemu/target/unicore32/ucf64

   1/*
   2 * UniCore-F64 simulation helpers for QEMU.
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "qemu/osdep.h"
  12#include "cpu.h"
  13#include "exec/helper-proto.h"
  14#include "fpu/softfloat.h"
  15
  16/*
  17 * The convention used for UniCore-F64 instructions:
  18 *  Single precition routines have a "s" suffix
  19 *  Double precision routines have a "d" suffix.
  20 */
  21
  22/* Convert host exception flags to f64 form.  */
  23static inline int ucf64_exceptbits_from_host(int host_bits)
  24{
  25    int target_bits = 0;
  26
  27    if (host_bits & float_flag_invalid) {
  28        target_bits |= UCF64_FPSCR_FLAG_INVALID;
  29    }
  30    if (host_bits & float_flag_divbyzero) {
  31        target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
  32    }
  33    if (host_bits & float_flag_overflow) {
  34        target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
  35    }
  36    if (host_bits & float_flag_underflow) {
  37        target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
  38    }
  39    if (host_bits & float_flag_inexact) {
  40        target_bits |= UCF64_FPSCR_FLAG_INEXACT;
  41    }
  42    return target_bits;
  43}
  44
  45uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
  46{
  47    int i;
  48    uint32_t fpscr;
  49
  50    fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
  51    i = get_float_exception_flags(&env->ucf64.fp_status);
  52    fpscr |= ucf64_exceptbits_from_host(i);
  53    return fpscr;
  54}
  55
  56/* Convert ucf64 exception flags to target form.  */
  57static inline int ucf64_exceptbits_to_host(int target_bits)
  58{
  59    int host_bits = 0;
  60
  61    if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
  62        host_bits |= float_flag_invalid;
  63    }
  64    if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
  65        host_bits |= float_flag_divbyzero;
  66    }
  67    if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
  68        host_bits |= float_flag_overflow;
  69    }
  70    if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
  71        host_bits |= float_flag_underflow;
  72    }
  73    if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
  74        host_bits |= float_flag_inexact;
  75    }
  76    return host_bits;
  77}
  78
  79void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
  80{
  81    UniCore32CPU *cpu = env_archcpu(env);
  82    int i;
  83    uint32_t changed;
  84
  85    changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
  86    env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
  87
  88    changed ^= val;
  89    if (changed & (UCF64_FPSCR_RND_MASK)) {
  90        i = UCF64_FPSCR_RND(val);
  91        switch (i) {
  92        case 0:
  93            i = float_round_nearest_even;
  94            break;
  95        case 1:
  96            i = float_round_to_zero;
  97            break;
  98        case 2:
  99            i = float_round_up;
 100            break;
 101        case 3:
 102            i = float_round_down;
 103            break;
 104        default: /* 100 and 101 not implement */
 105            cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
 106        }
 107        set_float_rounding_mode(i, &env->ucf64.fp_status);
 108    }
 109
 110    i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
 111    set_float_exception_flags(i, &env->ucf64.fp_status);
 112}
 113
 114float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
 115{
 116    return float32_add(a, b, &env->ucf64.fp_status);
 117}
 118
 119float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
 120{
 121    return float64_add(a, b, &env->ucf64.fp_status);
 122}
 123
 124float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
 125{
 126    return float32_sub(a, b, &env->ucf64.fp_status);
 127}
 128
 129float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
 130{
 131    return float64_sub(a, b, &env->ucf64.fp_status);
 132}
 133
 134float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
 135{
 136    return float32_mul(a, b, &env->ucf64.fp_status);
 137}
 138
 139float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
 140{
 141    return float64_mul(a, b, &env->ucf64.fp_status);
 142}
 143
 144float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
 145{
 146    return float32_div(a, b, &env->ucf64.fp_status);
 147}
 148
 149float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
 150{
 151    return float64_div(a, b, &env->ucf64.fp_status);
 152}
 153
 154float32 HELPER(ucf64_negs)(float32 a)
 155{
 156    return float32_chs(a);
 157}
 158
 159float64 HELPER(ucf64_negd)(float64 a)
 160{
 161    return float64_chs(a);
 162}
 163
 164float32 HELPER(ucf64_abss)(float32 a)
 165{
 166    return float32_abs(a);
 167}
 168
 169float64 HELPER(ucf64_absd)(float64 a)
 170{
 171    return float64_abs(a);
 172}
 173
 174void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c,
 175        CPUUniCore32State *env)
 176{
 177    int flag;
 178    flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
 179    env->CF = 0;
 180    switch (c & 0x7) {
 181    case 0: /* F */
 182        break;
 183    case 1: /* UN */
 184        if (flag == 2) {
 185            env->CF = 1;
 186        }
 187        break;
 188    case 2: /* EQ */
 189        if (flag == 0) {
 190            env->CF = 1;
 191        }
 192        break;
 193    case 3: /* UEQ */
 194        if ((flag == 0) || (flag == 2)) {
 195            env->CF = 1;
 196        }
 197        break;
 198    case 4: /* OLT */
 199        if (flag == -1) {
 200            env->CF = 1;
 201        }
 202        break;
 203    case 5: /* ULT */
 204        if ((flag == -1) || (flag == 2)) {
 205            env->CF = 1;
 206        }
 207        break;
 208    case 6: /* OLE */
 209        if ((flag == -1) || (flag == 0)) {
 210            env->CF = 1;
 211        }
 212        break;
 213    case 7: /* ULE */
 214        if (flag != 1) {
 215            env->CF = 1;
 216        }
 217        break;
 218    }
 219    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 220                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 221}
 222
 223void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c,
 224        CPUUniCore32State *env)
 225{
 226    int flag;
 227    flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
 228    env->CF = 0;
 229    switch (c & 0x7) {
 230    case 0: /* F */
 231        break;
 232    case 1: /* UN */
 233        if (flag == 2) {
 234            env->CF = 1;
 235        }
 236        break;
 237    case 2: /* EQ */
 238        if (flag == 0) {
 239            env->CF = 1;
 240        }
 241        break;
 242    case 3: /* UEQ */
 243        if ((flag == 0) || (flag == 2)) {
 244            env->CF = 1;
 245        }
 246        break;
 247    case 4: /* OLT */
 248        if (flag == -1) {
 249            env->CF = 1;
 250        }
 251        break;
 252    case 5: /* ULT */
 253        if ((flag == -1) || (flag == 2)) {
 254            env->CF = 1;
 255        }
 256        break;
 257    case 6: /* OLE */
 258        if ((flag == -1) || (flag == 0)) {
 259            env->CF = 1;
 260        }
 261        break;
 262    case 7: /* ULE */
 263        if (flag != 1) {
 264            env->CF = 1;
 265        }
 266        break;
 267    }
 268    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 269                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 270}
 271
 272/* Helper routines to perform bitwise copies between float and int.  */
 273static inline float32 ucf64_itos(uint32_t i)
 274{
 275    union {
 276        uint32_t i;
 277        float32 s;
 278    } v;
 279
 280    v.i = i;
 281    return v.s;
 282}
 283
 284static inline uint32_t ucf64_stoi(float32 s)
 285{
 286    union {
 287        uint32_t i;
 288        float32 s;
 289    } v;
 290
 291    v.s = s;
 292    return v.i;
 293}
 294
 295/* Integer to float conversion.  */
 296float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
 297{
 298    return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
 299}
 300
 301float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
 302{
 303    return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
 304}
 305
 306/* Float to integer conversion.  */
 307float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
 308{
 309    return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
 310}
 311
 312float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
 313{
 314    return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
 315}
 316
 317/* floating point conversion */
 318float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
 319{
 320    return float32_to_float64(x, &env->ucf64.fp_status);
 321}
 322
 323float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
 324{
 325    return float64_to_float32(x, &env->ucf64.fp_status);
 326}
 327