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28#include "qemu/osdep.h"
29#include "cpu.h"
30#include "chardev/char-fe.h"
31#include "exec/helper-proto.h"
32#include "hw/semihosting/semihost.h"
33#include "qapi/error.h"
34#include "qemu/log.h"
35#include "sysemu/sysemu.h"
36
37enum {
38 TARGET_SYS_exit = 1,
39 TARGET_SYS_read = 3,
40 TARGET_SYS_write = 4,
41 TARGET_SYS_open = 5,
42 TARGET_SYS_close = 6,
43 TARGET_SYS_lseek = 19,
44 TARGET_SYS_select_one = 29,
45
46 TARGET_SYS_argc = 1000,
47 TARGET_SYS_argv_sz = 1001,
48 TARGET_SYS_argv = 1002,
49 TARGET_SYS_memset = 1004,
50};
51
52enum {
53 SELECT_ONE_READ = 1,
54 SELECT_ONE_WRITE = 2,
55 SELECT_ONE_EXCEPT = 3,
56};
57
58enum {
59 TARGET_EPERM = 1,
60 TARGET_ENOENT = 2,
61 TARGET_ESRCH = 3,
62 TARGET_EINTR = 4,
63 TARGET_EIO = 5,
64 TARGET_ENXIO = 6,
65 TARGET_E2BIG = 7,
66 TARGET_ENOEXEC = 8,
67 TARGET_EBADF = 9,
68 TARGET_ECHILD = 10,
69 TARGET_EAGAIN = 11,
70 TARGET_ENOMEM = 12,
71 TARGET_EACCES = 13,
72 TARGET_EFAULT = 14,
73 TARGET_ENOTBLK = 15,
74 TARGET_EBUSY = 16,
75 TARGET_EEXIST = 17,
76 TARGET_EXDEV = 18,
77 TARGET_ENODEV = 19,
78 TARGET_ENOTDIR = 20,
79 TARGET_EISDIR = 21,
80 TARGET_EINVAL = 22,
81 TARGET_ENFILE = 23,
82 TARGET_EMFILE = 24,
83 TARGET_ENOTTY = 25,
84 TARGET_ETXTBSY = 26,
85 TARGET_EFBIG = 27,
86 TARGET_ENOSPC = 28,
87 TARGET_ESPIPE = 29,
88 TARGET_EROFS = 30,
89 TARGET_EMLINK = 31,
90 TARGET_EPIPE = 32,
91 TARGET_EDOM = 33,
92 TARGET_ERANGE = 34,
93 TARGET_ENOSYS = 88,
94 TARGET_ELOOP = 92,
95};
96
97static uint32_t errno_h2g(int host_errno)
98{
99 static const uint32_t guest_errno[] = {
100 [EPERM] = TARGET_EPERM,
101 [ENOENT] = TARGET_ENOENT,
102 [ESRCH] = TARGET_ESRCH,
103 [EINTR] = TARGET_EINTR,
104 [EIO] = TARGET_EIO,
105 [ENXIO] = TARGET_ENXIO,
106 [E2BIG] = TARGET_E2BIG,
107 [ENOEXEC] = TARGET_ENOEXEC,
108 [EBADF] = TARGET_EBADF,
109 [ECHILD] = TARGET_ECHILD,
110 [EAGAIN] = TARGET_EAGAIN,
111 [ENOMEM] = TARGET_ENOMEM,
112 [EACCES] = TARGET_EACCES,
113 [EFAULT] = TARGET_EFAULT,
114#ifdef ENOTBLK
115 [ENOTBLK] = TARGET_ENOTBLK,
116#endif
117 [EBUSY] = TARGET_EBUSY,
118 [EEXIST] = TARGET_EEXIST,
119 [EXDEV] = TARGET_EXDEV,
120 [ENODEV] = TARGET_ENODEV,
121 [ENOTDIR] = TARGET_ENOTDIR,
122 [EISDIR] = TARGET_EISDIR,
123 [EINVAL] = TARGET_EINVAL,
124 [ENFILE] = TARGET_ENFILE,
125 [EMFILE] = TARGET_EMFILE,
126 [ENOTTY] = TARGET_ENOTTY,
127#ifdef ETXTBSY
128 [ETXTBSY] = TARGET_ETXTBSY,
129#endif
130 [EFBIG] = TARGET_EFBIG,
131 [ENOSPC] = TARGET_ENOSPC,
132 [ESPIPE] = TARGET_ESPIPE,
133 [EROFS] = TARGET_EROFS,
134 [EMLINK] = TARGET_EMLINK,
135 [EPIPE] = TARGET_EPIPE,
136 [EDOM] = TARGET_EDOM,
137 [ERANGE] = TARGET_ERANGE,
138 [ENOSYS] = TARGET_ENOSYS,
139#ifdef ELOOP
140 [ELOOP] = TARGET_ELOOP,
141#endif
142 };
143
144 if (host_errno == 0) {
145 return 0;
146 } else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
147 guest_errno[host_errno]) {
148 return guest_errno[host_errno];
149 } else {
150 return TARGET_EINVAL;
151 }
152}
153
154typedef struct XtensaSimConsole {
155 CharBackend be;
156 struct {
157 char buffer[16];
158 size_t offset;
159 } input;
160} XtensaSimConsole;
161
162static XtensaSimConsole *sim_console;
163
164static IOCanReadHandler sim_console_can_read;
165static int sim_console_can_read(void *opaque)
166{
167 XtensaSimConsole *p = opaque;
168
169 return sizeof(p->input.buffer) - p->input.offset;
170}
171
172static IOReadHandler sim_console_read;
173static void sim_console_read(void *opaque, const uint8_t *buf, int size)
174{
175 XtensaSimConsole *p = opaque;
176 size_t copy = sizeof(p->input.buffer) - p->input.offset;
177
178 if (size < copy) {
179 copy = size;
180 }
181 memcpy(p->input.buffer + p->input.offset, buf, copy);
182 p->input.offset += copy;
183}
184
185void xtensa_sim_open_console(Chardev *chr)
186{
187 static XtensaSimConsole console;
188
189 qemu_chr_fe_init(&console.be, chr, &error_abort);
190 qemu_chr_fe_set_handlers(&console.be,
191 sim_console_can_read,
192 sim_console_read,
193 NULL, NULL, &console,
194 NULL, true);
195 sim_console = &console;
196}
197
198void HELPER(simcall)(CPUXtensaState *env)
199{
200 CPUState *cs = env_cpu(env);
201 uint32_t *regs = env->regs;
202
203 switch (regs[2]) {
204 case TARGET_SYS_exit:
205 exit(regs[3]);
206 break;
207
208 case TARGET_SYS_read:
209 case TARGET_SYS_write:
210 {
211 bool is_write = regs[2] == TARGET_SYS_write;
212 uint32_t fd = regs[3];
213 uint32_t vaddr = regs[4];
214 uint32_t len = regs[5];
215 uint32_t len_done = 0;
216
217 while (len > 0) {
218 hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
219 uint32_t page_left =
220 TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
221 uint32_t io_sz = page_left < len ? page_left : len;
222 hwaddr sz = io_sz;
223 void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
224 uint32_t io_done;
225 bool error = false;
226
227 if (buf) {
228 vaddr += io_sz;
229 len -= io_sz;
230 if (fd < 3 && sim_console) {
231 if (is_write && (fd == 1 || fd == 2)) {
232 io_done = qemu_chr_fe_write_all(&sim_console->be,
233 buf, io_sz);
234 regs[3] = errno_h2g(errno);
235 } else if (!is_write && fd == 0) {
236 if (sim_console->input.offset) {
237 io_done = sim_console->input.offset;
238 if (io_sz < io_done) {
239 io_done = io_sz;
240 }
241 memcpy(buf, sim_console->input.buffer, io_done);
242 memmove(sim_console->input.buffer,
243 sim_console->input.buffer + io_done,
244 sim_console->input.offset - io_done);
245 sim_console->input.offset -= io_done;
246 qemu_chr_fe_accept_input(&sim_console->be);
247 } else {
248 io_done = -1;
249 regs[3] = TARGET_EAGAIN;
250 }
251 } else {
252 qemu_log_mask(LOG_GUEST_ERROR,
253 "%s fd %d is not supported with chardev console\n",
254 is_write ?
255 "writing to" : "reading from", fd);
256 io_done = -1;
257 regs[3] = TARGET_EBADF;
258 }
259 } else {
260 io_done = is_write ?
261 write(fd, buf, io_sz) :
262 read(fd, buf, io_sz);
263 regs[3] = errno_h2g(errno);
264 }
265 if (io_done == -1) {
266 error = true;
267 io_done = 0;
268 }
269 cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
270 } else {
271 error = true;
272 regs[3] = TARGET_EINVAL;
273 break;
274 }
275 if (error) {
276 if (!len_done) {
277 len_done = -1;
278 }
279 break;
280 }
281 len_done += io_done;
282 if (io_done < io_sz) {
283 break;
284 }
285 }
286 regs[2] = len_done;
287 }
288 break;
289
290 case TARGET_SYS_open:
291 {
292 char name[1024];
293 int rc;
294 int i;
295
296 for (i = 0; i < ARRAY_SIZE(name); ++i) {
297 rc = cpu_memory_rw_debug(cs, regs[3] + i,
298 (uint8_t *)name + i, 1, 0);
299 if (rc != 0 || name[i] == 0) {
300 break;
301 }
302 }
303
304 if (rc == 0 && i < ARRAY_SIZE(name)) {
305 regs[2] = open(name, regs[4], regs[5]);
306 regs[3] = errno_h2g(errno);
307 } else {
308 regs[2] = -1;
309 regs[3] = TARGET_EINVAL;
310 }
311 }
312 break;
313
314 case TARGET_SYS_close:
315 if (regs[3] < 3) {
316 regs[2] = regs[3] = 0;
317 } else {
318 regs[2] = close(regs[3]);
319 regs[3] = errno_h2g(errno);
320 }
321 break;
322
323 case TARGET_SYS_lseek:
324 regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
325 regs[3] = errno_h2g(errno);
326 break;
327
328 case TARGET_SYS_select_one:
329 {
330 uint32_t fd = regs[3];
331 uint32_t rq = regs[4];
332 uint32_t target_tv = regs[5];
333 uint32_t target_tvv[2];
334
335 struct timeval tv = {0};
336
337 if (target_tv) {
338 cpu_memory_rw_debug(cs, target_tv,
339 (uint8_t *)target_tvv, sizeof(target_tvv), 0);
340 tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
341 tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
342 }
343 if (fd < 3 && sim_console) {
344 if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
345 regs[2] = 1;
346 } else if (fd == 0 && rq == SELECT_ONE_READ) {
347 regs[2] = sim_console->input.offset > 0;
348 } else {
349 regs[2] = 0;
350 }
351 regs[3] = 0;
352 } else {
353 fd_set fdset;
354
355 FD_ZERO(&fdset);
356 FD_SET(fd, &fdset);
357 regs[2] = select(fd + 1,
358 rq == SELECT_ONE_READ ? &fdset : NULL,
359 rq == SELECT_ONE_WRITE ? &fdset : NULL,
360 rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
361 target_tv ? &tv : NULL);
362 regs[3] = errno_h2g(errno);
363 }
364 }
365 break;
366
367 case TARGET_SYS_argc:
368 regs[2] = semihosting_get_argc();
369 regs[3] = 0;
370 break;
371
372 case TARGET_SYS_argv_sz:
373 {
374 int argc = semihosting_get_argc();
375 int sz = (argc + 1) * sizeof(uint32_t);
376 int i;
377
378 for (i = 0; i < argc; ++i) {
379 sz += 1 + strlen(semihosting_get_arg(i));
380 }
381 regs[2] = sz;
382 regs[3] = 0;
383 }
384 break;
385
386 case TARGET_SYS_argv:
387 {
388 int argc = semihosting_get_argc();
389 int str_offset = (argc + 1) * sizeof(uint32_t);
390 int i;
391 uint32_t argptr;
392
393 for (i = 0; i < argc; ++i) {
394 const char *str = semihosting_get_arg(i);
395 int str_size = strlen(str) + 1;
396
397 argptr = tswap32(regs[3] + str_offset);
398
399 cpu_memory_rw_debug(cs,
400 regs[3] + i * sizeof(uint32_t),
401 (uint8_t *)&argptr, sizeof(argptr), 1);
402 cpu_memory_rw_debug(cs,
403 regs[3] + str_offset,
404 (uint8_t *)str, str_size, 1);
405 str_offset += str_size;
406 }
407 argptr = 0;
408 cpu_memory_rw_debug(cs,
409 regs[3] + i * sizeof(uint32_t),
410 (uint8_t *)&argptr, sizeof(argptr), 1);
411 regs[3] = 0;
412 }
413 break;
414
415 case TARGET_SYS_memset:
416 {
417 uint32_t base = regs[3];
418 uint32_t sz = regs[5];
419
420 while (sz) {
421 hwaddr len = sz;
422 void *buf = cpu_physical_memory_map(base, &len, 1);
423
424 if (buf && len) {
425 memset(buf, regs[4], len);
426 cpu_physical_memory_unmap(buf, len, 1, len);
427 } else {
428 len = 1;
429 }
430 base += len;
431 sz -= len;
432 }
433 regs[2] = regs[3];
434 regs[3] = 0;
435 }
436 break;
437
438 default:
439 qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
440 regs[2] = -1;
441 regs[3] = TARGET_ENOSYS;
442 break;
443 }
444}
445
