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25#include "qemu/osdep.h"
26#include <getopt.h>
27
28#include "libqtest.h"
29#include "libqos/libqos-pc.h"
30#include "libqos/ahci.h"
31#include "libqos/pci-pc.h"
32
33#include "qemu-common.h"
34#include "qapi/qmp/qdict.h"
35#include "qemu/host-utils.h"
36
37#include "hw/pci/pci_ids.h"
38#include "hw/pci/pci_regs.h"
39
40
41#define qmp_discard_response(s, ...) qobject_unref(qtest_qmp(s, __VA_ARGS__))
42
43
44#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
45#define TEST_IMAGE_SIZE_MB_SMALL 64
46
47
48static char tmp_path[] = "/tmp/qtest.XXXXXX";
49static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
50static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
51static bool ahci_pedantic;
52static const char *imgfmt;
53static unsigned test_image_size_mb;
54
55
56static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
57static void ahci_test_pci_spec(AHCIQState *ahci);
58static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
59 uint8_t offset);
60static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
61static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
62static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
63
64
65
66static uint64_t mb_to_sectors(uint64_t image_size_mb)
67{
68 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
69}
70
71static void string_bswap16(uint16_t *s, size_t bytes)
72{
73 g_assert_cmphex((bytes & 1), ==, 0);
74 bytes /= 2;
75
76 while (bytes--) {
77 *s = bswap16(*s);
78 s++;
79 }
80}
81
82
83
84
85static void verify_state(AHCIQState *ahci, uint64_t hba_old)
86{
87 int i, j;
88 uint32_t ahci_fingerprint;
89 uint64_t hba_base;
90 AHCICommandHeader cmd;
91
92 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
93 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
94
95
96 if (!ahci->enabled) {
97 return;
98 }
99
100 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
101 g_assert_cmphex(hba_base, ==, hba_old);
102
103 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
104 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
105
106 for (i = 0; i < 32; i++) {
107 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
108 ahci->port[i].fb);
109 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
110 ahci->port[i].clb);
111 for (j = 0; j < 32; j++) {
112 ahci_get_command_header(ahci, i, j, &cmd);
113 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
114 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
115 }
116 }
117}
118
119static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
120{
121 QOSState *tmp = to->parent;
122 QPCIDevice *dev = to->dev;
123 char *uri_local = NULL;
124 uint64_t hba_old;
125
126 if (uri == NULL) {
127 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
128 uri = uri_local;
129 }
130
131 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
132
133
134 migrate(from->parent, to->parent, uri);
135
136
137
138
139 memcpy(to, from, sizeof(AHCIQState));
140 to->parent = tmp;
141 to->dev = dev;
142
143 tmp = from->parent;
144 dev = from->dev;
145 memset(from, 0x00, sizeof(AHCIQState));
146 from->parent = tmp;
147 from->dev = dev;
148
149 verify_state(to, hba_old);
150 g_free(uri_local);
151}
152
153
154
155
156
157
158static AHCIQState *ahci_vboot(const char *cli, va_list ap)
159{
160 AHCIQState *s;
161
162 s = g_new0(AHCIQState, 1);
163 s->parent = qtest_pc_vboot(cli, ap);
164 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT);
165
166
167 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
168
169 return s;
170}
171
172
173
174
175static AHCIQState *ahci_boot(const char *cli, ...)
176{
177 AHCIQState *s;
178 va_list ap;
179
180 if (cli) {
181 va_start(ap, cli);
182 s = ahci_vboot(cli, ap);
183 va_end(ap);
184 } else {
185 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
186 " -M q35 "
187 "-device ide-hd,drive=drive0 "
188 "-global ide-hd.serial=%s "
189 "-global ide-hd.ver=%s";
190 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version");
191 }
192
193 return s;
194}
195
196
197
198
199static void ahci_shutdown(AHCIQState *ahci)
200{
201 QOSState *qs = ahci->parent;
202
203 assert(!global_qtest);
204 ahci_clean_mem(ahci);
205 free_ahci_device(ahci->dev);
206 g_free(ahci);
207 qtest_shutdown(qs);
208}
209
210
211
212
213
214static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
215{
216 AHCIQState *ahci;
217 va_list ap;
218 uint16_t buff[256];
219 uint8_t port;
220 uint8_t hello;
221
222 if (cli) {
223 va_start(ap, cli);
224 ahci = ahci_vboot(cli, ap);
225 va_end(ap);
226 } else {
227 ahci = ahci_boot(NULL);
228 }
229
230 ahci_pci_enable(ahci);
231 ahci_hba_enable(ahci);
232
233 port = ahci_port_select(ahci);
234 ahci_port_clear(ahci, port);
235 if (is_atapi(ahci, port)) {
236 hello = CMD_PACKET_ID;
237 } else {
238 hello = CMD_IDENTIFY;
239 }
240 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
241
242 return ahci;
243}
244
245
246
247
248
249
250static void ahci_test_pci_spec(AHCIQState *ahci)
251{
252 uint8_t datab;
253 uint16_t data;
254 uint32_t datal;
255
256
257 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE);
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
265 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
266 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
267 ASSERT_BIT_CLEAR(data, 0xF800);
268
269 data = qpci_config_readw(ahci->dev, PCI_STATUS);
270 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
272 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
278 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
279 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
280
281
282 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
283 if (ahci_pedantic) {
284
285
286 ASSERT_BIT_CLEAR(datal, 0xFF);
287 }
288
289
290 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
291 if (PCI_SCC(datal) == 0x01) {
292
293 ASSERT_BIT_SET(0x80000000, datal);
294 ASSERT_BIT_CLEAR(0x60000000, datal);
295 } else if (PCI_SCC(datal) == 0x04) {
296
297 g_assert_cmphex(PCI_PI(datal), ==, 0);
298 } else if (PCI_SCC(datal) == 0x06) {
299
300 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
301 } else {
302 g_assert_not_reached();
303 }
304
305 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
306 g_assert_cmphex(datab, ==, 0);
307
308 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
309 g_assert_cmphex(datab, ==, 0);
310
311
312 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
313 ASSERT_BIT_CLEAR(datab, 0x7F);
314
315
316 datab = qpci_config_readb(ahci->dev, PCI_BIST);
317 ASSERT_BIT_CLEAR(datab, 0x7F);
318
319
320 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
321 g_assert_cmphex(datal, ==, 0);
322
323 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
324 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
325
326
327 ASSERT_BIT_CLEAR(datal, 0xFF);
328
329
330 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
331
332 ASSERT_BIT_CLEAR(datal, ~0xFF);
333 g_assert_cmphex(datal, !=, 0);
334
335
336 data = qpci_config_readw(ahci->dev, datal);
337
338 switch (ahci->fingerprint) {
339 case AHCI_INTEL_ICH9:
340
341 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
342 break;
343 default:
344
345 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
346 }
347
348 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
349
350
351 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
352 g_assert_cmphex(datal, ==, 0);
353
354
355 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
356 g_assert_cmphex(datab, ==, 0);
357}
358
359
360
361
362static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
363 uint8_t offset)
364{
365 uint8_t cid = header & 0xFF;
366 uint8_t next = header >> 8;
367
368 g_test_message("CID: %02x; next: %02x", cid, next);
369
370 switch (cid) {
371 case PCI_CAP_ID_PM:
372 ahci_test_pmcap(ahci, offset);
373 break;
374 case PCI_CAP_ID_MSI:
375 ahci_test_msicap(ahci, offset);
376 break;
377 case PCI_CAP_ID_SATA:
378 ahci_test_satacap(ahci, offset);
379 break;
380
381 default:
382 g_test_message("Unknown CAP 0x%02x", cid);
383 }
384
385 if (next) {
386 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
387 }
388}
389
390
391
392
393static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
394{
395 uint16_t dataw;
396 uint32_t datal;
397
398 g_test_message("Verifying SATACAP");
399
400
401 dataw = qpci_config_readw(ahci->dev, offset + 2);
402 g_assert_cmphex(dataw, ==, 0x10);
403
404
405 datal = qpci_config_readw(ahci->dev, offset + 4);
406
407 switch (datal & 0x0F) {
408 case 0x04:
409 case 0x05:
410 case 0x06:
411 case 0x07:
412 case 0x08:
413 case 0x09:
414 case 0x0F:
415 break;
416 default:
417
418 g_assert_not_reached();
419 }
420
421
422 g_assert_cmphex((datal >> 24), ==, 0x00);
423}
424
425
426
427
428static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
429{
430 uint16_t dataw;
431 uint32_t datal;
432
433 g_test_message("Verifying MSICAP");
434
435 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
437 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
438 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
439
440 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
441 g_assert_cmphex(datal, ==, 0);
442
443 if (dataw & PCI_MSI_FLAGS_64BIT) {
444 g_test_message("MSICAP is 64bit");
445 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
446 g_assert_cmphex(datal, ==, 0);
447 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
448 g_assert_cmphex(dataw, ==, 0);
449 } else {
450 g_test_message("MSICAP is 32bit");
451 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
452 g_assert_cmphex(dataw, ==, 0);
453 }
454}
455
456
457
458
459static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
460{
461 uint16_t dataw;
462
463 g_test_message("Verifying PMCAP");
464
465 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
468 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
469 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
470
471 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
474 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
475 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
476}
477
478static void ahci_test_hba_spec(AHCIQState *ahci)
479{
480 unsigned i;
481 uint32_t reg;
482 uint32_t ports;
483 uint8_t nports_impl;
484 uint8_t maxports;
485
486 g_assert(ahci != NULL);
487
488
489
490
491
492
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494
495
496
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498
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505
506
507
508
509 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
510 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
511
512
513 reg = ahci_rreg(ahci, AHCI_GHC);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
515 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
516 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
517 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
518 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
519 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
520 } else {
521 g_test_message("Supports AHCI/Legacy mix.");
522 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
523 }
524
525
526 reg = ahci_rreg(ahci, AHCI_IS);
527 g_assert_cmphex(reg, ==, 0);
528
529
530 ports = ahci_rreg(ahci, AHCI_PI);
531
532 g_assert_cmphex(ports, !=, 0);
533
534 nports_impl = ctpopl(ports);
535 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
536
537
538
539
540 g_assert_cmphex(ahci->barsize, >, 0);
541 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
542
543 g_assert_cmphex((reg >> maxports), ==, 0);
544
545
546 reg = ahci_rreg(ahci, AHCI_VS);
547 switch (reg) {
548 case AHCI_VERSION_0_95:
549 case AHCI_VERSION_1_0:
550 case AHCI_VERSION_1_1:
551 case AHCI_VERSION_1_2:
552 case AHCI_VERSION_1_3:
553 break;
554 default:
555 g_assert_not_reached();
556 }
557
558
559 reg = ahci_rreg(ahci, AHCI_CCCCTL);
560 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
561 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
562 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
563 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
564 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
565 } else {
566 g_assert_cmphex(reg, ==, 0);
567 }
568
569
570 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
571
572 g_assert_cmphex(reg, ==, 0);
573
574
575 reg = ahci_rreg(ahci, AHCI_EMLOC);
576 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
577 g_assert_cmphex(reg, ==, 0);
578 }
579
580
581 reg = ahci_rreg(ahci, AHCI_EMCTL);
582 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
585 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
586 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
587 } else {
588 g_assert_cmphex(reg, ==, 0);
589 }
590
591
592 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
593 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
594
595
596 reg = ahci_rreg(ahci, AHCI_BOHC);
597 g_assert_cmphex(reg, ==, 0);
598
599
600 g_test_message("Verifying HBA reserved area is empty.");
601 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
602 reg = ahci_rreg(ahci, i);
603 g_assert_cmphex(reg, ==, 0);
604 }
605
606
607 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
608 g_test_message("Verifying HBA/NVMHCI area is empty.");
609 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
610 reg = ahci_rreg(ahci, i);
611 g_assert_cmphex(reg, ==, 0);
612 }
613 }
614
615
616 g_test_message("Verifying HBA/Vendor area is empty.");
617 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
618 reg = ahci_rreg(ahci, i);
619 g_assert_cmphex(reg, ==, 0);
620 }
621
622
623 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
624 if (BITSET(ports, 0x1)) {
625 g_test_message("Testing port %u for spec", i);
626 ahci_test_port_spec(ahci, i);
627 } else {
628 uint16_t j;
629 uint16_t low = AHCI_PORTS + (32 * i);
630 uint16_t high = AHCI_PORTS + (32 * (i + 1));
631 g_test_message("Asserting unimplemented port %u "
632 "(reg [%u-%u]) is empty.",
633 i, low, high - 1);
634 for (j = low; j < high; ++j) {
635 reg = ahci_rreg(ahci, j);
636 g_assert_cmphex(reg, ==, 0);
637 }
638 }
639 }
640}
641
642
643
644
645static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
646{
647 uint32_t reg;
648 unsigned i;
649
650
651 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
652 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
653
654
655 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
656 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
657 g_assert_cmphex(reg, ==, 0);
658 }
659
660
661 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
662 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
663
664
665 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
666 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
667 g_assert_cmphex(reg, ==, 0);
668 }
669
670
671 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
672 g_assert_cmphex(reg, ==, 0);
673
674
675 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
676 g_assert_cmphex(reg, ==, 0);
677
678
679 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);
690 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);
691 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
692
693 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
694 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
695 }
696
697 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
698 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
699 }
700
701 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
702 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
703 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
704 }
705
706 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
707 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
708 }
709
710 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
711
712 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
713 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
714 }
715
716
717 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
718 g_assert_cmphex(reg, ==, 0);
719
720
721 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
722
723
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
726 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
727 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
729 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
730 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
731
732
733
734
735
736
737
738
739 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
740 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
741
742
743
744
745 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
746 g_assert_cmphex(reg, ==, 0);
747
748
749 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
750 g_assert_cmphex(reg, ==, 0);
751
752
753 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
754 g_assert_cmphex(reg, ==, 0);
755
756
757 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
758 g_assert_cmphex(reg, ==, 0);
759
760
761 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
762 g_assert_cmphex(reg, ==, 0);
763
764
765 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
770 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
771 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
772 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
773
774 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
775 }
776
777
778 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
779 reg = ahci_px_rreg(ahci, port, i);
780 g_assert_cmphex(reg, ==, 0);
781 }
782
783
784 for (i = AHCI_PX_VS; i < 32; ++i) {
785 reg = ahci_px_rreg(ahci, port, i);
786 if (reg) {
787 g_test_message("INFO: Vendor register %u non-empty", i);
788 }
789 }
790}
791
792
793
794
795
796static void ahci_test_identify(AHCIQState *ahci)
797{
798 uint16_t buff[256];
799 unsigned px;
800 int rc;
801 uint16_t sect_size;
802 const size_t buffsize = 512;
803
804 g_assert(ahci != NULL);
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828 px = ahci_port_select(ahci);
829 g_test_message("Selected port %u for test", px);
830
831
832 ahci_port_clear(ahci, px);
833
834
835 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
836
837
838
839
840
841
842 string_bswap16(&buff[10], 20);
843 rc = memcmp(&buff[10], "testdisk ", 20);
844 g_assert_cmphex(rc, ==, 0);
845
846 string_bswap16(&buff[23], 8);
847 rc = memcmp(&buff[23], "version ", 8);
848 g_assert_cmphex(rc, ==, 0);
849
850 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
851 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
852}
853
854static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
855 uint64_t sector, uint8_t read_cmd,
856 uint8_t write_cmd)
857{
858 uint64_t ptr;
859 uint8_t port;
860 unsigned char *tx = g_malloc(bufsize);
861 unsigned char *rx = g_malloc0(bufsize);
862
863 g_assert(ahci != NULL);
864
865
866 port = ahci_port_select(ahci);
867 ahci_port_clear(ahci, port);
868
869
870
871 ptr = ahci_alloc(ahci, bufsize);
872 g_assert(ptr);
873
874
875 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
876 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
877
878
879 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
880 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
881 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
882
883
884 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
885 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
886
887 ahci_free(ahci, ptr);
888 g_free(tx);
889 g_free(rx);
890}
891
892static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
893{
894 uint8_t port;
895
896
897 port = ahci_port_select(ahci);
898 ahci_port_clear(ahci, port);
899
900 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
901
902 return port;
903}
904
905static void ahci_test_flush(AHCIQState *ahci)
906{
907 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
908}
909
910static void ahci_test_max(AHCIQState *ahci)
911{
912 RegD2HFIS *d2h = g_malloc0(0x20);
913 uint64_t nsect;
914 uint8_t port;
915 uint8_t cmd;
916 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
917
918 if (config_sect > 0xFFFFFF) {
919 cmd = CMD_READ_MAX_EXT;
920 } else {
921 cmd = CMD_READ_MAX;
922 }
923
924 port = ahci_test_nondata(ahci, cmd);
925 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
926 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
927 (uint64_t)d2h->lba_hi[1] << 32 |
928 (uint64_t)d2h->lba_hi[0] << 24 |
929 (uint64_t)d2h->lba_lo[2] << 16 |
930 (uint64_t)d2h->lba_lo[1] << 8 |
931 (uint64_t)d2h->lba_lo[0];
932
933 g_assert_cmphex(nsect, ==, config_sect);
934 g_free(d2h);
935}
936
937
938
939
940
941
942
943
944
945static void test_sanity(void)
946{
947 AHCIQState *ahci;
948 ahci = ahci_boot(NULL);
949 ahci_shutdown(ahci);
950}
951
952
953
954
955
956static void test_pci_spec(void)
957{
958 AHCIQState *ahci;
959 ahci = ahci_boot(NULL);
960 ahci_test_pci_spec(ahci);
961 ahci_shutdown(ahci);
962}
963
964
965
966
967
968static void test_pci_enable(void)
969{
970 AHCIQState *ahci;
971 ahci = ahci_boot(NULL);
972 ahci_pci_enable(ahci);
973 ahci_shutdown(ahci);
974}
975
976
977
978
979
980static void test_hba_spec(void)
981{
982 AHCIQState *ahci;
983
984 ahci = ahci_boot(NULL);
985 ahci_pci_enable(ahci);
986 ahci_test_hba_spec(ahci);
987 ahci_shutdown(ahci);
988}
989
990
991
992
993
994static void test_hba_enable(void)
995{
996 AHCIQState *ahci;
997
998 ahci = ahci_boot(NULL);
999 ahci_pci_enable(ahci);
1000 ahci_hba_enable(ahci);
1001 ahci_shutdown(ahci);
1002}
1003
1004
1005
1006
1007
1008static void test_identify(void)
1009{
1010 AHCIQState *ahci;
1011
1012 ahci = ahci_boot_and_enable(NULL);
1013 ahci_test_identify(ahci);
1014 ahci_shutdown(ahci);
1015}
1016
1017
1018
1019
1020
1021
1022
1023static void test_dma_fragmented(void)
1024{
1025 AHCIQState *ahci;
1026 AHCICommand *cmd;
1027 uint8_t px;
1028 size_t bufsize = 4096;
1029 unsigned char *tx = g_malloc(bufsize);
1030 unsigned char *rx = g_malloc0(bufsize);
1031 uint64_t ptr;
1032
1033 ahci = ahci_boot_and_enable(NULL);
1034 px = ahci_port_select(ahci);
1035 ahci_port_clear(ahci, px);
1036
1037
1038 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1039
1040
1041 ptr = guest_alloc(&ahci->parent->alloc, bufsize);
1042 g_assert(ptr);
1043 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
1044
1045 cmd = ahci_command_create(CMD_WRITE_DMA);
1046 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1047 ahci_command_commit(ahci, cmd, px);
1048 ahci_command_issue(ahci, cmd);
1049 ahci_command_verify(ahci, cmd);
1050 ahci_command_free(cmd);
1051
1052 cmd = ahci_command_create(CMD_READ_DMA);
1053 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1054 ahci_command_commit(ahci, cmd, px);
1055 ahci_command_issue(ahci, cmd);
1056 ahci_command_verify(ahci, cmd);
1057 ahci_command_free(cmd);
1058
1059
1060 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
1061 guest_free(&ahci->parent->alloc, ptr);
1062
1063 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1064
1065 ahci_shutdown(ahci);
1066
1067 g_free(rx);
1068 g_free(tx);
1069}
1070
1071
1072
1073
1074
1075static void make_dirty(AHCIQState* ahci, uint8_t port)
1076{
1077 uint64_t ptr;
1078 unsigned bufsize = 512;
1079
1080 ptr = ahci_alloc(ahci, bufsize);
1081 g_assert(ptr);
1082
1083 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1084 ahci_free(ahci, ptr);
1085}
1086
1087static void test_flush(void)
1088{
1089 AHCIQState *ahci;
1090 uint8_t port;
1091
1092 ahci = ahci_boot_and_enable(NULL);
1093
1094 port = ahci_port_select(ahci);
1095 ahci_port_clear(ahci, port);
1096
1097 make_dirty(ahci, port);
1098
1099 ahci_test_flush(ahci);
1100 ahci_shutdown(ahci);
1101}
1102
1103static void test_flush_retry(void)
1104{
1105 AHCIQState *ahci;
1106 AHCICommand *cmd;
1107 uint8_t port;
1108
1109 prepare_blkdebug_script(debug_path, "flush_to_disk");
1110 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1111 "format=%s,cache=writeback,"
1112 "rerror=stop,werror=stop "
1113 "-M q35 "
1114 "-device ide-hd,drive=drive0 ",
1115 debug_path,
1116 tmp_path, imgfmt);
1117
1118 port = ahci_port_select(ahci);
1119 ahci_port_clear(ahci, port);
1120
1121
1122 make_dirty(ahci, port);
1123
1124
1125 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1126 ahci_guest_io_resume(ahci, cmd);
1127
1128 ahci_shutdown(ahci);
1129}
1130
1131
1132
1133
1134static void test_migrate_sanity(void)
1135{
1136 AHCIQState *src, *dst;
1137 char *uri = g_strdup_printf("unix:%s", mig_socket);
1138
1139 src = ahci_boot("-m 384 -M q35 "
1140 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1141 dst = ahci_boot("-m 384 -M q35 "
1142 "-drive if=ide,file=%s,format=%s "
1143 "-incoming %s", tmp_path, imgfmt, uri);
1144
1145 ahci_migrate(src, dst, uri);
1146
1147 ahci_shutdown(src);
1148 ahci_shutdown(dst);
1149 g_free(uri);
1150}
1151
1152
1153
1154
1155static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1156{
1157 AHCIQState *src, *dst;
1158 uint8_t px;
1159 size_t bufsize = 4096;
1160 unsigned char *tx = g_malloc(bufsize);
1161 unsigned char *rx = g_malloc0(bufsize);
1162 char *uri = g_strdup_printf("unix:%s", mig_socket);
1163
1164 src = ahci_boot_and_enable("-m 384 -M q35 "
1165 "-drive if=ide,format=%s,file=%s ",
1166 imgfmt, tmp_path);
1167 dst = ahci_boot("-m 384 -M q35 "
1168 "-drive if=ide,format=%s,file=%s "
1169 "-incoming %s", imgfmt, tmp_path, uri);
1170
1171
1172 px = ahci_port_select(src);
1173 ahci_port_clear(src, px);
1174
1175
1176 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1177
1178
1179 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1180 ahci_migrate(src, dst, uri);
1181 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1182
1183
1184 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1185
1186 ahci_shutdown(src);
1187 ahci_shutdown(dst);
1188 g_free(rx);
1189 g_free(tx);
1190 g_free(uri);
1191}
1192
1193static void test_migrate_dma(void)
1194{
1195 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1196}
1197
1198static void test_migrate_ncq(void)
1199{
1200 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1201}
1202
1203
1204
1205
1206
1207
1208
1209
1210static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1211{
1212 AHCIQState *ahci;
1213 uint8_t port;
1214 size_t bufsize = 4096;
1215 unsigned char *tx = g_malloc(bufsize);
1216 unsigned char *rx = g_malloc0(bufsize);
1217 uint64_t ptr;
1218 AHCICommand *cmd;
1219
1220 prepare_blkdebug_script(debug_path, "write_aio");
1221
1222 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1223 "format=%s,cache=writeback,"
1224 "rerror=stop,werror=stop "
1225 "-M q35 "
1226 "-device ide-hd,drive=drive0 ",
1227 debug_path,
1228 tmp_path, imgfmt);
1229
1230
1231 port = ahci_port_select(ahci);
1232 ahci_port_clear(ahci, port);
1233
1234
1235 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1236 ptr = ahci_alloc(ahci, bufsize);
1237 g_assert(ptr);
1238 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize);
1239
1240
1241 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1242 ptr, bufsize, 0);
1243
1244
1245 ahci_guest_io_resume(ahci, cmd);
1246 ahci_free(ahci, ptr);
1247
1248
1249 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1250 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1251
1252
1253 ahci_shutdown(ahci);
1254 g_free(rx);
1255 g_free(tx);
1256}
1257
1258static void test_halted_dma(void)
1259{
1260 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1261}
1262
1263static void test_halted_ncq(void)
1264{
1265 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1266}
1267
1268
1269
1270
1271
1272
1273
1274
1275static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1276{
1277 AHCIQState *src, *dst;
1278 uint8_t port;
1279 size_t bufsize = 4096;
1280 unsigned char *tx = g_malloc(bufsize);
1281 unsigned char *rx = g_malloc0(bufsize);
1282 uint64_t ptr;
1283 AHCICommand *cmd;
1284 char *uri = g_strdup_printf("unix:%s", mig_socket);
1285
1286 prepare_blkdebug_script(debug_path, "write_aio");
1287
1288 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1289 "format=%s,cache=writeback,"
1290 "rerror=stop,werror=stop "
1291 "-M q35 "
1292 "-device ide-hd,drive=drive0 ",
1293 debug_path,
1294 tmp_path, imgfmt);
1295
1296 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1297 "format=%s,cache=writeback,"
1298 "rerror=stop,werror=stop "
1299 "-M q35 "
1300 "-device ide-hd,drive=drive0 "
1301 "-incoming %s",
1302 tmp_path, imgfmt, uri);
1303
1304
1305 port = ahci_port_select(src);
1306 ahci_port_clear(src, port);
1307 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1308
1309
1310 ptr = ahci_alloc(src, bufsize);
1311 g_assert(ptr);
1312 qtest_memwrite(src->parent->qts, ptr, tx, bufsize);
1313
1314
1315 cmd = ahci_guest_io_halt(src, port, cmd_write,
1316 ptr, bufsize, 0);
1317 ahci_migrate(src, dst, uri);
1318 ahci_guest_io_resume(dst, cmd);
1319 ahci_free(dst, ptr);
1320
1321
1322 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1323
1324
1325 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1326
1327
1328 ahci_shutdown(src);
1329 ahci_shutdown(dst);
1330 g_free(rx);
1331 g_free(tx);
1332 g_free(uri);
1333}
1334
1335static void test_migrate_halted_dma(void)
1336{
1337 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1338}
1339
1340static void test_migrate_halted_ncq(void)
1341{
1342 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1343}
1344
1345
1346
1347
1348static void test_flush_migrate(void)
1349{
1350 AHCIQState *src, *dst;
1351 AHCICommand *cmd;
1352 uint8_t px;
1353 char *uri = g_strdup_printf("unix:%s", mig_socket);
1354
1355 prepare_blkdebug_script(debug_path, "flush_to_disk");
1356
1357 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1358 "cache=writeback,rerror=stop,werror=stop,"
1359 "format=%s "
1360 "-M q35 "
1361 "-device ide-hd,drive=drive0 ",
1362 debug_path, tmp_path, imgfmt);
1363 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1364 "cache=writeback,rerror=stop,werror=stop,"
1365 "format=%s "
1366 "-M q35 "
1367 "-device ide-hd,drive=drive0 "
1368 "-incoming %s", tmp_path, imgfmt, uri);
1369
1370 px = ahci_port_select(src);
1371 ahci_port_clear(src, px);
1372
1373
1374 make_dirty(src, px);
1375
1376
1377 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1378 ahci_command_commit(src, cmd, px);
1379 ahci_command_issue_async(src, cmd);
1380 qtest_qmp_eventwait(src->parent->qts, "STOP");
1381
1382
1383 ahci_migrate(src, dst, uri);
1384
1385
1386 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }");
1387 qtest_qmp_eventwait(dst->parent->qts, "RESUME");
1388 ahci_command_wait(dst, cmd);
1389 ahci_command_verify(dst, cmd);
1390
1391 ahci_command_free(cmd);
1392 ahci_shutdown(src);
1393 ahci_shutdown(dst);
1394 g_free(uri);
1395}
1396
1397static void test_max(void)
1398{
1399 AHCIQState *ahci;
1400
1401 ahci = ahci_boot_and_enable(NULL);
1402 ahci_test_max(ahci);
1403 ahci_shutdown(ahci);
1404}
1405
1406static void test_reset(void)
1407{
1408 AHCIQState *ahci;
1409 int i;
1410
1411 ahci = ahci_boot(NULL);
1412 ahci_test_pci_spec(ahci);
1413 ahci_pci_enable(ahci);
1414
1415 for (i = 0; i < 2; i++) {
1416 ahci_test_hba_spec(ahci);
1417 ahci_hba_enable(ahci);
1418 ahci_test_identify(ahci);
1419 ahci_test_io_rw_simple(ahci, 4096, 0,
1420 CMD_READ_DMA_EXT,
1421 CMD_WRITE_DMA_EXT);
1422 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1423 ahci_clean_mem(ahci);
1424 }
1425
1426 ahci_shutdown(ahci);
1427}
1428
1429static void test_ncq_simple(void)
1430{
1431 AHCIQState *ahci;
1432
1433 ahci = ahci_boot_and_enable(NULL);
1434 ahci_test_io_rw_simple(ahci, 4096, 0,
1435 READ_FPDMA_QUEUED,
1436 WRITE_FPDMA_QUEUED);
1437 ahci_shutdown(ahci);
1438}
1439
1440static int prepare_iso(size_t size, unsigned char **buf, char **name)
1441{
1442 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1443 unsigned char *patt;
1444 ssize_t ret;
1445 int fd = mkstemp(cdrom_path);
1446
1447 g_assert(buf);
1448 g_assert(name);
1449 patt = g_malloc(size);
1450
1451
1452 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1453 ret = write(fd, patt, size);
1454 g_assert(ret == size);
1455
1456 *name = g_strdup(cdrom_path);
1457 *buf = patt;
1458 return fd;
1459}
1460
1461static void remove_iso(int fd, char *name)
1462{
1463 unlink(name);
1464 g_free(name);
1465 close(fd);
1466}
1467
1468static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1469 const AHCIOpts *opts)
1470{
1471 unsigned char *tx = opts->opaque;
1472 unsigned char *rx;
1473
1474 if (!opts->size) {
1475 return 0;
1476 }
1477
1478 rx = g_malloc0(opts->size);
1479 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
1480 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1481 g_free(rx);
1482
1483 return 0;
1484}
1485
1486static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1487 bool override_bcl, uint16_t bcl)
1488{
1489 AHCIQState *ahci;
1490 unsigned char *tx;
1491 char *iso;
1492 int fd;
1493 AHCIOpts opts = {
1494 .size = (ATAPI_SECTOR_SIZE * nsectors),
1495 .atapi = true,
1496 .atapi_dma = dma,
1497 .post_cb = ahci_cb_cmp_buff,
1498 .set_bcl = override_bcl,
1499 .bcl = bcl,
1500 };
1501 uint64_t iso_size = ATAPI_SECTOR_SIZE * (nsectors + 1);
1502
1503
1504 fd = prepare_iso(iso_size, &tx, &iso);
1505 opts.opaque = tx;
1506
1507
1508 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1509 "-M q35 "
1510 "-device ide-cd,drive=drive0 ", iso);
1511
1512
1513 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1514
1515
1516 g_free(tx);
1517 ahci_shutdown(ahci);
1518 remove_iso(fd, iso);
1519}
1520
1521static void ahci_test_cdrom_read10(int nsectors, bool dma)
1522{
1523 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1524}
1525
1526static void test_cdrom_dma(void)
1527{
1528 ahci_test_cdrom_read10(1, true);
1529}
1530
1531static void test_cdrom_dma_multi(void)
1532{
1533 ahci_test_cdrom_read10(3, true);
1534}
1535
1536static void test_cdrom_pio(void)
1537{
1538 ahci_test_cdrom_read10(1, false);
1539}
1540
1541static void test_cdrom_pio_multi(void)
1542{
1543 ahci_test_cdrom_read10(3, false);
1544}
1545
1546
1547
1548static void test_atapi_bcl(void)
1549{
1550 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
1551}
1552
1553
1554static void atapi_wait_tray(AHCIQState *ahci, bool open)
1555{
1556 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts,
1557 "DEVICE_TRAY_MOVED");
1558 QDict *data = qdict_get_qdict(rsp, "data");
1559 if (open) {
1560 g_assert(qdict_get_bool(data, "tray-open"));
1561 } else {
1562 g_assert(!qdict_get_bool(data, "tray-open"));
1563 }
1564 qobject_unref(rsp);
1565}
1566
1567static void test_atapi_tray(void)
1568{
1569 AHCIQState *ahci;
1570 unsigned char *tx;
1571 char *iso;
1572 int fd;
1573 uint8_t port, sense, asc;
1574 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1575 QDict *rsp;
1576
1577 fd = prepare_iso(iso_size, &tx, &iso);
1578 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1579 "-M q35 "
1580 "-device ide-cd,id=cd0,drive=drive0 ", iso);
1581 port = ahci_port_select(ahci);
1582
1583 ahci_atapi_eject(ahci, port);
1584 atapi_wait_tray(ahci, true);
1585
1586 ahci_atapi_load(ahci, port);
1587 atapi_wait_tray(ahci, false);
1588
1589
1590 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', "
1591 "'arguments': {'id': 'cd0'}}");
1592 atapi_wait_tray(ahci, true);
1593 rsp = qtest_qmp_receive(ahci->parent->qts);
1594 qobject_unref(rsp);
1595
1596 qmp_discard_response(ahci->parent->qts,
1597 "{'execute': 'blockdev-remove-medium', "
1598 "'arguments': {'id': 'cd0'}}");
1599
1600
1601 ahci_atapi_load(ahci, port);
1602 atapi_wait_tray(ahci, false);
1603
1604 ahci_atapi_eject(ahci, port);
1605 atapi_wait_tray(ahci, true);
1606
1607
1608 qmp_discard_response(ahci->parent->qts,
1609 "{'execute': 'blockdev-add', "
1610 "'arguments': {'node-name': 'node0', "
1611 "'driver': 'raw', "
1612 "'file': { 'driver': 'file', "
1613 "'filename': %s }}}", iso);
1614 qmp_discard_response(ahci->parent->qts,
1615 "{'execute': 'blockdev-insert-medium',"
1616 "'arguments': { 'id': 'cd0', "
1617 "'node-name': 'node0' }}");
1618
1619
1620 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', "
1621 "'arguments': {'id': 'cd0'}}");
1622 atapi_wait_tray(ahci, false);
1623 rsp = qtest_qmp_receive(ahci->parent->qts);
1624 qobject_unref(rsp);
1625
1626
1627 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1628 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1629 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1630 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1631
1632 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1633 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1634 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1635 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1636
1637 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1638 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1639 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1640
1641
1642 ahci_atapi_eject(ahci, port);
1643 atapi_wait_tray(ahci, true);
1644
1645 ahci_atapi_load(ahci, port);
1646 atapi_wait_tray(ahci, false);
1647
1648
1649 g_free(tx);
1650 ahci_shutdown(ahci);
1651 remove_iso(fd, iso);
1652}
1653
1654
1655
1656
1657enum BuffLen {
1658 LEN_BEGIN = 0,
1659 LEN_SIMPLE = LEN_BEGIN,
1660 LEN_DOUBLE,
1661 LEN_LONG,
1662 LEN_SHORT,
1663 NUM_LENGTHS
1664};
1665
1666static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1667 "long", "short" };
1668
1669enum AddrMode {
1670 ADDR_MODE_BEGIN = 0,
1671 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1672 ADDR_MODE_LBA48,
1673 NUM_ADDR_MODES
1674};
1675
1676static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1677
1678enum IOMode {
1679 MODE_BEGIN = 0,
1680 MODE_PIO = MODE_BEGIN,
1681 MODE_DMA,
1682 NUM_MODES
1683};
1684
1685static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1686
1687enum IOOps {
1688 IO_BEGIN = 0,
1689 IO_READ = IO_BEGIN,
1690 IO_WRITE,
1691 NUM_IO_OPS
1692};
1693
1694enum OffsetType {
1695 OFFSET_BEGIN = 0,
1696 OFFSET_ZERO = OFFSET_BEGIN,
1697 OFFSET_LOW,
1698 OFFSET_HIGH,
1699 NUM_OFFSETS
1700};
1701
1702static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1703
1704typedef struct AHCIIOTestOptions {
1705 enum BuffLen length;
1706 enum AddrMode address_type;
1707 enum IOMode io_type;
1708 enum OffsetType offset;
1709} AHCIIOTestOptions;
1710
1711static uint64_t offset_sector(enum OffsetType ofst,
1712 enum AddrMode addr_type,
1713 uint64_t buffsize)
1714{
1715 uint64_t ceil;
1716 uint64_t nsectors;
1717
1718 switch (ofst) {
1719 case OFFSET_ZERO:
1720 return 0;
1721 case OFFSET_LOW:
1722 return 1;
1723 case OFFSET_HIGH:
1724 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1725 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1726 nsectors = buffsize / AHCI_SECTOR_SIZE;
1727 return ceil - nsectors + 1;
1728 default:
1729 g_assert_not_reached();
1730 }
1731}
1732
1733
1734
1735
1736static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1737 [MODE_PIO] = {
1738 [ADDR_MODE_LBA28] = {
1739 [IO_READ] = CMD_READ_PIO,
1740 [IO_WRITE] = CMD_WRITE_PIO },
1741 [ADDR_MODE_LBA48] = {
1742 [IO_READ] = CMD_READ_PIO_EXT,
1743 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1744 },
1745 [MODE_DMA] = {
1746 [ADDR_MODE_LBA28] = {
1747 [IO_READ] = CMD_READ_DMA,
1748 [IO_WRITE] = CMD_WRITE_DMA },
1749 [ADDR_MODE_LBA48] = {
1750 [IO_READ] = CMD_READ_DMA_EXT,
1751 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1752 }
1753};
1754
1755
1756
1757
1758
1759static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1760 unsigned bufsize, uint64_t sector)
1761{
1762 AHCIQState *ahci;
1763
1764 ahci = ahci_boot_and_enable(NULL);
1765 ahci_test_io_rw_simple(ahci, bufsize, sector,
1766 io_cmds[dma][lba48][IO_READ],
1767 io_cmds[dma][lba48][IO_WRITE]);
1768 ahci_shutdown(ahci);
1769}
1770
1771
1772
1773
1774static void test_io_interface(gconstpointer opaque)
1775{
1776 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1777 unsigned bufsize;
1778 uint64_t sector;
1779
1780 switch (opts->length) {
1781 case LEN_SIMPLE:
1782 bufsize = 4096;
1783 break;
1784 case LEN_DOUBLE:
1785 bufsize = 8192;
1786 break;
1787 case LEN_LONG:
1788 bufsize = 4096 * 64;
1789 break;
1790 case LEN_SHORT:
1791 bufsize = 512;
1792 break;
1793 default:
1794 g_assert_not_reached();
1795 }
1796
1797 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1798 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1799 g_free(opts);
1800 return;
1801}
1802
1803static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1804 enum BuffLen len, enum OffsetType offset)
1805{
1806 char *name;
1807 AHCIIOTestOptions *opts;
1808
1809 opts = g_new(AHCIIOTestOptions, 1);
1810 opts->length = len;
1811 opts->address_type = addr;
1812 opts->io_type = type;
1813 opts->offset = offset;
1814
1815 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1816 io_mode_str[type],
1817 addr_mode_str[addr],
1818 buff_len_str[len],
1819 offset_str[offset]);
1820
1821 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1822 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1823 g_test_message("%s: skipped; test image too small", name);
1824 g_free(opts);
1825 g_free(name);
1826 return;
1827 }
1828
1829 qtest_add_data_func(name, opts, test_io_interface);
1830 g_free(name);
1831}
1832
1833
1834
1835int main(int argc, char **argv)
1836{
1837 const char *arch;
1838 int ret;
1839 int fd;
1840 int c;
1841 int i, j, k, m;
1842
1843 static struct option long_options[] = {
1844 {"pedantic", no_argument, 0, 'p' },
1845 {0, 0, 0, 0},
1846 };
1847
1848
1849 g_test_init(&argc, &argv, NULL);
1850
1851 while (1) {
1852 c = getopt_long(argc, argv, "", long_options, NULL);
1853 if (c == -1) {
1854 break;
1855 }
1856 switch (c) {
1857 case -1:
1858 break;
1859 case 'p':
1860 ahci_pedantic = 1;
1861 break;
1862 default:
1863 fprintf(stderr, "Unrecognized ahci_test option.\n");
1864 g_assert_not_reached();
1865 }
1866 }
1867
1868
1869 arch = qtest_get_arch();
1870 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1871 g_test_message("Skipping test for non-x86");
1872 return 0;
1873 }
1874
1875
1876 fd = mkstemp(tmp_path);
1877 g_assert(fd >= 0);
1878 if (have_qemu_img()) {
1879 imgfmt = "qcow2";
1880 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1881 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1882 } else {
1883 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1884 "skipping LBA48 high-sector tests");
1885 imgfmt = "raw";
1886 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1887 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1888 g_assert(ret == 0);
1889 }
1890 close(fd);
1891
1892
1893 fd = mkstemp(debug_path);
1894 g_assert(fd >= 0);
1895 close(fd);
1896
1897
1898 fd = mkstemp(mig_socket);
1899 g_assert(fd >= 0);
1900 close(fd);
1901
1902
1903 qtest_add_func("/ahci/sanity", test_sanity);
1904 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1905 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1906 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1907 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1908 qtest_add_func("/ahci/identify", test_identify);
1909
1910 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1911 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1912 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1913 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1914 create_ahci_io_test(i, j, k, m);
1915 }
1916 }
1917 }
1918 }
1919
1920 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1921
1922 qtest_add_func("/ahci/flush/simple", test_flush);
1923 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1924 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1925
1926 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1927 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1928 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1929 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1930
1931 qtest_add_func("/ahci/max", test_max);
1932 qtest_add_func("/ahci/reset", test_reset);
1933
1934 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1935 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1936 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1937 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1938
1939 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1940 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1941 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1942 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1943
1944 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
1945 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
1946
1947 ret = g_test_run();
1948
1949
1950 unlink(tmp_path);
1951 unlink(debug_path);
1952 unlink(mig_socket);
1953
1954 return ret;
1955}
1956