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14#include "qemu/osdep.h"
15#include "qemu/error-report.h"
16#include "qapi/error.h"
17#include "hw/arm/pxa.h"
18#include "hw/arm/boot.h"
19#include "net/net.h"
20#include "hw/net/smc91c111.h"
21#include "hw/boards.h"
22#include "hw/block/flash.h"
23#include "hw/sysbus.h"
24#include "exec/address-spaces.h"
25#include "sysemu/qtest.h"
26#include "cpu.h"
27
28
29#define MST_FPGA_PHYS 0x08000000
30#define MST_ETH_PHYS 0x10000300
31#define MST_FLASH_0 0x00000000
32#define MST_FLASH_1 0x04000000
33
34
35#define MMC_IRQ 0
36#define USIM_IRQ 1
37#define USBC_IRQ 2
38#define ETHERNET_IRQ 3
39#define AC97_IRQ 4
40#define PEN_IRQ 5
41#define MSINS_IRQ 6
42#define EXBRD_IRQ 7
43#define S0_CD_IRQ 9
44#define S0_STSCHG_IRQ 10
45#define S0_IRQ 11
46#define S1_CD_IRQ 13
47#define S1_STSCHG_IRQ 14
48#define S1_IRQ 15
49
50static const struct keymap map[0xE0] = {
51 [0 ... 0xDF] = { -1, -1 },
52 [0x1e] = {0,0},
53 [0x30] = {0,1},
54 [0x2e] = {0,2},
55 [0x20] = {0,3},
56 [0x12] = {0,4},
57 [0x21] = {0,5},
58 [0x22] = {1,0},
59 [0x23] = {1,1},
60 [0x17] = {1,2},
61 [0x24] = {1,3},
62 [0x25] = {1,4},
63 [0x26] = {1,5},
64 [0x32] = {2,0},
65 [0x31] = {2,1},
66 [0x18] = {2,2},
67 [0x19] = {2,3},
68 [0x10] = {2,4},
69 [0x13] = {2,5},
70 [0x1f] = {3,0},
71 [0x14] = {3,1},
72 [0x16] = {3,2},
73 [0x2f] = {3,3},
74 [0x11] = {3,4},
75 [0x2d] = {3,5},
76 [0x34] = {4,0},
77 [0x15] = {4,2},
78 [0x2c] = {4,3},
79 [0x35] = {4,4},
80 [0xc7] = {5,0},
81 [0x2a] = {5,1},
82
83
84
85
86
87
88 [0x39] = {5,3},
89
90
91
92
93 [0x1c] = {5,4},
94 [0x0e] = {5,5},
95 [0xc8] = {6,0},
96 [0xd0] = {6,1},
97 [0xcb] = {6,2},
98 [0xcd] = {6,3},
99};
100
101enum mainstone_model_e { mainstone };
102
103#define MAINSTONE_RAM 0x04000000
104#define MAINSTONE_ROM 0x00800000
105#define MAINSTONE_FLASH 0x02000000
106
107static struct arm_boot_info mainstone_binfo = {
108 .loader_start = PXA2XX_SDRAM_BASE,
109 .ram_size = 0x04000000,
110};
111
112static void mainstone_common_init(MemoryRegion *address_space_mem,
113 MachineState *machine,
114 enum mainstone_model_e model, int arm_id)
115{
116 uint32_t sector_len = 256 * 1024;
117 hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
118 PXA2xxState *mpu;
119 DeviceState *mst_irq;
120 DriveInfo *dinfo;
121 int i;
122 int be;
123 MemoryRegion *rom = g_new(MemoryRegion, 1);
124
125
126 mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
127 machine->cpu_type);
128 memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
129 &error_fatal);
130 memory_region_set_readonly(rom, true);
131 memory_region_add_subregion(address_space_mem, 0, rom);
132
133#ifdef TARGET_WORDS_BIGENDIAN
134 be = 1;
135#else
136 be = 0;
137#endif
138
139 for (i = 0; i < 2; i ++) {
140 dinfo = drive_get(IF_PFLASH, 0, i);
141 if (!dinfo) {
142 if (qtest_enabled()) {
143 break;
144 }
145 error_report("Two flash images must be given with the "
146 "'pflash' parameter");
147 exit(1);
148 }
149
150 if (!pflash_cfi01_register(mainstone_flash_base[i],
151 i ? "mainstone.flash1" : "mainstone.flash0",
152 MAINSTONE_FLASH,
153 blk_by_legacy_dinfo(dinfo),
154 sector_len, 4, 0, 0, 0, 0, be)) {
155 error_report("Error registering flash memory");
156 exit(1);
157 }
158 }
159
160 mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
161 qdev_get_gpio_in(mpu->gpio, 0));
162
163
164 pxa27x_register_keypad(mpu->kp, map, 0xe0);
165
166
167 pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
168
169 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
170 qdev_get_gpio_in(mst_irq, S0_IRQ),
171 qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
172 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
173 qdev_get_gpio_in(mst_irq, S1_IRQ),
174 qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
175
176 smc91c111_init(&nd_table[0], MST_ETH_PHYS,
177 qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
178
179 mainstone_binfo.board_id = arm_id;
180 arm_load_kernel(mpu->cpu, machine, &mainstone_binfo);
181}
182
183static void mainstone_init(MachineState *machine)
184{
185 mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
186}
187
188static void mainstone2_machine_init(MachineClass *mc)
189{
190 mc->desc = "Mainstone II (PXA27x)";
191 mc->init = mainstone_init;
192 mc->ignore_memory_transaction_failures = true;
193 mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
194}
195
196DEFINE_MACHINE("mainstone", mainstone2_machine_init)
197