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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu/cutils.h"
25#include "qemu/bswap.h"
26#include "sysemu/reset.h"
27#include "sysemu/runstate.h"
28#include "sysemu/sysemu.h"
29#include "hw/arm/omap.h"
30#include "hw/arm/boot.h"
31#include "hw/irq.h"
32#include "ui/console.h"
33#include "hw/boards.h"
34#include "hw/i2c/i2c.h"
35#include "hw/display/blizzard.h"
36#include "hw/input/tsc2xxx.h"
37#include "hw/misc/cbus.h"
38#include "hw/misc/tmp105.h"
39#include "hw/qdev-properties.h"
40#include "hw/block/flash.h"
41#include "hw/hw.h"
42#include "hw/bt.h"
43#include "hw/loader.h"
44#include "hw/sysbus.h"
45#include "qemu/log.h"
46#include "exec/address-spaces.h"
47
48
49struct n800_s {
50 MemoryRegion sdram;
51 struct omap_mpu_state_s *mpu;
52
53 struct rfbi_chip_s blizzard;
54 struct {
55 void *opaque;
56 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
57 uWireSlave *chip;
58 } ts;
59
60 int keymap[0x80];
61 DeviceState *kbd;
62
63 DeviceState *usb;
64 void *retu;
65 void *tahvo;
66 DeviceState *nand;
67};
68
69
70#define N8X0_TUSB_ENABLE_GPIO 0
71#define N800_MMC2_WP_GPIO 8
72#define N800_UNKNOWN_GPIO0 9
73#define N810_MMC2_VIOSD_GPIO 9
74#define N810_HEADSET_AMP_GPIO 10
75#define N800_CAM_TURN_GPIO 12
76#define N810_GPS_RESET_GPIO 12
77#define N800_BLIZZARD_POWERDOWN_GPIO 15
78#define N800_MMC1_WP_GPIO 23
79#define N810_MMC2_VSD_GPIO 23
80#define N8X0_ONENAND_GPIO 26
81#define N810_BLIZZARD_RESET_GPIO 30
82#define N800_UNKNOWN_GPIO2 53
83#define N8X0_TUSB_INT_GPIO 58
84#define N8X0_BT_WKUP_GPIO 61
85#define N8X0_STI_GPIO 62
86#define N8X0_CBUS_SEL_GPIO 64
87#define N8X0_CBUS_DAT_GPIO 65
88#define N8X0_CBUS_CLK_GPIO 66
89#define N8X0_WLAN_IRQ_GPIO 87
90#define N8X0_BT_RESET_GPIO 92
91#define N8X0_TEA5761_CS_GPIO 93
92#define N800_UNKNOWN_GPIO 94
93#define N810_TSC_RESET_GPIO 94
94#define N800_CAM_ACT_GPIO 95
95#define N810_GPS_WAKEUP_GPIO 95
96#define N8X0_MMC_CS_GPIO 96
97#define N8X0_WLAN_PWR_GPIO 97
98#define N8X0_BT_HOST_WKUP_GPIO 98
99#define N810_SPEAKER_AMP_GPIO 101
100#define N810_KB_LOCK_GPIO 102
101#define N800_TSC_TS_GPIO 103
102#define N810_TSC_TS_GPIO 106
103#define N8X0_HEADPHONE_GPIO 107
104#define N8X0_RETU_GPIO 108
105#define N800_TSC_KP_IRQ_GPIO 109
106#define N810_KEYBOARD_GPIO 109
107#define N800_BAT_COVER_GPIO 110
108#define N810_SLIDE_GPIO 110
109#define N8X0_TAHVO_GPIO 111
110#define N800_UNKNOWN_GPIO4 112
111#define N810_SLEEPX_LED_GPIO 112
112#define N800_TSC_RESET_GPIO 118
113#define N810_AIC33_RESET_GPIO 118
114#define N800_TSC_UNKNOWN_GPIO 119
115#define N8X0_TMP105_GPIO 125
116
117
118#define BT_UART 0
119#define XLDR_LL_UART 1
120
121
122#define N810_TLV320AIC33_ADDR 0x18
123#define N8X0_TCM825x_ADDR 0x29
124#define N810_LP5521_ADDR 0x32
125#define N810_TSL2563_ADDR 0x3d
126#define N810_LM8323_ADDR 0x45
127
128#define N8X0_TMP105_ADDR 0x48
129#define N8X0_MENELAUS_ADDR 0x72
130
131
132#define N8X0_ONENAND_CS 0
133#define N8X0_USB_ASYNC_CS 1
134#define N8X0_USB_SYNC_CS 4
135
136#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
137
138static void n800_mmc_cs_cb(void *opaque, int line, int level)
139{
140
141
142 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
143}
144
145static void n8x0_gpio_setup(struct n800_s *s)
146{
147 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
148 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
149 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
150}
151
152#define MAEMO_CAL_HEADER(...) \
153 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
154 __VA_ARGS__, \
155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
156
157static const uint8_t n8x0_cal_wlan_mac[] = {
158 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
159 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
160 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
161 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
162 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
163 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
164};
165
166static const uint8_t n8x0_cal_bt_id[] = {
167 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
168 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
169 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
170 N8X0_BD_ADDR,
171};
172
173static void n8x0_nand_setup(struct n800_s *s)
174{
175 char *otp_region;
176 DriveInfo *dinfo;
177
178 s->nand = qdev_create(NULL, "onenand");
179 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
180
181 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
182 qdev_prop_set_uint16(s->nand, "version_id", 0);
183 qdev_prop_set_int32(s->nand, "shift", 1);
184 dinfo = drive_get(IF_MTD, 0, 0);
185 if (dinfo) {
186 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
187 &error_fatal);
188 }
189 qdev_init_nofail(s->nand);
190 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
191 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
192 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
193 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
194 otp_region = onenand_raw_otp(s->nand);
195
196 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
197 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
198
199}
200
201static qemu_irq n8x0_system_powerdown;
202
203static void n8x0_powerdown_req(Notifier *n, void *opaque)
204{
205 qemu_irq_raise(n8x0_system_powerdown);
206}
207
208static Notifier n8x0_system_powerdown_notifier = {
209 .notify = n8x0_powerdown_req
210};
211
212static void n8x0_i2c_setup(struct n800_s *s)
213{
214 DeviceState *dev;
215 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
216 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
217
218
219 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
220 qdev_connect_gpio_out(dev, 3,
221 qdev_get_gpio_in(s->mpu->ih[0],
222 OMAP_INT_24XX_SYS_NIRQ));
223
224 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
225 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
226
227
228 dev = i2c_create_slave(i2c, TYPE_TMP105, N8X0_TMP105_ADDR);
229 qdev_connect_gpio_out(dev, 0, tmp_irq);
230}
231
232
233static MouseTransformInfo n800_pointercal = {
234 .x = 800,
235 .y = 480,
236 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
237};
238
239static MouseTransformInfo n810_pointercal = {
240 .x = 800,
241 .y = 480,
242 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
243};
244
245#define RETU_KEYCODE 61
246
247static void n800_key_event(void *opaque, int keycode)
248{
249 struct n800_s *s = (struct n800_s *) opaque;
250 int code = s->keymap[keycode & 0x7f];
251
252 if (code == -1) {
253 if ((keycode & 0x7f) == RETU_KEYCODE) {
254 retu_key_event(s->retu, !(keycode & 0x80));
255 }
256 return;
257 }
258
259 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
260}
261
262static const int n800_keys[16] = {
263 -1,
264 72,
265 63,
266 -1,
267 75,
268 28,
269 77,
270 -1,
271 1,
272 80,
273 62,
274 -1,
275 66,
276 64,
277 65,
278 -1,
279};
280
281static void n800_tsc_kbd_setup(struct n800_s *s)
282{
283 int i;
284
285
286
287 qemu_irq penirq = NULL;
288 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
289 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
290
291 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
292 s->ts.opaque = s->ts.chip->opaque;
293 s->ts.txrx = tsc210x_txrx;
294
295 for (i = 0; i < 0x80; i++) {
296 s->keymap[i] = -1;
297 }
298 for (i = 0; i < 0x10; i++) {
299 if (n800_keys[i] >= 0) {
300 s->keymap[n800_keys[i]] = i;
301 }
302 }
303
304 qemu_add_kbd_event_handler(n800_key_event, s);
305
306 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
307}
308
309static void n810_tsc_setup(struct n800_s *s)
310{
311 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
312
313 s->ts.opaque = tsc2005_init(pintdav);
314 s->ts.txrx = tsc2005_txrx;
315
316 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
317}
318
319
320static void n810_key_event(void *opaque, int keycode)
321{
322 struct n800_s *s = (struct n800_s *) opaque;
323 int code = s->keymap[keycode & 0x7f];
324
325 if (code == -1) {
326 if ((keycode & 0x7f) == RETU_KEYCODE) {
327 retu_key_event(s->retu, !(keycode & 0x80));
328 }
329 return;
330 }
331
332 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
333}
334
335#define M 0
336
337static int n810_keys[0x80] = {
338 [0x01] = 16,
339 [0x02] = 37,
340 [0x03] = 24,
341 [0x04] = 25,
342 [0x05] = 14,
343 [0x06] = 30,
344 [0x07] = 31,
345 [0x08] = 32,
346 [0x09] = 33,
347 [0x0a] = 34,
348 [0x0b] = 35,
349 [0x0c] = 36,
350
351 [0x11] = 17,
352 [0x12] = 62,
353 [0x13] = 38,
354 [0x14] = 40,
355 [0x16] = 44,
356 [0x17] = 45,
357 [0x18] = 46,
358 [0x19] = 47,
359 [0x1a] = 48,
360 [0x1b] = 49,
361 [0x1c] = 42,
362 [0x1f] = 65,
363
364 [0x21] = 18,
365 [0x22] = 39,
366 [0x23] = 12,
367 [0x24] = 13,
368 [0x2b] = 56,
369 [0x2c] = 50,
370 [0x2f] = 66,
371
372 [0x31] = 19,
373 [0x32] = 29 | M,
374 [0x34] = 57,
375 [0x35] = 51,
376 [0x37] = 72 | M,
377 [0x3c] = 82 | M,
378 [0x3f] = 64,
379
380 [0x41] = 20,
381 [0x44] = 52,
382 [0x46] = 77 | M,
383 [0x4f] = 63,
384 [0x51] = 21,
385 [0x53] = 80 | M,
386 [0x55] = 28,
387 [0x5f] = 1,
388
389 [0x61] = 22,
390 [0x64] = 75 | M,
391
392 [0x71] = 23,
393#if 0
394 [0x75] = 28 | M,
395#else
396 [0x75] = 15,
397#endif
398};
399
400#undef M
401
402static void n810_kbd_setup(struct n800_s *s)
403{
404 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
405 int i;
406
407 for (i = 0; i < 0x80; i++) {
408 s->keymap[i] = -1;
409 }
410 for (i = 0; i < 0x80; i++) {
411 if (n810_keys[i] > 0) {
412 s->keymap[n810_keys[i]] = i;
413 }
414 }
415
416 qemu_add_kbd_event_handler(n810_key_event, s);
417
418
419
420 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
421 "lm8323", N810_LM8323_ADDR);
422 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
423}
424
425
426struct mipid_s {
427 int resp[4];
428 int param[4];
429 int p;
430 int pm;
431 int cmd;
432
433 int sleep;
434 int booster;
435 int te;
436 int selfcheck;
437 int partial;
438 int normal;
439 int vscr;
440 int invert;
441 int onoff;
442 int gamma;
443 uint32_t id;
444};
445
446static void mipid_reset(struct mipid_s *s)
447{
448 s->pm = 0;
449 s->cmd = 0;
450
451 s->sleep = 1;
452 s->booster = 0;
453 s->selfcheck =
454 (1 << 7) |
455 (1 << 5) |
456 (1 << 4);
457 s->te = 0;
458 s->partial = 0;
459 s->normal = 1;
460 s->vscr = 0;
461 s->invert = 0;
462 s->onoff = 1;
463 s->gamma = 0;
464}
465
466static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
467{
468 struct mipid_s *s = (struct mipid_s *) opaque;
469 uint8_t ret;
470
471 if (len > 9) {
472 hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
473 }
474
475 if (s->p >= ARRAY_SIZE(s->resp)) {
476 ret = 0;
477 } else {
478 ret = s->resp[s->p++];
479 }
480 if (s->pm-- > 0) {
481 s->param[s->pm] = cmd;
482 } else {
483 s->cmd = cmd;
484 }
485
486 switch (s->cmd) {
487 case 0x00:
488 break;
489
490 case 0x01:
491 mipid_reset(s);
492 break;
493
494 case 0x02:
495 s->booster = 0;
496 break;
497 case 0x03:
498 s->booster = 1;
499 break;
500
501 case 0x04:
502 s->p = 0;
503 s->resp[0] = (s->id >> 16) & 0xff;
504 s->resp[1] = (s->id >> 8) & 0xff;
505 s->resp[2] = (s->id >> 0) & 0xff;
506 break;
507
508 case 0x06:
509 case 0x07:
510
511
512 case 0x08:
513 s->p = 0;
514
515 s->resp[0] = 0x01;
516 break;
517
518 case 0x09:
519 s->p = 0;
520 s->resp[0] = s->booster << 7;
521 s->resp[1] = (5 << 4) | (s->partial << 2) |
522 (s->sleep << 1) | s->normal;
523 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
524 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
525 s->resp[3] = s->gamma << 6;
526 break;
527
528 case 0x0a:
529 s->p = 0;
530 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
531 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
532 break;
533 case 0x0b:
534 s->p = 0;
535 s->resp[0] = 0;
536 break;
537 case 0x0c:
538 s->p = 0;
539 s->resp[0] = 5;
540 break;
541 case 0x0d:
542 s->p = 0;
543 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
544 break;
545 case 0x0e:
546 s->p = 0;
547 s->resp[0] = s->te << 7;
548 break;
549 case 0x0f:
550 s->p = 0;
551 s->resp[0] = s->selfcheck;
552 break;
553
554 case 0x10:
555 s->sleep = 1;
556 break;
557 case 0x11:
558 s->sleep = 0;
559 s->selfcheck ^= 1 << 6;
560 break;
561
562 case 0x12:
563 s->partial = 1;
564 s->normal = 0;
565 s->vscr = 0;
566 break;
567 case 0x13:
568 s->partial = 0;
569 s->normal = 1;
570 s->vscr = 0;
571 break;
572
573 case 0x20:
574 s->invert = 0;
575 break;
576 case 0x21:
577 s->invert = 1;
578 break;
579
580 case 0x22:
581 case 0x23:
582 goto bad_cmd;
583
584 case 0x25:
585 if (s->pm < 0) {
586 s->pm = 1;
587 }
588 goto bad_cmd;
589
590 case 0x26:
591 if (!s->pm) {
592 s->gamma = ctz32(s->param[0] & 0xf);
593 if (s->gamma == 32) {
594 s->gamma = -1;
595 }
596 } else if (s->pm < 0) {
597 s->pm = 1;
598 }
599 break;
600
601 case 0x28:
602 s->onoff = 0;
603 break;
604 case 0x29:
605 s->onoff = 1;
606 break;
607
608 case 0x2a:
609 case 0x2b:
610 case 0x2c:
611 case 0x2d:
612 case 0x2e:
613 case 0x30:
614 case 0x33:
615 goto bad_cmd;
616
617 case 0x34:
618 s->te = 0;
619 break;
620 case 0x35:
621 if (!s->pm) {
622 s->te = 1;
623 } else if (s->pm < 0) {
624 s->pm = 1;
625 }
626 break;
627
628 case 0x36:
629 goto bad_cmd;
630
631 case 0x37:
632 s->partial = 0;
633 s->normal = 0;
634 s->vscr = 1;
635 break;
636
637 case 0x38:
638 case 0x39:
639 case 0x3a:
640 goto bad_cmd;
641
642 case 0xb0:
643 case 0xb1:
644 if (s->pm < 0) {
645 s->pm = 2;
646 }
647 break;
648
649 case 0xb4:
650 break;
651
652 case 0xb5:
653 case 0xb6:
654 case 0xb7:
655 case 0xb8:
656 case 0xba:
657 case 0xbb:
658 goto bad_cmd;
659
660 case 0xbd:
661 s->p = 0;
662 s->resp[0] = 0;
663 s->resp[1] = 1;
664 break;
665
666 case 0xc2:
667 if (s->pm < 0) {
668 s->pm = 2;
669 }
670 break;
671
672 case 0xc6:
673 case 0xc7:
674 case 0xd0:
675 case 0xd1:
676 case 0xd4:
677 case 0xd5:
678 goto bad_cmd;
679
680 case 0xda:
681 s->p = 0;
682 s->resp[0] = (s->id >> 16) & 0xff;
683 break;
684 case 0xdb:
685 s->p = 0;
686 s->resp[0] = (s->id >> 8) & 0xff;
687 break;
688 case 0xdc:
689 s->p = 0;
690 s->resp[0] = (s->id >> 0) & 0xff;
691 break;
692
693 default:
694 bad_cmd:
695 qemu_log_mask(LOG_GUEST_ERROR,
696 "%s: unknown command %02x\n", __func__, s->cmd);
697 break;
698 }
699
700 return ret;
701}
702
703static void *mipid_init(void)
704{
705 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
706
707 s->id = 0x838f03;
708 mipid_reset(s);
709
710 return s;
711}
712
713static void n8x0_spi_setup(struct n800_s *s)
714{
715 void *tsc = s->ts.opaque;
716 void *mipid = mipid_init();
717
718 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
719 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
720}
721
722
723
724static void n800_dss_init(struct rfbi_chip_s *chip)
725{
726 uint8_t *fb_blank;
727
728 chip->write(chip->opaque, 0, 0x2a);
729 chip->write(chip->opaque, 1, 0x64);
730 chip->write(chip->opaque, 0, 0x2c);
731 chip->write(chip->opaque, 1, 0x1e);
732 chip->write(chip->opaque, 0, 0x2e);
733 chip->write(chip->opaque, 1, 0xe0);
734 chip->write(chip->opaque, 0, 0x30);
735 chip->write(chip->opaque, 1, 0x01);
736 chip->write(chip->opaque, 0, 0x32);
737 chip->write(chip->opaque, 1, 0x06);
738 chip->write(chip->opaque, 0, 0x68);
739 chip->write(chip->opaque, 1, 1);
740
741 chip->write(chip->opaque, 0, 0x6c);
742 chip->write(chip->opaque, 1, 0x00);
743 chip->write(chip->opaque, 1, 0x00);
744 chip->write(chip->opaque, 1, 0x00);
745 chip->write(chip->opaque, 1, 0x00);
746 chip->write(chip->opaque, 1, 0x1f);
747 chip->write(chip->opaque, 1, 0x03);
748 chip->write(chip->opaque, 1, 0xdf);
749 chip->write(chip->opaque, 1, 0x01);
750 chip->write(chip->opaque, 1, 0x00);
751 chip->write(chip->opaque, 1, 0x00);
752 chip->write(chip->opaque, 1, 0x00);
753 chip->write(chip->opaque, 1, 0x00);
754 chip->write(chip->opaque, 1, 0x1f);
755 chip->write(chip->opaque, 1, 0x03);
756 chip->write(chip->opaque, 1, 0xdf);
757 chip->write(chip->opaque, 1, 0x01);
758 chip->write(chip->opaque, 1, 0x01);
759 chip->write(chip->opaque, 1, 0x01);
760
761 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
762
763 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
764 g_free(fb_blank);
765}
766
767static void n8x0_dss_setup(struct n800_s *s)
768{
769 s->blizzard.opaque = s1d13745_init(NULL);
770 s->blizzard.block = s1d13745_write_block;
771 s->blizzard.write = s1d13745_write;
772 s->blizzard.read = s1d13745_read;
773
774 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
775}
776
777static void n8x0_cbus_setup(struct n800_s *s)
778{
779 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
780 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
781 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
782
783 CBus *cbus = cbus_init(dat_out);
784
785 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
786 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
787 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
788
789 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
790 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
791}
792
793static void n8x0_uart_setup(struct n800_s *s)
794{
795 Chardev *radio = uart_hci_init();
796
797 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
798 csrhci_pins_get(radio)[csrhci_pin_reset]);
799 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
800 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
801
802 omap_uart_attach(s->mpu->uart[BT_UART], radio);
803}
804
805static void n8x0_usb_setup(struct n800_s *s)
806{
807 SysBusDevice *dev;
808 s->usb = qdev_create(NULL, "tusb6010");
809 dev = SYS_BUS_DEVICE(s->usb);
810 qdev_init_nofail(s->usb);
811 sysbus_connect_irq(dev, 0,
812 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
813
814 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
815 sysbus_mmio_get_region(dev, 0));
816 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
817 sysbus_mmio_get_region(dev, 1));
818 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
819 qdev_get_gpio_in(s->usb, 0));
820}
821
822
823
824
825static uint32_t n800_pinout[104] = {
826 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
827 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
828 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
829 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
830 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
831 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
832 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
833 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
834 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
835 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
836 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
837 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
838 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
839 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
840 0x00000000, 0x00000038, 0x00340000, 0x00000000,
841 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
842 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
843 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
844 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
845 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
846 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
847 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
848 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
849 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
850 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
851 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
852};
853
854static void n800_setup_nolo_tags(void *sram_base)
855{
856 int i;
857 uint32_t *p = sram_base + 0x8000;
858 uint32_t *v = sram_base + 0xa000;
859
860 memset(p, 0, 0x3000);
861
862 strcpy((void *) (p + 0), "QEMU N800");
863
864 strcpy((void *) (p + 8), "F5");
865
866 stl_p(p + 10, 0x04f70000);
867 strcpy((void *) (p + 9), "RX-34");
868
869
870 stl_p(p + 12, 0x80);
871
872
873 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
874
875
876 p = sram_base + 0x9000;
877#define ADD_TAG(tag, len) \
878 stw_p((uint16_t *) p + 0, tag); \
879 stw_p((uint16_t *) p + 1, len); p++; \
880 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
881
882
883 ADD_TAG(0x6e01, 414);
884 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
885 stl_p(v++, n800_pinout[i]);
886 }
887
888
889 ADD_TAG(0x6e05, 1);
890 stl_p(v++, 2);
891
892
893 ADD_TAG(0x6e02, 4);
894 stl_p(v++, XLDR_LL_UART);
895
896#if 0
897
898 ADD_TAG(0x6e03, 6);
899 stw_p((uint16_t *) v + 0, 65);
900 stw_p((uint16_t *) v + 1, 66);
901 stw_p((uint16_t *) v + 2, 64);
902 v += 2;
903#endif
904
905
906 ADD_TAG(0x6e0a, 4);
907 stw_p((uint16_t *) v + 0, 111);
908 stw_p((uint16_t *) v + 1, 108);
909 v++;
910
911
912 ADD_TAG(0x6e04, 4);
913 stw_p((uint16_t *) v + 0, 30);
914 stw_p((uint16_t *) v + 1, 24);
915 v++;
916
917#if 0
918
919 ADD_TAG(0x6e06, 2);
920 stw_p((uint16_t *) (v++), 15);
921#endif
922
923
924 ADD_TAG(0x6e07, 4);
925 stl_p(v++, 0x00720000);
926
927
928 ADD_TAG(0x6e0b, 6);
929 stw_p((uint16_t *) v + 0, 94);
930 stw_p((uint16_t *) v + 1, 23);
931 stw_p((uint16_t *) v + 2, 0);
932 v += 2;
933
934
935 ADD_TAG(0x6e0c, 80);
936 strcpy((void *) v, "bat_cover"); v += 3;
937 stw_p((uint16_t *) v + 0, 110);
938 stw_p((uint16_t *) v + 1, 1);
939 v += 2;
940 strcpy((void *) v, "cam_act"); v += 3;
941 stw_p((uint16_t *) v + 0, 95);
942 stw_p((uint16_t *) v + 1, 32);
943 v += 2;
944 strcpy((void *) v, "cam_turn"); v += 3;
945 stw_p((uint16_t *) v + 0, 12);
946 stw_p((uint16_t *) v + 1, 33);
947 v += 2;
948 strcpy((void *) v, "headphone"); v += 3;
949 stw_p((uint16_t *) v + 0, 107);
950 stw_p((uint16_t *) v + 1, 17);
951 v += 2;
952
953
954 ADD_TAG(0x6e0e, 12);
955 stl_p(v++, 0x5c623d01);
956 stl_p(v++, 0x00000201);
957 stl_p(v++, 0x00000000);
958
959
960 ADD_TAG(0x6e0f, 8);
961 stl_p(v++, 0x00610025);
962 stl_p(v++, 0xffff0057);
963
964
965 ADD_TAG(0x6e10, 12);
966 stl_p(v++, 0xffff000f);
967 stl_p(v++, 0xffffffff);
968 stl_p(v++, 0x00000060);
969
970
971 ADD_TAG(0x6e11, 10);
972 stl_p(v++, 0x00000401);
973 stl_p(v++, 0x0002003a);
974 stl_p(v++, 0x00000002);
975
976
977 ADD_TAG(0x6e12, 2);
978 stl_p(v++, 93);
979
980#if 0
981
982 ADD_TAG(6e09, 0);
983
984
985 ADD_TAG(6e12, 0);
986#endif
987
988
989 stl_p(p++, 0x00000000);
990 stl_p(p++, 0x00000000);
991}
992
993
994
995static void n800_gpmc_init(struct n800_s *s)
996{
997 uint32_t config7 =
998 (0xf << 8) |
999 (1 << 6) |
1000 (4 << 0);
1001
1002 cpu_physical_memory_write(0x6800a078,
1003 &config7, sizeof(config7));
1004}
1005
1006
1007static void n8x0_boot_init(void *opaque)
1008{
1009 struct n800_s *s = (struct n800_s *) opaque;
1010 uint32_t buf;
1011
1012
1013#define omap_writel(addr, val) \
1014 buf = (val); \
1015 cpu_physical_memory_write(addr, &buf, sizeof(buf))
1016
1017 omap_writel(0x48008060, 0x41);
1018 omap_writel(0x48008070, 1);
1019 omap_writel(0x48008078, 0);
1020 omap_writel(0x48008090, 0);
1021 omap_writel(0x48008094, 0);
1022 omap_writel(0x48008098, 0);
1023 omap_writel(0x48008140, 2);
1024 omap_writel(0x48008148, 0);
1025 omap_writel(0x48008158, 1);
1026 omap_writel(0x480081c8, 0x15);
1027 omap_writel(0x480081d4, 0x1d4);
1028 omap_writel(0x480081d8, 0);
1029 omap_writel(0x480081dc, 0);
1030 omap_writel(0x480081e0, 0xc);
1031 omap_writel(0x48008200, 0x047e7ff7);
1032 omap_writel(0x48008204, 0x00000004);
1033 omap_writel(0x48008210, 0x047e7ff1);
1034 omap_writel(0x48008214, 0x00000004);
1035 omap_writel(0x4800821c, 0x00000000);
1036 omap_writel(0x48008230, 0);
1037 omap_writel(0x48008234, 0);
1038 omap_writel(0x48008238, 7);
1039 omap_writel(0x4800823c, 0);
1040 omap_writel(0x48008240, 0x04360626);
1041 omap_writel(0x48008244, 0x00000014);
1042 omap_writel(0x48008248, 0);
1043 omap_writel(0x48008300, 0x00000000);
1044 omap_writel(0x48008310, 0x00000000);
1045 omap_writel(0x48008340, 0x00000001);
1046 omap_writel(0x48008400, 0x00000004);
1047 omap_writel(0x48008410, 0x00000004);
1048 omap_writel(0x48008440, 0x00000000);
1049 omap_writel(0x48008500, 0x000000cf);
1050 omap_writel(0x48008530, 0x0000000c);
1051 omap_writel(0x48008540,
1052 (0x78 << 12) | (6 << 8));
1053 omap_writel(0x48008544, 2);
1054
1055
1056 n800_gpmc_init(s);
1057
1058
1059 n800_dss_init(&s->blizzard);
1060
1061
1062 s->mpu->cpu->env.GE = 0x5;
1063
1064
1065 if (s->kbd) {
1066 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1067 }
1068}
1069
1070#define OMAP_TAG_NOKIA_BT 0x4e01
1071#define OMAP_TAG_WLAN_CX3110X 0x4e02
1072#define OMAP_TAG_CBUS 0x4e03
1073#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1074
1075static struct omap_gpiosw_info_s {
1076 const char *name;
1077 int line;
1078 int type;
1079} n800_gpiosw_info[] = {
1080 {
1081 "bat_cover", N800_BAT_COVER_GPIO,
1082 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1083 }, {
1084 "cam_act", N800_CAM_ACT_GPIO,
1085 OMAP_GPIOSW_TYPE_ACTIVITY,
1086 }, {
1087 "cam_turn", N800_CAM_TURN_GPIO,
1088 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1089 }, {
1090 "headphone", N8X0_HEADPHONE_GPIO,
1091 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1092 },
1093 { NULL }
1094}, n810_gpiosw_info[] = {
1095 {
1096 "gps_reset", N810_GPS_RESET_GPIO,
1097 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1098 }, {
1099 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1100 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1101 }, {
1102 "headphone", N8X0_HEADPHONE_GPIO,
1103 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1104 }, {
1105 "kb_lock", N810_KB_LOCK_GPIO,
1106 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1107 }, {
1108 "sleepx_led", N810_SLEEPX_LED_GPIO,
1109 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1110 }, {
1111 "slide", N810_SLIDE_GPIO,
1112 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1113 },
1114 { NULL }
1115};
1116
1117static struct omap_partition_info_s {
1118 uint32_t offset;
1119 uint32_t size;
1120 int mask;
1121 const char *name;
1122} n800_part_info[] = {
1123 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1124 { 0x00020000, 0x00060000, 0x0, "config" },
1125 { 0x00080000, 0x00200000, 0x0, "kernel" },
1126 { 0x00280000, 0x00200000, 0x3, "initfs" },
1127 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1128
1129 { 0, 0, 0, NULL }
1130}, n810_part_info[] = {
1131 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1132 { 0x00020000, 0x00060000, 0x0, "config" },
1133 { 0x00080000, 0x00220000, 0x0, "kernel" },
1134 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1135 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1136
1137 { 0, 0, 0, NULL }
1138};
1139
1140static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1141
1142static int n8x0_atag_setup(void *p, int model)
1143{
1144 uint8_t *b;
1145 uint16_t *w;
1146 uint32_t *l;
1147 struct omap_gpiosw_info_s *gpiosw;
1148 struct omap_partition_info_s *partition;
1149 const char *tag;
1150
1151 w = p;
1152
1153 stw_p(w++, OMAP_TAG_UART);
1154 stw_p(w++, 4);
1155 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0));
1156 w++;
1157
1158#if 0
1159 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE);
1160 stw_p(w++, 4);
1161 stw_p(w++, XLDR_LL_UART + 1);
1162 stw_p(w++, 115200);
1163#endif
1164
1165 stw_p(w++, OMAP_TAG_LCD);
1166 stw_p(w++, 36);
1167 strcpy((void *) w, "QEMU LCD panel");
1168 w += 8;
1169 strcpy((void *) w, "blizzard");
1170 w += 8;
1171 stw_p(w++, N810_BLIZZARD_RESET_GPIO);
1172 stw_p(w++, 24);
1173
1174 stw_p(w++, OMAP_TAG_CBUS);
1175 stw_p(w++, 8);
1176 stw_p(w++, N8X0_CBUS_CLK_GPIO);
1177 stw_p(w++, N8X0_CBUS_DAT_GPIO);
1178 stw_p(w++, N8X0_CBUS_SEL_GPIO);
1179 w++;
1180
1181 stw_p(w++, OMAP_TAG_EM_ASIC_BB5);
1182 stw_p(w++, 4);
1183 stw_p(w++, N8X0_RETU_GPIO);
1184 stw_p(w++, N8X0_TAHVO_GPIO);
1185
1186 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1187 for (; gpiosw->name; gpiosw++) {
1188 stw_p(w++, OMAP_TAG_GPIO_SWITCH);
1189 stw_p(w++, 20);
1190 strcpy((void *) w, gpiosw->name);
1191 w += 6;
1192 stw_p(w++, gpiosw->line);
1193 stw_p(w++, gpiosw->type);
1194 stw_p(w++, 0);
1195 stw_p(w++, 0);
1196 }
1197
1198 stw_p(w++, OMAP_TAG_NOKIA_BT);
1199 stw_p(w++, 12);
1200 b = (void *) w;
1201 stb_p(b++, 0x01);
1202 stb_p(b++, N8X0_BT_WKUP_GPIO);
1203 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO);
1204 stb_p(b++, N8X0_BT_RESET_GPIO);
1205 stb_p(b++, BT_UART + 1);
1206 memcpy(b, &n8x0_bd_addr, 6);
1207 b += 6;
1208 stb_p(b++, 0x02);
1209 w = (void *) b;
1210
1211 stw_p(w++, OMAP_TAG_WLAN_CX3110X);
1212 stw_p(w++, 8);
1213 stw_p(w++, 0x25);
1214 stw_p(w++, N8X0_WLAN_PWR_GPIO);
1215 stw_p(w++, N8X0_WLAN_IRQ_GPIO);
1216 stw_p(w++, -1);
1217
1218 stw_p(w++, OMAP_TAG_MMC);
1219 stw_p(w++, 16);
1220 if (model == 810) {
1221 stw_p(w++, 0x23f);
1222 stw_p(w++, -1);
1223 stw_p(w++, -1);
1224 stw_p(w++, -1);
1225 stw_p(w++, 0x240);
1226 stw_p(w++, 0xc000);
1227 stw_p(w++, 0x0248);
1228 stw_p(w++, 0xc000);
1229 } else {
1230 stw_p(w++, 0xf);
1231 stw_p(w++, -1);
1232 stw_p(w++, -1);
1233 stw_p(w++, -1);
1234 stw_p(w++, 0);
1235 stw_p(w++, 0);
1236 stw_p(w++, 0);
1237 stw_p(w++, 0);
1238 }
1239
1240 stw_p(w++, OMAP_TAG_TEA5761);
1241 stw_p(w++, 4);
1242 stw_p(w++, N8X0_TEA5761_CS_GPIO);
1243 w++;
1244
1245 partition = (model == 810) ? n810_part_info : n800_part_info;
1246 for (; partition->name; partition++) {
1247 stw_p(w++, OMAP_TAG_PARTITION);
1248 stw_p(w++, 28);
1249 strcpy((void *) w, partition->name);
1250 l = (void *) (w + 8);
1251 stl_p(l++, partition->size);
1252 stl_p(l++, partition->offset);
1253 stl_p(l++, partition->mask);
1254 w = (void *) l;
1255 }
1256
1257 stw_p(w++, OMAP_TAG_BOOT_REASON);
1258 stw_p(w++, 12);
1259#if 0
1260 strcpy((void *) w, "por");
1261 strcpy((void *) w, "charger");
1262 strcpy((void *) w, "32wd_to");
1263 strcpy((void *) w, "sw_rst");
1264 strcpy((void *) w, "mbus");
1265 strcpy((void *) w, "unknown");
1266 strcpy((void *) w, "swdg_to");
1267 strcpy((void *) w, "sec_vio");
1268 strcpy((void *) w, "pwr_key");
1269 strcpy((void *) w, "rtc_alarm");
1270#else
1271 strcpy((void *) w, "pwr_key");
1272#endif
1273 w += 6;
1274
1275 tag = (model == 810) ? "RX-44" : "RX-34";
1276 stw_p(w++, OMAP_TAG_VERSION_STR);
1277 stw_p(w++, 24);
1278 strcpy((void *) w, "product");
1279 w += 6;
1280 strcpy((void *) w, tag);
1281 w += 6;
1282
1283 stw_p(w++, OMAP_TAG_VERSION_STR);
1284 stw_p(w++, 24);
1285 strcpy((void *) w, "hw-build");
1286 w += 6;
1287 strcpy((void *) w, "QEMU ");
1288 pstrcat((void *) w, 12, qemu_hw_version());
1289 w += 6;
1290
1291 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1292 stw_p(w++, OMAP_TAG_VERSION_STR);
1293 stw_p(w++, 24);
1294 strcpy((void *) w, "nolo");
1295 w += 6;
1296 strcpy((void *) w, tag);
1297 w += 6;
1298
1299 return (void *) w - p;
1300}
1301
1302static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1303{
1304 return n8x0_atag_setup(p, 800);
1305}
1306
1307static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1308{
1309 return n8x0_atag_setup(p, 810);
1310}
1311
1312static void n8x0_init(MachineState *machine,
1313 struct arm_boot_info *binfo, int model)
1314{
1315 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1316 uint64_t sdram_size = binfo->ram_size;
1317
1318 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
1319 sdram_size);
1320 memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram);
1321
1322 s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type);
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349 n8x0_gpio_setup(s);
1350 n8x0_nand_setup(s);
1351 n8x0_i2c_setup(s);
1352 if (model == 800) {
1353 n800_tsc_kbd_setup(s);
1354 } else if (model == 810) {
1355 n810_tsc_setup(s);
1356 n810_kbd_setup(s);
1357 }
1358 n8x0_spi_setup(s);
1359 n8x0_dss_setup(s);
1360 n8x0_cbus_setup(s);
1361 n8x0_uart_setup(s);
1362 if (machine_usb(machine)) {
1363 n8x0_usb_setup(s);
1364 }
1365
1366 if (machine->kernel_filename) {
1367
1368 arm_load_kernel(s->mpu->cpu, machine, binfo);
1369
1370 qemu_register_reset(n8x0_boot_init, s);
1371 }
1372
1373 if (option_rom[0].name &&
1374 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
1375 uint8_t *nolo_tags = g_new(uint8_t, 0x10000);
1376
1377 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388 load_image_targphys(option_rom[0].name,
1389 OMAP2_Q2_BASE + 0x400000,
1390 sdram_size - 0x400000);
1391
1392 n800_setup_nolo_tags(nolo_tags);
1393 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1394 g_free(nolo_tags);
1395 }
1396}
1397
1398static struct arm_boot_info n800_binfo = {
1399 .loader_start = OMAP2_Q2_BASE,
1400
1401 .ram_size = 0x08000000,
1402 .board_id = 0x4f7,
1403 .atag_board = n800_atag_setup,
1404};
1405
1406static struct arm_boot_info n810_binfo = {
1407 .loader_start = OMAP2_Q2_BASE,
1408
1409 .ram_size = 0x08000000,
1410
1411
1412
1413 .board_id = 0x60c,
1414 .atag_board = n810_atag_setup,
1415};
1416
1417static void n800_init(MachineState *machine)
1418{
1419 n8x0_init(machine, &n800_binfo, 800);
1420}
1421
1422static void n810_init(MachineState *machine)
1423{
1424 n8x0_init(machine, &n810_binfo, 810);
1425}
1426
1427static void n800_class_init(ObjectClass *oc, void *data)
1428{
1429 MachineClass *mc = MACHINE_CLASS(oc);
1430
1431 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1432 mc->init = n800_init;
1433 mc->default_boot_order = "";
1434 mc->ignore_memory_transaction_failures = true;
1435 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
1436}
1437
1438static const TypeInfo n800_type = {
1439 .name = MACHINE_TYPE_NAME("n800"),
1440 .parent = TYPE_MACHINE,
1441 .class_init = n800_class_init,
1442};
1443
1444static void n810_class_init(ObjectClass *oc, void *data)
1445{
1446 MachineClass *mc = MACHINE_CLASS(oc);
1447
1448 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1449 mc->init = n810_init;
1450 mc->default_boot_order = "";
1451 mc->ignore_memory_transaction_failures = true;
1452 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
1453}
1454
1455static const TypeInfo n810_type = {
1456 .name = MACHINE_TYPE_NAME("n810"),
1457 .parent = TYPE_MACHINE,
1458 .class_init = n810_class_init,
1459};
1460
1461static void nseries_machine_init(void)
1462{
1463 type_register_static(&n800_type);
1464 type_register_static(&n810_type);
1465}
1466
1467type_init(nseries_machine_init)
1468