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31#include "qemu/osdep.h"
32#include "qemu-common.h"
33#include "qemu/units.h"
34#include "qemu/option.h"
35#include "qapi/error.h"
36#include "hw/sysbus.h"
37#include "hw/boards.h"
38#include "hw/arm/boot.h"
39#include "hw/arm/primecell.h"
40#include "hw/arm/virt.h"
41#include "hw/block/flash.h"
42#include "hw/vfio/vfio-calxeda-xgmac.h"
43#include "hw/vfio/vfio-amd-xgbe.h"
44#include "hw/display/ramfb.h"
45#include "net/net.h"
46#include "sysemu/device_tree.h"
47#include "sysemu/numa.h"
48#include "sysemu/runstate.h"
49#include "sysemu/sysemu.h"
50#include "sysemu/kvm.h"
51#include "hw/loader.h"
52#include "exec/address-spaces.h"
53#include "qemu/bitops.h"
54#include "qemu/error-report.h"
55#include "qemu/module.h"
56#include "hw/pci-host/gpex.h"
57#include "hw/arm/sysbus-fdt.h"
58#include "hw/platform-bus.h"
59#include "hw/qdev-properties.h"
60#include "hw/arm/fdt.h"
61#include "hw/intc/arm_gic.h"
62#include "hw/intc/arm_gicv3_common.h"
63#include "hw/irq.h"
64#include "kvm_arm.h"
65#include "hw/firmware/smbios.h"
66#include "qapi/visitor.h"
67#include "standard-headers/linux/input.h"
68#include "hw/arm/smmuv3.h"
69#include "hw/acpi/acpi.h"
70#include "target/arm/internals.h"
71#include "hw/mem/pc-dimm.h"
72#include "hw/mem/nvdimm.h"
73#include "hw/acpi/generic_event_device.h"
74
75#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
76 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
77 void *data) \
78 { \
79 MachineClass *mc = MACHINE_CLASS(oc); \
80 virt_machine_##major##_##minor##_options(mc); \
81 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
82 if (latest) { \
83 mc->alias = "virt"; \
84 } \
85 } \
86 static const TypeInfo machvirt_##major##_##minor##_info = { \
87 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
88 .parent = TYPE_VIRT_MACHINE, \
89 .class_init = virt_##major##_##minor##_class_init, \
90 }; \
91 static void machvirt_machine_##major##_##minor##_init(void) \
92 { \
93 type_register_static(&machvirt_##major##_##minor##_info); \
94 } \
95 type_init(machvirt_machine_##major##_##minor##_init);
96
97#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
98 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
99#define DEFINE_VIRT_MACHINE(major, minor) \
100 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
101
102
103
104#define NUM_IRQS 256
105
106#define PLATFORM_BUS_NUM_IRQS 64
107
108
109#define LEGACY_RAMLIMIT_GB 255
110#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
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123
124static const MemMapEntry base_memmap[] = {
125
126 [VIRT_FLASH] = { 0, 0x08000000 },
127 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
128
129 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
130 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
131 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
132 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
133 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
134
135 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
136
137 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
138 [VIRT_UART] = { 0x09000000, 0x00001000 },
139 [VIRT_RTC] = { 0x09010000, 0x00001000 },
140 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
141 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
142 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
143 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
144 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
145 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
146 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
147
148 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
149 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
150 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
151 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
152 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
153
154 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
155};
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166
167static MemMapEntry extended_memmap[] = {
168
169 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
170 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
171
172 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
173};
174
175static const int a15irqmap[] = {
176 [VIRT_UART] = 1,
177 [VIRT_RTC] = 2,
178 [VIRT_PCIE] = 3,
179 [VIRT_GPIO] = 7,
180 [VIRT_SECURE_UART] = 8,
181 [VIRT_ACPI_GED] = 9,
182 [VIRT_MMIO] = 16,
183 [VIRT_GIC_V2M] = 48,
184 [VIRT_SMMU] = 74,
185 [VIRT_PLATFORM_BUS] = 112,
186};
187
188static const char *valid_cpus[] = {
189 ARM_CPU_TYPE_NAME("cortex-a7"),
190 ARM_CPU_TYPE_NAME("cortex-a15"),
191 ARM_CPU_TYPE_NAME("cortex-a53"),
192 ARM_CPU_TYPE_NAME("cortex-a57"),
193 ARM_CPU_TYPE_NAME("cortex-a72"),
194 ARM_CPU_TYPE_NAME("host"),
195 ARM_CPU_TYPE_NAME("max"),
196};
197
198static bool cpu_type_valid(const char *cpu)
199{
200 int i;
201
202 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
203 if (strcmp(cpu, valid_cpus[i]) == 0) {
204 return true;
205 }
206 }
207 return false;
208}
209
210static void create_fdt(VirtMachineState *vms)
211{
212 MachineState *ms = MACHINE(vms);
213 int nb_numa_nodes = ms->numa_state->num_nodes;
214 void *fdt = create_device_tree(&vms->fdt_size);
215
216 if (!fdt) {
217 error_report("create_device_tree() failed");
218 exit(1);
219 }
220
221 vms->fdt = fdt;
222
223
224 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
225 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
226 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
227
228
229 qemu_fdt_add_subnode(fdt, "/chosen");
230
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235
236 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
237 qemu_fdt_add_subnode(fdt, "/apb-pclk");
238 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
239 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
240 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
241 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
242 "clk24mhz");
243 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
244
245 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
246 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
247 uint32_t *matrix = g_malloc0(size);
248 int idx, i, j;
249
250 for (i = 0; i < nb_numa_nodes; i++) {
251 for (j = 0; j < nb_numa_nodes; j++) {
252 idx = (i * nb_numa_nodes + j) * 3;
253 matrix[idx + 0] = cpu_to_be32(i);
254 matrix[idx + 1] = cpu_to_be32(j);
255 matrix[idx + 2] =
256 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
257 }
258 }
259
260 qemu_fdt_add_subnode(fdt, "/distance-map");
261 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
262 "numa-distance-map-v1");
263 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
264 matrix, size);
265 g_free(matrix);
266 }
267}
268
269static void fdt_add_timer_nodes(const VirtMachineState *vms)
270{
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289 ARMCPU *armcpu;
290 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
291 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
292
293 if (vmc->claim_edge_triggered_timers) {
294 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
295 }
296
297 if (vms->gic_version == 2) {
298 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
299 GIC_FDT_IRQ_PPI_CPU_WIDTH,
300 (1 << vms->smp_cpus) - 1);
301 }
302
303 qemu_fdt_add_subnode(vms->fdt, "/timer");
304
305 armcpu = ARM_CPU(qemu_get_cpu(0));
306 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
307 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
308 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
309 compat, sizeof(compat));
310 } else {
311 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
312 "arm,armv7-timer");
313 }
314 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
315 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
316 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
317 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
318 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
319 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
320}
321
322static void fdt_add_cpu_nodes(const VirtMachineState *vms)
323{
324 int cpu;
325 int addr_cells = 1;
326 const MachineState *ms = MACHINE(vms);
327
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339
340
341 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
342 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
343
344 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
345 addr_cells = 2;
346 break;
347 }
348 }
349
350 qemu_fdt_add_subnode(vms->fdt, "/cpus");
351 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
352 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
353
354 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
355 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
356 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
357 CPUState *cs = CPU(armcpu);
358
359 qemu_fdt_add_subnode(vms->fdt, nodename);
360 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
361 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
362 armcpu->dtb_compatible);
363
364 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
365 && vms->smp_cpus > 1) {
366 qemu_fdt_setprop_string(vms->fdt, nodename,
367 "enable-method", "psci");
368 }
369
370 if (addr_cells == 2) {
371 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
372 armcpu->mp_affinity);
373 } else {
374 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
375 armcpu->mp_affinity);
376 }
377
378 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
379 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
380 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
381 }
382
383 g_free(nodename);
384 }
385}
386
387static void fdt_add_its_gic_node(VirtMachineState *vms)
388{
389 char *nodename;
390
391 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
392 nodename = g_strdup_printf("/intc/its@%" PRIx64,
393 vms->memmap[VIRT_GIC_ITS].base);
394 qemu_fdt_add_subnode(vms->fdt, nodename);
395 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
396 "arm,gic-v3-its");
397 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
398 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
399 2, vms->memmap[VIRT_GIC_ITS].base,
400 2, vms->memmap[VIRT_GIC_ITS].size);
401 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
402 g_free(nodename);
403}
404
405static void fdt_add_v2m_gic_node(VirtMachineState *vms)
406{
407 char *nodename;
408
409 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
410 vms->memmap[VIRT_GIC_V2M].base);
411 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
412 qemu_fdt_add_subnode(vms->fdt, nodename);
413 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
414 "arm,gic-v2m-frame");
415 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
416 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
417 2, vms->memmap[VIRT_GIC_V2M].base,
418 2, vms->memmap[VIRT_GIC_V2M].size);
419 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
420 g_free(nodename);
421}
422
423static void fdt_add_gic_node(VirtMachineState *vms)
424{
425 char *nodename;
426
427 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
428 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
429
430 nodename = g_strdup_printf("/intc@%" PRIx64,
431 vms->memmap[VIRT_GIC_DIST].base);
432 qemu_fdt_add_subnode(vms->fdt, nodename);
433 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
434 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
435 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
436 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
437 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
438 if (vms->gic_version == 3) {
439 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
440
441 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
442 "arm,gic-v3");
443
444 qemu_fdt_setprop_cell(vms->fdt, nodename,
445 "#redistributor-regions", nb_redist_regions);
446
447 if (nb_redist_regions == 1) {
448 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
449 2, vms->memmap[VIRT_GIC_DIST].base,
450 2, vms->memmap[VIRT_GIC_DIST].size,
451 2, vms->memmap[VIRT_GIC_REDIST].base,
452 2, vms->memmap[VIRT_GIC_REDIST].size);
453 } else {
454 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
455 2, vms->memmap[VIRT_GIC_DIST].base,
456 2, vms->memmap[VIRT_GIC_DIST].size,
457 2, vms->memmap[VIRT_GIC_REDIST].base,
458 2, vms->memmap[VIRT_GIC_REDIST].size,
459 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
460 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
461 }
462
463 if (vms->virt) {
464 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
465 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
466 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
467 }
468 } else {
469
470 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
471 "arm,cortex-a15-gic");
472 if (!vms->virt) {
473 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
474 2, vms->memmap[VIRT_GIC_DIST].base,
475 2, vms->memmap[VIRT_GIC_DIST].size,
476 2, vms->memmap[VIRT_GIC_CPU].base,
477 2, vms->memmap[VIRT_GIC_CPU].size);
478 } else {
479 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
480 2, vms->memmap[VIRT_GIC_DIST].base,
481 2, vms->memmap[VIRT_GIC_DIST].size,
482 2, vms->memmap[VIRT_GIC_CPU].base,
483 2, vms->memmap[VIRT_GIC_CPU].size,
484 2, vms->memmap[VIRT_GIC_HYP].base,
485 2, vms->memmap[VIRT_GIC_HYP].size,
486 2, vms->memmap[VIRT_GIC_VCPU].base,
487 2, vms->memmap[VIRT_GIC_VCPU].size);
488 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
489 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
490 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
491 }
492 }
493
494 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
495 g_free(nodename);
496}
497
498static void fdt_add_pmu_nodes(const VirtMachineState *vms)
499{
500 CPUState *cpu;
501 ARMCPU *armcpu;
502 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
503
504 CPU_FOREACH(cpu) {
505 armcpu = ARM_CPU(cpu);
506 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
507 return;
508 }
509 if (kvm_enabled()) {
510 if (kvm_irqchip_in_kernel()) {
511 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
512 }
513 kvm_arm_pmu_init(cpu);
514 }
515 }
516
517 if (vms->gic_version == 2) {
518 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
519 GIC_FDT_IRQ_PPI_CPU_WIDTH,
520 (1 << vms->smp_cpus) - 1);
521 }
522
523 armcpu = ARM_CPU(qemu_get_cpu(0));
524 qemu_fdt_add_subnode(vms->fdt, "/pmu");
525 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
526 const char compat[] = "arm,armv8-pmuv3";
527 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
528 compat, sizeof(compat));
529 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
530 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
531 }
532}
533
534static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu_irq *pic)
535{
536 DeviceState *dev;
537 MachineState *ms = MACHINE(vms);
538 int irq = vms->irqmap[VIRT_ACPI_GED];
539 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
540
541 if (ms->ram_slots) {
542 event |= ACPI_GED_MEM_HOTPLUG_EVT;
543 }
544
545 dev = qdev_create(NULL, TYPE_ACPI_GED);
546 qdev_prop_set_uint32(dev, "ged-event", event);
547
548 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
549 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
550 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]);
551
552 qdev_init_nofail(dev);
553
554 return dev;
555}
556
557static void create_its(VirtMachineState *vms, DeviceState *gicdev)
558{
559 const char *itsclass = its_class_name();
560 DeviceState *dev;
561
562 if (!itsclass) {
563
564 return;
565 }
566
567 dev = qdev_create(NULL, itsclass);
568
569 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
570 &error_abort);
571 qdev_init_nofail(dev);
572 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
573
574 fdt_add_its_gic_node(vms);
575}
576
577static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
578{
579 int i;
580 int irq = vms->irqmap[VIRT_GIC_V2M];
581 DeviceState *dev;
582
583 dev = qdev_create(NULL, "arm-gicv2m");
584 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
585 qdev_prop_set_uint32(dev, "base-spi", irq);
586 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
587 qdev_init_nofail(dev);
588
589 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
590 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
591 }
592
593 fdt_add_v2m_gic_node(vms);
594}
595
596static void create_gic(VirtMachineState *vms, qemu_irq *pic)
597{
598 MachineState *ms = MACHINE(vms);
599
600 DeviceState *gicdev;
601 SysBusDevice *gicbusdev;
602 const char *gictype;
603 int type = vms->gic_version, i;
604 unsigned int smp_cpus = ms->smp.cpus;
605 uint32_t nb_redist_regions = 0;
606
607 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
608
609 gicdev = qdev_create(NULL, gictype);
610 qdev_prop_set_uint32(gicdev, "revision", type);
611 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
612
613
614
615 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
616 if (!kvm_irqchip_in_kernel()) {
617 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
618 }
619
620 if (type == 3) {
621 uint32_t redist0_capacity =
622 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
623 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
624
625 nb_redist_regions = virt_gicv3_redist_region_count(vms);
626
627 qdev_prop_set_uint32(gicdev, "len-redist-region-count",
628 nb_redist_regions);
629 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
630
631 if (nb_redist_regions == 2) {
632 uint32_t redist1_capacity =
633 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
634
635 qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
636 MIN(smp_cpus - redist0_count, redist1_capacity));
637 }
638 } else {
639 if (!kvm_irqchip_in_kernel()) {
640 qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
641 vms->virt);
642 }
643 }
644 qdev_init_nofail(gicdev);
645 gicbusdev = SYS_BUS_DEVICE(gicdev);
646 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
647 if (type == 3) {
648 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
649 if (nb_redist_regions == 2) {
650 sysbus_mmio_map(gicbusdev, 2,
651 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
652 }
653 } else {
654 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
655 if (vms->virt) {
656 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
657 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
658 }
659 }
660
661
662
663
664
665 for (i = 0; i < smp_cpus; i++) {
666 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
667 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
668 int irq;
669
670
671
672 const int timer_irq[] = {
673 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
674 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
675 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
676 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
677 };
678
679 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
680 qdev_connect_gpio_out(cpudev, irq,
681 qdev_get_gpio_in(gicdev,
682 ppibase + timer_irq[irq]));
683 }
684
685 if (type == 3) {
686 qemu_irq irq = qdev_get_gpio_in(gicdev,
687 ppibase + ARCH_GIC_MAINT_IRQ);
688 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
689 0, irq);
690 } else if (vms->virt) {
691 qemu_irq irq = qdev_get_gpio_in(gicdev,
692 ppibase + ARCH_GIC_MAINT_IRQ);
693 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
694 }
695
696 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
697 qdev_get_gpio_in(gicdev, ppibase
698 + VIRTUAL_PMU_IRQ));
699
700 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
701 sysbus_connect_irq(gicbusdev, i + smp_cpus,
702 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
703 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
704 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
705 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
706 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
707 }
708
709 for (i = 0; i < NUM_IRQS; i++) {
710 pic[i] = qdev_get_gpio_in(gicdev, i);
711 }
712
713 fdt_add_gic_node(vms);
714
715 if (type == 3 && vms->its) {
716 create_its(vms, gicdev);
717 } else if (type == 2) {
718 create_v2m(vms, pic);
719 }
720}
721
722static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
723 MemoryRegion *mem, Chardev *chr)
724{
725 char *nodename;
726 hwaddr base = vms->memmap[uart].base;
727 hwaddr size = vms->memmap[uart].size;
728 int irq = vms->irqmap[uart];
729 const char compat[] = "arm,pl011\0arm,primecell";
730 const char clocknames[] = "uartclk\0apb_pclk";
731 DeviceState *dev = qdev_create(NULL, "pl011");
732 SysBusDevice *s = SYS_BUS_DEVICE(dev);
733
734 qdev_prop_set_chr(dev, "chardev", chr);
735 qdev_init_nofail(dev);
736 memory_region_add_subregion(mem, base,
737 sysbus_mmio_get_region(s, 0));
738 sysbus_connect_irq(s, 0, pic[irq]);
739
740 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
741 qemu_fdt_add_subnode(vms->fdt, nodename);
742
743 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
744 compat, sizeof(compat));
745 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
746 2, base, 2, size);
747 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
748 GIC_FDT_IRQ_TYPE_SPI, irq,
749 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
750 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
751 vms->clock_phandle, vms->clock_phandle);
752 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
753 clocknames, sizeof(clocknames));
754
755 if (uart == VIRT_UART) {
756 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
757 } else {
758
759 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
760 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
761
762 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
763 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
764 nodename);
765 }
766
767 g_free(nodename);
768}
769
770static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
771{
772 char *nodename;
773 hwaddr base = vms->memmap[VIRT_RTC].base;
774 hwaddr size = vms->memmap[VIRT_RTC].size;
775 int irq = vms->irqmap[VIRT_RTC];
776 const char compat[] = "arm,pl031\0arm,primecell";
777
778 sysbus_create_simple("pl031", base, pic[irq]);
779
780 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
781 qemu_fdt_add_subnode(vms->fdt, nodename);
782 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
783 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
784 2, base, 2, size);
785 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
786 GIC_FDT_IRQ_TYPE_SPI, irq,
787 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
788 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
789 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
790 g_free(nodename);
791}
792
793static DeviceState *gpio_key_dev;
794static void virt_powerdown_req(Notifier *n, void *opaque)
795{
796 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
797
798 if (s->acpi_dev) {
799 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
800 } else {
801
802 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
803 }
804}
805
806static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
807{
808 char *nodename;
809 DeviceState *pl061_dev;
810 hwaddr base = vms->memmap[VIRT_GPIO].base;
811 hwaddr size = vms->memmap[VIRT_GPIO].size;
812 int irq = vms->irqmap[VIRT_GPIO];
813 const char compat[] = "arm,pl061\0arm,primecell";
814
815 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
816
817 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
818 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
819 qemu_fdt_add_subnode(vms->fdt, nodename);
820 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
821 2, base, 2, size);
822 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
823 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
824 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
825 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
826 GIC_FDT_IRQ_TYPE_SPI, irq,
827 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
828 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
829 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
830 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
831
832 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
833 qdev_get_gpio_in(pl061_dev, 3));
834 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
835 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
836 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
837 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
838
839 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
840 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
841 "label", "GPIO Key Poweroff");
842 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
843 KEY_POWER);
844 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
845 "gpios", phandle, 3, 0);
846 g_free(nodename);
847}
848
849static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
850{
851 int i;
852 hwaddr size = vms->memmap[VIRT_MMIO].size;
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
882 int irq = vms->irqmap[VIRT_MMIO] + i;
883 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
884
885 sysbus_create_simple("virtio-mmio", base, pic[irq]);
886 }
887
888
889
890
891
892
893
894
895 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
896 char *nodename;
897 int irq = vms->irqmap[VIRT_MMIO] + i;
898 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
899
900 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
901 qemu_fdt_add_subnode(vms->fdt, nodename);
902 qemu_fdt_setprop_string(vms->fdt, nodename,
903 "compatible", "virtio,mmio");
904 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
905 2, base, 2, size);
906 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
907 GIC_FDT_IRQ_TYPE_SPI, irq,
908 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
909 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
910 g_free(nodename);
911 }
912}
913
914#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
915
916static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
917 const char *name,
918 const char *alias_prop_name)
919{
920
921
922
923
924 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
925
926 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
927 qdev_prop_set_uint8(dev, "width", 4);
928 qdev_prop_set_uint8(dev, "device-width", 2);
929 qdev_prop_set_bit(dev, "big-endian", false);
930 qdev_prop_set_uint16(dev, "id0", 0x89);
931 qdev_prop_set_uint16(dev, "id1", 0x18);
932 qdev_prop_set_uint16(dev, "id2", 0x00);
933 qdev_prop_set_uint16(dev, "id3", 0x00);
934 qdev_prop_set_string(dev, "name", name);
935 object_property_add_child(OBJECT(vms), name, OBJECT(dev),
936 &error_abort);
937 object_property_add_alias(OBJECT(vms), alias_prop_name,
938 OBJECT(dev), "drive", &error_abort);
939 return PFLASH_CFI01(dev);
940}
941
942static void virt_flash_create(VirtMachineState *vms)
943{
944 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
945 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
946}
947
948static void virt_flash_map1(PFlashCFI01 *flash,
949 hwaddr base, hwaddr size,
950 MemoryRegion *sysmem)
951{
952 DeviceState *dev = DEVICE(flash);
953
954 assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
955 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
956 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
957 qdev_init_nofail(dev);
958
959 memory_region_add_subregion(sysmem, base,
960 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
961 0));
962}
963
964static void virt_flash_map(VirtMachineState *vms,
965 MemoryRegion *sysmem,
966 MemoryRegion *secure_sysmem)
967{
968
969
970
971
972
973
974
975
976 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
977 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
978
979 virt_flash_map1(vms->flash[0], flashbase, flashsize,
980 secure_sysmem);
981 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
982 sysmem);
983}
984
985static void virt_flash_fdt(VirtMachineState *vms,
986 MemoryRegion *sysmem,
987 MemoryRegion *secure_sysmem)
988{
989 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
990 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
991 char *nodename;
992
993 if (sysmem == secure_sysmem) {
994
995 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
996 qemu_fdt_add_subnode(vms->fdt, nodename);
997 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
998 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
999 2, flashbase, 2, flashsize,
1000 2, flashbase + flashsize, 2, flashsize);
1001 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1002 g_free(nodename);
1003 } else {
1004
1005
1006
1007
1008 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1009 qemu_fdt_add_subnode(vms->fdt, nodename);
1010 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1011 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1012 2, flashbase, 2, flashsize);
1013 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1014 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1015 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1016 g_free(nodename);
1017
1018 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1019 qemu_fdt_add_subnode(vms->fdt, nodename);
1020 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1021 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1022 2, flashbase + flashsize, 2, flashsize);
1023 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1024 g_free(nodename);
1025 }
1026}
1027
1028static bool virt_firmware_init(VirtMachineState *vms,
1029 MemoryRegion *sysmem,
1030 MemoryRegion *secure_sysmem)
1031{
1032 int i;
1033 BlockBackend *pflash_blk0;
1034
1035
1036 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1037 pflash_cfi01_legacy_drive(vms->flash[i],
1038 drive_get(IF_PFLASH, 0, i));
1039 }
1040
1041 virt_flash_map(vms, sysmem, secure_sysmem);
1042
1043 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1044
1045 if (bios_name) {
1046 char *fname;
1047 MemoryRegion *mr;
1048 int image_size;
1049
1050 if (pflash_blk0) {
1051 error_report("The contents of the first flash device may be "
1052 "specified with -bios or with -drive if=pflash... "
1053 "but you cannot use both options at once");
1054 exit(1);
1055 }
1056
1057
1058
1059 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1060 if (!fname) {
1061 error_report("Could not find ROM image '%s'", bios_name);
1062 exit(1);
1063 }
1064 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1065 image_size = load_image_mr(fname, mr);
1066 g_free(fname);
1067 if (image_size < 0) {
1068 error_report("Could not load ROM image '%s'", bios_name);
1069 exit(1);
1070 }
1071 }
1072
1073 return pflash_blk0 || bios_name;
1074}
1075
1076static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1077{
1078 MachineState *ms = MACHINE(vms);
1079 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1080 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1081 FWCfgState *fw_cfg;
1082 char *nodename;
1083
1084 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1085 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1086
1087 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1088 qemu_fdt_add_subnode(vms->fdt, nodename);
1089 qemu_fdt_setprop_string(vms->fdt, nodename,
1090 "compatible", "qemu,fw-cfg-mmio");
1091 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1092 2, base, 2, size);
1093 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1094 g_free(nodename);
1095 return fw_cfg;
1096}
1097
1098static void create_pcie_irq_map(const VirtMachineState *vms,
1099 uint32_t gic_phandle,
1100 int first_irq, const char *nodename)
1101{
1102 int devfn, pin;
1103 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1104 uint32_t *irq_map = full_irq_map;
1105
1106 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1107 for (pin = 0; pin < 4; pin++) {
1108 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1109 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1110 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1111 int i;
1112
1113 uint32_t map[] = {
1114 devfn << 8, 0, 0,
1115 pin + 1,
1116 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1117
1118
1119 for (i = 0; i < 10; i++) {
1120 irq_map[i] = cpu_to_be32(map[i]);
1121 }
1122 irq_map += 10;
1123 }
1124 }
1125
1126 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1127 full_irq_map, sizeof(full_irq_map));
1128
1129 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1130 0x1800, 0, 0,
1131 0x7 );
1132}
1133
1134static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1135 PCIBus *bus)
1136{
1137 char *node;
1138 const char compat[] = "arm,smmu-v3";
1139 int irq = vms->irqmap[VIRT_SMMU];
1140 int i;
1141 hwaddr base = vms->memmap[VIRT_SMMU].base;
1142 hwaddr size = vms->memmap[VIRT_SMMU].size;
1143 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1144 DeviceState *dev;
1145
1146 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1147 return;
1148 }
1149
1150 dev = qdev_create(NULL, "arm-smmuv3");
1151
1152 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1153 &error_abort);
1154 qdev_init_nofail(dev);
1155 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1156 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1157 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1158 }
1159
1160 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1161 qemu_fdt_add_subnode(vms->fdt, node);
1162 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1163 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1164
1165 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1166 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1167 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1168 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1169 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1170
1171 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1172 sizeof(irq_names));
1173
1174 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1175 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1176 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1177
1178 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1179
1180 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1181 g_free(node);
1182}
1183
1184static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1185{
1186 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1187 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1188 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1189 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1190 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1191 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1192 hwaddr base_ecam, size_ecam;
1193 hwaddr base = base_mmio;
1194 int nr_pcie_buses;
1195 int irq = vms->irqmap[VIRT_PCIE];
1196 MemoryRegion *mmio_alias;
1197 MemoryRegion *mmio_reg;
1198 MemoryRegion *ecam_alias;
1199 MemoryRegion *ecam_reg;
1200 DeviceState *dev;
1201 char *nodename;
1202 int i, ecam_id;
1203 PCIHostState *pci;
1204
1205 dev = qdev_create(NULL, TYPE_GPEX_HOST);
1206 qdev_init_nofail(dev);
1207
1208 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1209 base_ecam = vms->memmap[ecam_id].base;
1210 size_ecam = vms->memmap[ecam_id].size;
1211 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1212
1213 ecam_alias = g_new0(MemoryRegion, 1);
1214 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1215 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1216 ecam_reg, 0, size_ecam);
1217 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1218
1219
1220
1221
1222
1223
1224 mmio_alias = g_new0(MemoryRegion, 1);
1225 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1226 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1227 mmio_reg, base_mmio, size_mmio);
1228 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1229
1230 if (vms->highmem) {
1231
1232 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1233
1234 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1235 mmio_reg, base_mmio_high, size_mmio_high);
1236 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1237 high_mmio_alias);
1238 }
1239
1240
1241 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1242
1243 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1244 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1245 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1246 }
1247
1248 pci = PCI_HOST_BRIDGE(dev);
1249 if (pci->bus) {
1250 for (i = 0; i < nb_nics; i++) {
1251 NICInfo *nd = &nd_table[i];
1252
1253 if (!nd->model) {
1254 nd->model = g_strdup("virtio");
1255 }
1256
1257 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1258 }
1259 }
1260
1261 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1262 qemu_fdt_add_subnode(vms->fdt, nodename);
1263 qemu_fdt_setprop_string(vms->fdt, nodename,
1264 "compatible", "pci-host-ecam-generic");
1265 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1266 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1267 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1268 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1269 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1270 nr_pcie_buses - 1);
1271 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1272
1273 if (vms->msi_phandle) {
1274 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1275 vms->msi_phandle);
1276 }
1277
1278 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1279 2, base_ecam, 2, size_ecam);
1280
1281 if (vms->highmem) {
1282 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1283 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1284 2, base_pio, 2, size_pio,
1285 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1286 2, base_mmio, 2, size_mmio,
1287 1, FDT_PCI_RANGE_MMIO_64BIT,
1288 2, base_mmio_high,
1289 2, base_mmio_high, 2, size_mmio_high);
1290 } else {
1291 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1292 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1293 2, base_pio, 2, size_pio,
1294 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1295 2, base_mmio, 2, size_mmio);
1296 }
1297
1298 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1299 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1300
1301 if (vms->iommu) {
1302 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1303
1304 create_smmu(vms, pic, pci->bus);
1305
1306 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1307 0x0, vms->iommu_phandle, 0x0, 0x10000);
1308 }
1309
1310 g_free(nodename);
1311}
1312
1313static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1314{
1315 DeviceState *dev;
1316 SysBusDevice *s;
1317 int i;
1318 MemoryRegion *sysmem = get_system_memory();
1319
1320 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1321 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1322 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1323 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1324 qdev_init_nofail(dev);
1325 vms->platform_bus_dev = dev;
1326
1327 s = SYS_BUS_DEVICE(dev);
1328 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1329 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1330 sysbus_connect_irq(s, i, pic[irqn]);
1331 }
1332
1333 memory_region_add_subregion(sysmem,
1334 vms->memmap[VIRT_PLATFORM_BUS].base,
1335 sysbus_mmio_get_region(s, 0));
1336}
1337
1338static void create_secure_ram(VirtMachineState *vms,
1339 MemoryRegion *secure_sysmem)
1340{
1341 MemoryRegion *secram = g_new(MemoryRegion, 1);
1342 char *nodename;
1343 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1344 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1345
1346 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1347 &error_fatal);
1348 memory_region_add_subregion(secure_sysmem, base, secram);
1349
1350 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1351 qemu_fdt_add_subnode(vms->fdt, nodename);
1352 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1353 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1354 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1355 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1356
1357 g_free(nodename);
1358}
1359
1360static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1361{
1362 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1363 bootinfo);
1364
1365 *fdt_size = board->fdt_size;
1366 return board->fdt;
1367}
1368
1369static void virt_build_smbios(VirtMachineState *vms)
1370{
1371 MachineClass *mc = MACHINE_GET_CLASS(vms);
1372 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1373 uint8_t *smbios_tables, *smbios_anchor;
1374 size_t smbios_tables_len, smbios_anchor_len;
1375 const char *product = "QEMU Virtual Machine";
1376
1377 if (kvm_enabled()) {
1378 product = "KVM Virtual Machine";
1379 }
1380
1381 smbios_set_defaults("QEMU", product,
1382 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1383 true, SMBIOS_ENTRY_POINT_30);
1384
1385 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1386 &smbios_anchor, &smbios_anchor_len);
1387
1388 if (smbios_anchor) {
1389 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1390 smbios_tables, smbios_tables_len);
1391 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1392 smbios_anchor, smbios_anchor_len);
1393 }
1394}
1395
1396static
1397void virt_machine_done(Notifier *notifier, void *data)
1398{
1399 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1400 machine_done);
1401 MachineState *ms = MACHINE(vms);
1402 ARMCPU *cpu = ARM_CPU(first_cpu);
1403 struct arm_boot_info *info = &vms->bootinfo;
1404 AddressSpace *as = arm_boot_address_space(cpu, info);
1405
1406
1407
1408
1409
1410
1411
1412
1413 if (info->dtb_filename == NULL) {
1414 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1415 vms->memmap[VIRT_PLATFORM_BUS].base,
1416 vms->memmap[VIRT_PLATFORM_BUS].size,
1417 vms->irqmap[VIRT_PLATFORM_BUS]);
1418 }
1419 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1420 exit(1);
1421 }
1422
1423 virt_acpi_setup(vms);
1424 virt_build_smbios(vms);
1425}
1426
1427static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1428{
1429 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1430 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1431
1432 if (!vmc->disallow_affinity_adjustment) {
1433
1434
1435
1436
1437
1438
1439
1440
1441 if (vms->gic_version == 3) {
1442 clustersz = GICV3_TARGETLIST_BITS;
1443 } else {
1444 clustersz = GIC_TARGETLIST_BITS;
1445 }
1446 }
1447 return arm_cpu_mp_affinity(idx, clustersz);
1448}
1449
1450static void virt_set_memmap(VirtMachineState *vms)
1451{
1452 MachineState *ms = MACHINE(vms);
1453 hwaddr base, device_memory_base, device_memory_size;
1454 int i;
1455
1456 vms->memmap = extended_memmap;
1457
1458 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1459 vms->memmap[i] = base_memmap[i];
1460 }
1461
1462 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1463 error_report("unsupported number of memory slots: %"PRIu64,
1464 ms->ram_slots);
1465 exit(EXIT_FAILURE);
1466 }
1467
1468
1469
1470
1471
1472
1473
1474
1475 device_memory_base =
1476 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1477 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1478
1479
1480 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1481 if (base < device_memory_base) {
1482 error_report("maxmem/slots too huge");
1483 exit(EXIT_FAILURE);
1484 }
1485 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1486 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1487 }
1488
1489 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1490 hwaddr size = extended_memmap[i].size;
1491
1492 base = ROUND_UP(base, size);
1493 vms->memmap[i].base = base;
1494 vms->memmap[i].size = size;
1495 base += size;
1496 }
1497 vms->highest_gpa = base - 1;
1498 if (device_memory_size > 0) {
1499 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1500 ms->device_memory->base = device_memory_base;
1501 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1502 "device-memory", device_memory_size);
1503 }
1504}
1505
1506static void machvirt_init(MachineState *machine)
1507{
1508 VirtMachineState *vms = VIRT_MACHINE(machine);
1509 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1510 MachineClass *mc = MACHINE_GET_CLASS(machine);
1511 const CPUArchIdList *possible_cpus;
1512 qemu_irq pic[NUM_IRQS];
1513 MemoryRegion *sysmem = get_system_memory();
1514 MemoryRegion *secure_sysmem = NULL;
1515 int n, virt_max_cpus;
1516 MemoryRegion *ram = g_new(MemoryRegion, 1);
1517 bool firmware_loaded;
1518 bool aarch64 = true;
1519 bool has_ged = !vmc->no_ged;
1520 unsigned int smp_cpus = machine->smp.cpus;
1521 unsigned int max_cpus = machine->smp.max_cpus;
1522
1523
1524
1525
1526
1527 if (!vms->memmap) {
1528 virt_set_memmap(vms);
1529 }
1530
1531
1532
1533
1534 if (vms->gic_version <= 0) {
1535
1536 if (!kvm_enabled()) {
1537 if (vms->gic_version == 0) {
1538 error_report("gic-version=host requires KVM");
1539 exit(1);
1540 } else {
1541
1542 vms->gic_version = 3;
1543 }
1544 } else {
1545 vms->gic_version = kvm_arm_vgic_probe();
1546 if (!vms->gic_version) {
1547 error_report(
1548 "Unable to determine GIC version supported by host");
1549 exit(1);
1550 }
1551 }
1552 }
1553
1554 if (!cpu_type_valid(machine->cpu_type)) {
1555 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1556 exit(1);
1557 }
1558
1559 if (vms->secure) {
1560 if (kvm_enabled()) {
1561 error_report("mach-virt: KVM does not support Security extensions");
1562 exit(1);
1563 }
1564
1565
1566
1567
1568
1569
1570
1571 secure_sysmem = g_new(MemoryRegion, 1);
1572 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1573 UINT64_MAX);
1574 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1575 }
1576
1577 firmware_loaded = virt_firmware_init(vms, sysmem,
1578 secure_sysmem ?: sysmem);
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590 if (vms->secure && firmware_loaded) {
1591 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1592 } else if (vms->virt) {
1593 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1594 } else {
1595 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1596 }
1597
1598
1599
1600
1601 if (vms->gic_version == 3) {
1602 virt_max_cpus =
1603 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1604 virt_max_cpus +=
1605 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1606 } else {
1607 virt_max_cpus = GIC_NCPU;
1608 }
1609
1610 if (max_cpus > virt_max_cpus) {
1611 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1612 "supported by machine 'mach-virt' (%d)",
1613 max_cpus, virt_max_cpus);
1614 exit(1);
1615 }
1616
1617 vms->smp_cpus = smp_cpus;
1618
1619 if (vms->virt && kvm_enabled()) {
1620 error_report("mach-virt: KVM does not support providing "
1621 "Virtualization extensions to the guest CPU");
1622 exit(1);
1623 }
1624
1625 create_fdt(vms);
1626
1627 possible_cpus = mc->possible_cpu_arch_ids(machine);
1628 for (n = 0; n < possible_cpus->len; n++) {
1629 Object *cpuobj;
1630 CPUState *cs;
1631
1632 if (n >= smp_cpus) {
1633 break;
1634 }
1635
1636 cpuobj = object_new(possible_cpus->cpus[n].type);
1637 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1638 "mp-affinity", NULL);
1639
1640 cs = CPU(cpuobj);
1641 cs->cpu_index = n;
1642
1643 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1644 &error_fatal);
1645
1646 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1647
1648 if (!vms->secure) {
1649 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1650 }
1651
1652 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1653 object_property_set_bool(cpuobj, false, "has_el2", NULL);
1654 }
1655
1656 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1657 object_property_set_int(cpuobj, vms->psci_conduit,
1658 "psci-conduit", NULL);
1659
1660
1661 if (n > 0) {
1662 object_property_set_bool(cpuobj, true,
1663 "start-powered-off", NULL);
1664 }
1665 }
1666
1667 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1668 object_property_set_bool(cpuobj, false, "pmu", NULL);
1669 }
1670
1671 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1672 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1673 "reset-cbar", &error_abort);
1674 }
1675
1676 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1677 &error_abort);
1678 if (vms->secure) {
1679 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1680 "secure-memory", &error_abort);
1681 }
1682
1683 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1684 object_unref(cpuobj);
1685 }
1686 fdt_add_timer_nodes(vms);
1687 fdt_add_cpu_nodes(vms);
1688
1689 if (!kvm_enabled()) {
1690 ARMCPU *cpu = ARM_CPU(first_cpu);
1691 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1692
1693 if (aarch64 && vms->highmem) {
1694 int requested_pa_size, pamax = arm_pamax(cpu);
1695
1696 requested_pa_size = 64 - clz64(vms->highest_gpa);
1697 if (pamax < requested_pa_size) {
1698 error_report("VCPU supports less PA bits (%d) than requested "
1699 "by the memory map (%d)", pamax, requested_pa_size);
1700 exit(1);
1701 }
1702 }
1703 }
1704
1705 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1706 machine->ram_size);
1707 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1708 if (machine->device_memory) {
1709 memory_region_add_subregion(sysmem, machine->device_memory->base,
1710 &machine->device_memory->mr);
1711 }
1712
1713 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
1714
1715 create_gic(vms, pic);
1716
1717 fdt_add_pmu_nodes(vms);
1718
1719 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1720
1721 if (vms->secure) {
1722 create_secure_ram(vms, secure_sysmem);
1723 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1724 }
1725
1726 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1727
1728 create_rtc(vms, pic);
1729
1730 create_pcie(vms, pic);
1731
1732 if (has_ged && aarch64 && firmware_loaded && acpi_enabled) {
1733 vms->acpi_dev = create_acpi_ged(vms, pic);
1734 } else {
1735 create_gpio(vms, pic);
1736 }
1737
1738
1739 vms->powerdown_notifier.notify = virt_powerdown_req;
1740 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
1741
1742
1743
1744
1745
1746 create_virtio_devices(vms, pic);
1747
1748 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1749 rom_set_fw(vms->fw_cfg);
1750
1751 create_platform_bus(vms, pic);
1752
1753 vms->bootinfo.ram_size = machine->ram_size;
1754 vms->bootinfo.nb_cpus = smp_cpus;
1755 vms->bootinfo.board_id = -1;
1756 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1757 vms->bootinfo.get_dtb = machvirt_dtb;
1758 vms->bootinfo.skip_dtb_autoload = true;
1759 vms->bootinfo.firmware_loaded = firmware_loaded;
1760 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
1761
1762 vms->machine_done.notify = virt_machine_done;
1763 qemu_add_machine_init_done_notifier(&vms->machine_done);
1764}
1765
1766static bool virt_get_secure(Object *obj, Error **errp)
1767{
1768 VirtMachineState *vms = VIRT_MACHINE(obj);
1769
1770 return vms->secure;
1771}
1772
1773static void virt_set_secure(Object *obj, bool value, Error **errp)
1774{
1775 VirtMachineState *vms = VIRT_MACHINE(obj);
1776
1777 vms->secure = value;
1778}
1779
1780static bool virt_get_virt(Object *obj, Error **errp)
1781{
1782 VirtMachineState *vms = VIRT_MACHINE(obj);
1783
1784 return vms->virt;
1785}
1786
1787static void virt_set_virt(Object *obj, bool value, Error **errp)
1788{
1789 VirtMachineState *vms = VIRT_MACHINE(obj);
1790
1791 vms->virt = value;
1792}
1793
1794static bool virt_get_highmem(Object *obj, Error **errp)
1795{
1796 VirtMachineState *vms = VIRT_MACHINE(obj);
1797
1798 return vms->highmem;
1799}
1800
1801static void virt_set_highmem(Object *obj, bool value, Error **errp)
1802{
1803 VirtMachineState *vms = VIRT_MACHINE(obj);
1804
1805 vms->highmem = value;
1806}
1807
1808static bool virt_get_its(Object *obj, Error **errp)
1809{
1810 VirtMachineState *vms = VIRT_MACHINE(obj);
1811
1812 return vms->its;
1813}
1814
1815static void virt_set_its(Object *obj, bool value, Error **errp)
1816{
1817 VirtMachineState *vms = VIRT_MACHINE(obj);
1818
1819 vms->its = value;
1820}
1821
1822static char *virt_get_gic_version(Object *obj, Error **errp)
1823{
1824 VirtMachineState *vms = VIRT_MACHINE(obj);
1825 const char *val = vms->gic_version == 3 ? "3" : "2";
1826
1827 return g_strdup(val);
1828}
1829
1830static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1831{
1832 VirtMachineState *vms = VIRT_MACHINE(obj);
1833
1834 if (!strcmp(value, "3")) {
1835 vms->gic_version = 3;
1836 } else if (!strcmp(value, "2")) {
1837 vms->gic_version = 2;
1838 } else if (!strcmp(value, "host")) {
1839 vms->gic_version = 0;
1840 } else if (!strcmp(value, "max")) {
1841 vms->gic_version = -1;
1842 } else {
1843 error_setg(errp, "Invalid gic-version value");
1844 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1845 }
1846}
1847
1848static char *virt_get_iommu(Object *obj, Error **errp)
1849{
1850 VirtMachineState *vms = VIRT_MACHINE(obj);
1851
1852 switch (vms->iommu) {
1853 case VIRT_IOMMU_NONE:
1854 return g_strdup("none");
1855 case VIRT_IOMMU_SMMUV3:
1856 return g_strdup("smmuv3");
1857 default:
1858 g_assert_not_reached();
1859 }
1860}
1861
1862static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1863{
1864 VirtMachineState *vms = VIRT_MACHINE(obj);
1865
1866 if (!strcmp(value, "smmuv3")) {
1867 vms->iommu = VIRT_IOMMU_SMMUV3;
1868 } else if (!strcmp(value, "none")) {
1869 vms->iommu = VIRT_IOMMU_NONE;
1870 } else {
1871 error_setg(errp, "Invalid iommu value");
1872 error_append_hint(errp, "Valid values are none, smmuv3.\n");
1873 }
1874}
1875
1876static CpuInstanceProperties
1877virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1878{
1879 MachineClass *mc = MACHINE_GET_CLASS(ms);
1880 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1881
1882 assert(cpu_index < possible_cpus->len);
1883 return possible_cpus->cpus[cpu_index].props;
1884}
1885
1886static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1887{
1888 return idx % ms->numa_state->num_nodes;
1889}
1890
1891static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1892{
1893 int n;
1894 unsigned int max_cpus = ms->smp.max_cpus;
1895 VirtMachineState *vms = VIRT_MACHINE(ms);
1896
1897 if (ms->possible_cpus) {
1898 assert(ms->possible_cpus->len == max_cpus);
1899 return ms->possible_cpus;
1900 }
1901
1902 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1903 sizeof(CPUArchId) * max_cpus);
1904 ms->possible_cpus->len = max_cpus;
1905 for (n = 0; n < ms->possible_cpus->len; n++) {
1906 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1907 ms->possible_cpus->cpus[n].arch_id =
1908 virt_cpu_mp_affinity(vms, n);
1909 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1910 ms->possible_cpus->cpus[n].props.thread_id = n;
1911 }
1912 return ms->possible_cpus;
1913}
1914
1915static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1916 Error **errp)
1917{
1918 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1919 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1920
1921 if (is_nvdimm) {
1922 error_setg(errp, "nvdimm is not yet supported");
1923 return;
1924 }
1925
1926 if (!vms->acpi_dev) {
1927 error_setg(errp,
1928 "memory hotplug is not enabled: missing acpi-ged device");
1929 return;
1930 }
1931
1932 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
1933}
1934
1935static void virt_memory_plug(HotplugHandler *hotplug_dev,
1936 DeviceState *dev, Error **errp)
1937{
1938 HotplugHandlerClass *hhc;
1939 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1940 Error *local_err = NULL;
1941
1942 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err);
1943 if (local_err) {
1944 goto out;
1945 }
1946
1947 hhc = HOTPLUG_HANDLER_GET_CLASS(vms->acpi_dev);
1948 hhc->plug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &error_abort);
1949out:
1950 error_propagate(errp, local_err);
1951}
1952
1953static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1954 DeviceState *dev, Error **errp)
1955{
1956 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1957 virt_memory_pre_plug(hotplug_dev, dev, errp);
1958 }
1959}
1960
1961static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1962 DeviceState *dev, Error **errp)
1963{
1964 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1965
1966 if (vms->platform_bus_dev) {
1967 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1968 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1969 SYS_BUS_DEVICE(dev));
1970 }
1971 }
1972 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1973 virt_memory_plug(hotplug_dev, dev, errp);
1974 }
1975}
1976
1977static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1978 DeviceState *dev, Error **errp)
1979{
1980 error_setg(errp, "device unplug request for unsupported device"
1981 " type: %s", object_get_typename(OBJECT(dev)));
1982}
1983
1984static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1985 DeviceState *dev)
1986{
1987 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) ||
1988 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
1989 return HOTPLUG_HANDLER(machine);
1990 }
1991
1992 return NULL;
1993}
1994
1995
1996
1997
1998
1999static int virt_kvm_type(MachineState *ms, const char *type_str)
2000{
2001 VirtMachineState *vms = VIRT_MACHINE(ms);
2002 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
2003 int requested_pa_size;
2004
2005
2006 virt_set_memmap(vms);
2007
2008 requested_pa_size = 64 - clz64(vms->highest_gpa);
2009
2010 if (requested_pa_size > max_vm_pa_size) {
2011 error_report("-m and ,maxmem option values "
2012 "require an IPA range (%d bits) larger than "
2013 "the one supported by the host (%d bits)",
2014 requested_pa_size, max_vm_pa_size);
2015 exit(1);
2016 }
2017
2018
2019
2020
2021
2022 return requested_pa_size > 40 ? requested_pa_size : 0;
2023}
2024
2025static void virt_machine_class_init(ObjectClass *oc, void *data)
2026{
2027 MachineClass *mc = MACHINE_CLASS(oc);
2028 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2029
2030 mc->init = machvirt_init;
2031
2032
2033
2034
2035 mc->max_cpus = 512;
2036 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2037 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2038 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2039 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2040 mc->block_default_type = IF_VIRTIO;
2041 mc->no_cdrom = 1;
2042 mc->pci_allow_0_address = true;
2043
2044 mc->minimum_page_bits = 12;
2045 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2046 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2047 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2048 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2049 mc->kvm_type = virt_kvm_type;
2050 assert(!mc->get_hotplug_handler);
2051 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2052 hc->pre_plug = virt_machine_device_pre_plug_cb;
2053 hc->plug = virt_machine_device_plug_cb;
2054 hc->unplug_request = virt_machine_device_unplug_request_cb;
2055 mc->numa_mem_supported = true;
2056 mc->auto_enable_numa_with_memhp = true;
2057}
2058
2059static void virt_instance_init(Object *obj)
2060{
2061 VirtMachineState *vms = VIRT_MACHINE(obj);
2062 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2063
2064
2065
2066
2067
2068 vms->secure = false;
2069 object_property_add_bool(obj, "secure", virt_get_secure,
2070 virt_set_secure, NULL);
2071 object_property_set_description(obj, "secure",
2072 "Set on/off to enable/disable the ARM "
2073 "Security Extensions (TrustZone)",
2074 NULL);
2075
2076
2077 vms->virt = false;
2078 object_property_add_bool(obj, "virtualization", virt_get_virt,
2079 virt_set_virt, NULL);
2080 object_property_set_description(obj, "virtualization",
2081 "Set on/off to enable/disable emulating a "
2082 "guest CPU which implements the ARM "
2083 "Virtualization Extensions",
2084 NULL);
2085
2086
2087 vms->highmem = true;
2088 object_property_add_bool(obj, "highmem", virt_get_highmem,
2089 virt_set_highmem, NULL);
2090 object_property_set_description(obj, "highmem",
2091 "Set on/off to enable/disable using "
2092 "physical address space above 32 bits",
2093 NULL);
2094
2095 vms->gic_version = 2;
2096 object_property_add_str(obj, "gic-version", virt_get_gic_version,
2097 virt_set_gic_version, NULL);
2098 object_property_set_description(obj, "gic-version",
2099 "Set GIC version. "
2100 "Valid values are 2, 3 and host", NULL);
2101
2102 vms->highmem_ecam = !vmc->no_highmem_ecam;
2103
2104 if (vmc->no_its) {
2105 vms->its = false;
2106 } else {
2107
2108 vms->its = true;
2109 object_property_add_bool(obj, "its", virt_get_its,
2110 virt_set_its, NULL);
2111 object_property_set_description(obj, "its",
2112 "Set on/off to enable/disable "
2113 "ITS instantiation",
2114 NULL);
2115 }
2116
2117
2118 vms->iommu = VIRT_IOMMU_NONE;
2119 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
2120 object_property_set_description(obj, "iommu",
2121 "Set the IOMMU type. "
2122 "Valid values are none and smmuv3",
2123 NULL);
2124
2125 vms->irqmap = a15irqmap;
2126
2127 virt_flash_create(vms);
2128}
2129
2130static const TypeInfo virt_machine_info = {
2131 .name = TYPE_VIRT_MACHINE,
2132 .parent = TYPE_MACHINE,
2133 .abstract = true,
2134 .instance_size = sizeof(VirtMachineState),
2135 .class_size = sizeof(VirtMachineClass),
2136 .class_init = virt_machine_class_init,
2137 .instance_init = virt_instance_init,
2138 .interfaces = (InterfaceInfo[]) {
2139 { TYPE_HOTPLUG_HANDLER },
2140 { }
2141 },
2142};
2143
2144static void machvirt_machine_init(void)
2145{
2146 type_register_static(&virt_machine_info);
2147}
2148type_init(machvirt_machine_init);
2149
2150static void virt_machine_4_2_options(MachineClass *mc)
2151{
2152}
2153DEFINE_VIRT_MACHINE_AS_LATEST(4, 2)
2154
2155static void virt_machine_4_1_options(MachineClass *mc)
2156{
2157 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2158
2159 virt_machine_4_2_options(mc);
2160 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2161 vmc->no_ged = true;
2162 mc->auto_enable_numa_with_memhp = false;
2163}
2164DEFINE_VIRT_MACHINE(4, 1)
2165
2166static void virt_machine_4_0_options(MachineClass *mc)
2167{
2168 virt_machine_4_1_options(mc);
2169 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2170}
2171DEFINE_VIRT_MACHINE(4, 0)
2172
2173static void virt_machine_3_1_options(MachineClass *mc)
2174{
2175 virt_machine_4_0_options(mc);
2176 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2177}
2178DEFINE_VIRT_MACHINE(3, 1)
2179
2180static void virt_machine_3_0_options(MachineClass *mc)
2181{
2182 virt_machine_3_1_options(mc);
2183 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2184}
2185DEFINE_VIRT_MACHINE(3, 0)
2186
2187static void virt_machine_2_12_options(MachineClass *mc)
2188{
2189 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2190
2191 virt_machine_3_0_options(mc);
2192 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2193 vmc->no_highmem_ecam = true;
2194 mc->max_cpus = 255;
2195}
2196DEFINE_VIRT_MACHINE(2, 12)
2197
2198static void virt_machine_2_11_options(MachineClass *mc)
2199{
2200 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2201
2202 virt_machine_2_12_options(mc);
2203 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2204 vmc->smbios_old_sys_ver = true;
2205}
2206DEFINE_VIRT_MACHINE(2, 11)
2207
2208static void virt_machine_2_10_options(MachineClass *mc)
2209{
2210 virt_machine_2_11_options(mc);
2211 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2212
2213 mc->ignore_memory_transaction_failures = true;
2214}
2215DEFINE_VIRT_MACHINE(2, 10)
2216
2217static void virt_machine_2_9_options(MachineClass *mc)
2218{
2219 virt_machine_2_10_options(mc);
2220 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2221}
2222DEFINE_VIRT_MACHINE(2, 9)
2223
2224static void virt_machine_2_8_options(MachineClass *mc)
2225{
2226 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2227
2228 virt_machine_2_9_options(mc);
2229 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2230
2231
2232
2233 vmc->claim_edge_triggered_timers = true;
2234}
2235DEFINE_VIRT_MACHINE(2, 8)
2236
2237static void virt_machine_2_7_options(MachineClass *mc)
2238{
2239 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2240
2241 virt_machine_2_8_options(mc);
2242 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2243
2244 vmc->no_its = true;
2245
2246 mc->minimum_page_bits = 0;
2247}
2248DEFINE_VIRT_MACHINE(2, 7)
2249
2250static void virt_machine_2_6_options(MachineClass *mc)
2251{
2252 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2253
2254 virt_machine_2_7_options(mc);
2255 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2256 vmc->disallow_affinity_adjustment = true;
2257
2258 vmc->no_pmu = true;
2259}
2260DEFINE_VIRT_MACHINE(2, 6)
2261