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20#include "qemu/osdep.h"
21#include "hw/audio/soundhw.h"
22#include "audio/audio.h"
23#include "hw/pci/pci.h"
24#include "hw/qdev-properties.h"
25#include "migration/vmstate.h"
26#include "qemu/module.h"
27#include "sysemu/dma.h"
28
29enum {
30 AC97_Reset = 0x00,
31 AC97_Master_Volume_Mute = 0x02,
32 AC97_Headphone_Volume_Mute = 0x04,
33 AC97_Master_Volume_Mono_Mute = 0x06,
34 AC97_Master_Tone_RL = 0x08,
35 AC97_PC_BEEP_Volume_Mute = 0x0A,
36 AC97_Phone_Volume_Mute = 0x0C,
37 AC97_Mic_Volume_Mute = 0x0E,
38 AC97_Line_In_Volume_Mute = 0x10,
39 AC97_CD_Volume_Mute = 0x12,
40 AC97_Video_Volume_Mute = 0x14,
41 AC97_Aux_Volume_Mute = 0x16,
42 AC97_PCM_Out_Volume_Mute = 0x18,
43 AC97_Record_Select = 0x1A,
44 AC97_Record_Gain_Mute = 0x1C,
45 AC97_Record_Gain_Mic_Mute = 0x1E,
46 AC97_General_Purpose = 0x20,
47 AC97_3D_Control = 0x22,
48 AC97_AC_97_RESERVED = 0x24,
49 AC97_Powerdown_Ctrl_Stat = 0x26,
50 AC97_Extended_Audio_ID = 0x28,
51 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
52 AC97_PCM_Front_DAC_Rate = 0x2C,
53 AC97_PCM_Surround_DAC_Rate = 0x2E,
54 AC97_PCM_LFE_DAC_Rate = 0x30,
55 AC97_PCM_LR_ADC_Rate = 0x32,
56 AC97_MIC_ADC_Rate = 0x34,
57 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
58 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
59 AC97_Vendor_Reserved = 0x58,
60 AC97_Sigmatel_Analog = 0x6c,
61 AC97_Sigmatel_Dac2Invert = 0x6e,
62 AC97_Vendor_ID1 = 0x7c,
63 AC97_Vendor_ID2 = 0x7e
64};
65
66#define SOFT_VOLUME
67#define SR_FIFOE 16
68#define SR_BCIS 8
69#define SR_LVBCI 4
70#define SR_CELV 2
71#define SR_DCH 1
72#define SR_VALID_MASK ((1 << 5) - 1)
73#define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
74#define SR_RO_MASK (SR_DCH | SR_CELV)
75#define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
76
77#define CR_IOCE 16
78#define CR_FEIE 8
79#define CR_LVBIE 4
80#define CR_RR 2
81#define CR_RPBM 1
82#define CR_VALID_MASK ((1 << 5) - 1)
83#define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
84
85#define GC_WR 4
86#define GC_CR 2
87#define GC_VALID_MASK ((1 << 6) - 1)
88
89#define GS_MD3 (1<<17)
90#define GS_AD3 (1<<16)
91#define GS_RCS (1<<15)
92#define GS_B3S12 (1<<14)
93#define GS_B2S12 (1<<13)
94#define GS_B1S12 (1<<12)
95#define GS_S1R1 (1<<11)
96#define GS_S0R1 (1<<10)
97#define GS_S1CR (1<<9)
98#define GS_S0CR (1<<8)
99#define GS_MINT (1<<7)
100#define GS_POINT (1<<6)
101#define GS_PIINT (1<<5)
102#define GS_RSRVD ((1<<4)|(1<<3))
103#define GS_MOINT (1<<2)
104#define GS_MIINT (1<<1)
105#define GS_GSCI 1
106#define GS_RO_MASK (GS_B3S12| \
107 GS_B2S12| \
108 GS_B1S12| \
109 GS_S1CR| \
110 GS_S0CR| \
111 GS_MINT| \
112 GS_POINT| \
113 GS_PIINT| \
114 GS_RSRVD| \
115 GS_MOINT| \
116 GS_MIINT)
117#define GS_VALID_MASK ((1 << 18) - 1)
118#define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
119
120#define BD_IOC (1<<31)
121#define BD_BUP (1<<30)
122
123#define EACS_VRA 1
124#define EACS_VRM 8
125
126#define MUTE_SHIFT 15
127
128#define TYPE_AC97 "AC97"
129#define AC97(obj) \
130 OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97)
131
132#define REC_MASK 7
133enum {
134 REC_MIC = 0,
135 REC_CD,
136 REC_VIDEO,
137 REC_AUX,
138 REC_LINE_IN,
139 REC_STEREO_MIX,
140 REC_MONO_MIX,
141 REC_PHONE
142};
143
144typedef struct BD {
145 uint32_t addr;
146 uint32_t ctl_len;
147} BD;
148
149typedef struct AC97BusMasterRegs {
150 uint32_t bdbar;
151 uint8_t civ;
152 uint8_t lvi;
153 uint16_t sr;
154 uint16_t picb;
155 uint8_t piv;
156 uint8_t cr;
157 unsigned int bd_valid;
158 BD bd;
159} AC97BusMasterRegs;
160
161typedef struct AC97LinkState {
162 PCIDevice dev;
163 QEMUSoundCard card;
164 uint32_t use_broken_id;
165 uint32_t glob_cnt;
166 uint32_t glob_sta;
167 uint32_t cas;
168 uint32_t last_samp;
169 AC97BusMasterRegs bm_regs[3];
170 uint8_t mixer_data[256];
171 SWVoiceIn *voice_pi;
172 SWVoiceOut *voice_po;
173 SWVoiceIn *voice_mc;
174 int invalid_freq[3];
175 uint8_t silence[128];
176 int bup_flag;
177 MemoryRegion io_nam;
178 MemoryRegion io_nabm;
179} AC97LinkState;
180
181enum {
182 BUP_SET = 1,
183 BUP_LAST = 2
184};
185
186#ifdef DEBUG_AC97
187#define dolog(...) AUD_log ("ac97", __VA_ARGS__)
188#else
189#define dolog(...)
190#endif
191
192#define MKREGS(prefix, start) \
193enum { \
194 prefix ## _BDBAR = start, \
195 prefix ## _CIV = start + 4, \
196 prefix ## _LVI = start + 5, \
197 prefix ## _SR = start + 6, \
198 prefix ## _PICB = start + 8, \
199 prefix ## _PIV = start + 10, \
200 prefix ## _CR = start + 11 \
201}
202
203enum {
204 PI_INDEX = 0,
205 PO_INDEX,
206 MC_INDEX,
207 LAST_INDEX
208};
209
210MKREGS (PI, PI_INDEX * 16);
211MKREGS (PO, PO_INDEX * 16);
212MKREGS (MC, MC_INDEX * 16);
213
214enum {
215 GLOB_CNT = 0x2c,
216 GLOB_STA = 0x30,
217 CAS = 0x34
218};
219
220#define GET_BM(index) (((index) >> 4) & 3)
221
222static void po_callback (void *opaque, int free);
223static void pi_callback (void *opaque, int avail);
224static void mc_callback (void *opaque, int avail);
225
226static void warm_reset (AC97LinkState *s)
227{
228 (void) s;
229}
230
231static void cold_reset (AC97LinkState * s)
232{
233 (void) s;
234}
235
236static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
237{
238 uint8_t b[8];
239
240 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
241 r->bd_valid = 1;
242 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
243 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
244 r->picb = r->bd.ctl_len & 0xffff;
245 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
246 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
247 r->bd.ctl_len & 0xffff,
248 (r->bd.ctl_len & 0xffff) << 1);
249}
250
251static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
252{
253 int event = 0;
254 int level = 0;
255 uint32_t new_mask = new_sr & SR_INT_MASK;
256 uint32_t old_mask = r->sr & SR_INT_MASK;
257 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
258
259 if (new_mask ^ old_mask) {
260
261 if (!new_mask) {
262 event = 1;
263 level = 0;
264 }
265 else {
266 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
267 event = 1;
268 level = 1;
269 }
270 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
271 event = 1;
272 level = 1;
273 }
274 }
275 }
276
277 r->sr = new_sr;
278
279 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
280 r->sr & SR_BCIS, r->sr & SR_LVBCI,
281 r->sr,
282 event, level);
283
284 if (!event)
285 return;
286
287 if (level) {
288 s->glob_sta |= masks[r - s->bm_regs];
289 dolog ("set irq level=1\n");
290 pci_irq_assert(&s->dev);
291 }
292 else {
293 s->glob_sta &= ~masks[r - s->bm_regs];
294 dolog ("set irq level=0\n");
295 pci_irq_deassert(&s->dev);
296 }
297}
298
299static void voice_set_active (AC97LinkState *s, int bm_index, int on)
300{
301 switch (bm_index) {
302 case PI_INDEX:
303 AUD_set_active_in (s->voice_pi, on);
304 break;
305
306 case PO_INDEX:
307 AUD_set_active_out (s->voice_po, on);
308 break;
309
310 case MC_INDEX:
311 AUD_set_active_in (s->voice_mc, on);
312 break;
313
314 default:
315 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
316 break;
317 }
318}
319
320static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
321{
322 dolog ("reset_bm_regs\n");
323 r->bdbar = 0;
324 r->civ = 0;
325 r->lvi = 0;
326
327 update_sr (s, r, SR_DCH);
328 r->picb = 0;
329 r->piv = 0;
330 r->cr = r->cr & CR_DONT_CLEAR_MASK;
331 r->bd_valid = 0;
332
333 voice_set_active (s, r - s->bm_regs, 0);
334 memset (s->silence, 0, sizeof (s->silence));
335}
336
337static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
338{
339 if (i + 2 > sizeof (s->mixer_data)) {
340 dolog ("mixer_store: index %d out of bounds %zd\n",
341 i, sizeof (s->mixer_data));
342 return;
343 }
344
345 s->mixer_data[i + 0] = v & 0xff;
346 s->mixer_data[i + 1] = v >> 8;
347}
348
349static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
350{
351 uint16_t val = 0xffff;
352
353 if (i + 2 > sizeof (s->mixer_data)) {
354 dolog ("mixer_load: index %d out of bounds %zd\n",
355 i, sizeof (s->mixer_data));
356 }
357 else {
358 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
359 }
360
361 return val;
362}
363
364static void open_voice (AC97LinkState *s, int index, int freq)
365{
366 struct audsettings as;
367
368 as.freq = freq;
369 as.nchannels = 2;
370 as.fmt = AUDIO_FORMAT_S16;
371 as.endianness = 0;
372
373 if (freq > 0) {
374 s->invalid_freq[index] = 0;
375 switch (index) {
376 case PI_INDEX:
377 s->voice_pi = AUD_open_in (
378 &s->card,
379 s->voice_pi,
380 "ac97.pi",
381 s,
382 pi_callback,
383 &as
384 );
385 break;
386
387 case PO_INDEX:
388 s->voice_po = AUD_open_out (
389 &s->card,
390 s->voice_po,
391 "ac97.po",
392 s,
393 po_callback,
394 &as
395 );
396 break;
397
398 case MC_INDEX:
399 s->voice_mc = AUD_open_in (
400 &s->card,
401 s->voice_mc,
402 "ac97.mc",
403 s,
404 mc_callback,
405 &as
406 );
407 break;
408 }
409 }
410 else {
411 s->invalid_freq[index] = freq;
412 switch (index) {
413 case PI_INDEX:
414 AUD_close_in (&s->card, s->voice_pi);
415 s->voice_pi = NULL;
416 break;
417
418 case PO_INDEX:
419 AUD_close_out (&s->card, s->voice_po);
420 s->voice_po = NULL;
421 break;
422
423 case MC_INDEX:
424 AUD_close_in (&s->card, s->voice_mc);
425 s->voice_mc = NULL;
426 break;
427 }
428 }
429}
430
431static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
432{
433 uint16_t freq;
434
435 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
436 open_voice (s, PI_INDEX, freq);
437 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
438
439 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
440 open_voice (s, PO_INDEX, freq);
441 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
442
443 freq = mixer_load (s, AC97_MIC_ADC_Rate);
444 open_voice (s, MC_INDEX, freq);
445 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
446}
447
448static void get_volume (uint16_t vol, uint16_t mask, int inverse,
449 int *mute, uint8_t *lvol, uint8_t *rvol)
450{
451 *mute = (vol >> MUTE_SHIFT) & 1;
452 *rvol = (255 * (vol & mask)) / mask;
453 *lvol = (255 * ((vol >> 8) & mask)) / mask;
454
455 if (inverse) {
456 *rvol = 255 - *rvol;
457 *lvol = 255 - *lvol;
458 }
459}
460
461static void update_combined_volume_out (AC97LinkState *s)
462{
463 uint8_t lvol, rvol, plvol, prvol;
464 int mute, pmute;
465
466 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1,
467 &mute, &lvol, &rvol);
468 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1,
469 &pmute, &plvol, &prvol);
470
471 mute = mute | pmute;
472 lvol = (lvol * plvol) / 255;
473 rvol = (rvol * prvol) / 255;
474
475 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
476}
477
478static void update_volume_in (AC97LinkState *s)
479{
480 uint8_t lvol, rvol;
481 int mute;
482
483 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0,
484 &mute, &lvol, &rvol);
485
486 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol);
487}
488
489static void set_volume (AC97LinkState *s, int index, uint32_t val)
490{
491 switch (index) {
492 case AC97_Master_Volume_Mute:
493 val &= 0xbf3f;
494 mixer_store (s, index, val);
495 update_combined_volume_out (s);
496 break;
497 case AC97_PCM_Out_Volume_Mute:
498 val &= 0x9f1f;
499 mixer_store (s, index, val);
500 update_combined_volume_out (s);
501 break;
502 case AC97_Record_Gain_Mute:
503 val &= 0x8f0f;
504 mixer_store (s, index, val);
505 update_volume_in (s);
506 break;
507 }
508}
509
510static void record_select (AC97LinkState *s, uint32_t val)
511{
512 uint8_t rs = val & REC_MASK;
513 uint8_t ls = (val >> 8) & REC_MASK;
514 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
515}
516
517static void mixer_reset (AC97LinkState *s)
518{
519 uint8_t active[LAST_INDEX];
520
521 dolog ("mixer_reset\n");
522 memset (s->mixer_data, 0, sizeof (s->mixer_data));
523 memset (active, 0, sizeof (active));
524 mixer_store (s, AC97_Reset , 0x0000);
525 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000);
526 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000);
527 mixer_store (s, AC97_Master_Tone_RL, 0x0000);
528 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
529 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000);
530 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000);
531 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000);
532 mixer_store (s, AC97_CD_Volume_Mute , 0x0000);
533 mixer_store (s, AC97_Video_Volume_Mute , 0x0000);
534 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000);
535 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000);
536 mixer_store (s, AC97_General_Purpose , 0x0000);
537 mixer_store (s, AC97_3D_Control , 0x0000);
538 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
539
540
541
542
543 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
544 mixer_store (s, AC97_Vendor_ID2 , 0x7600);
545
546 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
547 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
548 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
549 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
550 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
551 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
552 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
553
554 record_select (s, 0);
555 set_volume (s, AC97_Master_Volume_Mute, 0x8000);
556 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
557 set_volume (s, AC97_Record_Gain_Mute, 0x8808);
558
559 reset_voices (s, active);
560}
561
562
563
564
565
566static uint32_t nam_readb (void *opaque, uint32_t addr)
567{
568 AC97LinkState *s = opaque;
569 dolog ("U nam readb %#x\n", addr);
570 s->cas = 0;
571 return ~0U;
572}
573
574static uint32_t nam_readw (void *opaque, uint32_t addr)
575{
576 AC97LinkState *s = opaque;
577 uint32_t val = ~0U;
578 uint32_t index = addr;
579 s->cas = 0;
580 val = mixer_load (s, index);
581 return val;
582}
583
584static uint32_t nam_readl (void *opaque, uint32_t addr)
585{
586 AC97LinkState *s = opaque;
587 dolog ("U nam readl %#x\n", addr);
588 s->cas = 0;
589 return ~0U;
590}
591
592
593
594
595
596static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
597{
598 AC97LinkState *s = opaque;
599 dolog ("U nam writeb %#x <- %#x\n", addr, val);
600 s->cas = 0;
601}
602
603static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
604{
605 AC97LinkState *s = opaque;
606 uint32_t index = addr;
607 s->cas = 0;
608 switch (index) {
609 case AC97_Reset:
610 mixer_reset (s);
611 break;
612 case AC97_Powerdown_Ctrl_Stat:
613 val &= ~0x800f;
614 val |= mixer_load (s, index) & 0xf;
615 mixer_store (s, index, val);
616 break;
617 case AC97_PCM_Out_Volume_Mute:
618 case AC97_Master_Volume_Mute:
619 case AC97_Record_Gain_Mute:
620 set_volume (s, index, val);
621 break;
622 case AC97_Record_Select:
623 record_select (s, val);
624 break;
625 case AC97_Vendor_ID1:
626 case AC97_Vendor_ID2:
627 dolog ("Attempt to write vendor ID to %#x\n", val);
628 break;
629 case AC97_Extended_Audio_ID:
630 dolog ("Attempt to write extended audio ID to %#x\n", val);
631 break;
632 case AC97_Extended_Audio_Ctrl_Stat:
633 if (!(val & EACS_VRA)) {
634 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
635 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
636 open_voice (s, PI_INDEX, 48000);
637 open_voice (s, PO_INDEX, 48000);
638 }
639 if (!(val & EACS_VRM)) {
640 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
641 open_voice (s, MC_INDEX, 48000);
642 }
643 dolog ("Setting extended audio control to %#x\n", val);
644 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
645 break;
646 case AC97_PCM_Front_DAC_Rate:
647 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
648 mixer_store (s, index, val);
649 dolog ("Set front DAC rate to %d\n", val);
650 open_voice (s, PO_INDEX, val);
651 }
652 else {
653 dolog ("Attempt to set front DAC rate to %d, "
654 "but VRA is not set\n",
655 val);
656 }
657 break;
658 case AC97_MIC_ADC_Rate:
659 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
660 mixer_store (s, index, val);
661 dolog ("Set MIC ADC rate to %d\n", val);
662 open_voice (s, MC_INDEX, val);
663 }
664 else {
665 dolog ("Attempt to set MIC ADC rate to %d, "
666 "but VRM is not set\n",
667 val);
668 }
669 break;
670 case AC97_PCM_LR_ADC_Rate:
671 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
672 mixer_store (s, index, val);
673 dolog ("Set front LR ADC rate to %d\n", val);
674 open_voice (s, PI_INDEX, val);
675 }
676 else {
677 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
678 val);
679 }
680 break;
681 case AC97_Headphone_Volume_Mute:
682 case AC97_Master_Volume_Mono_Mute:
683 case AC97_Master_Tone_RL:
684 case AC97_PC_BEEP_Volume_Mute:
685 case AC97_Phone_Volume_Mute:
686 case AC97_Mic_Volume_Mute:
687 case AC97_Line_In_Volume_Mute:
688 case AC97_CD_Volume_Mute:
689 case AC97_Video_Volume_Mute:
690 case AC97_Aux_Volume_Mute:
691 case AC97_Record_Gain_Mic_Mute:
692 case AC97_General_Purpose:
693 case AC97_3D_Control:
694 case AC97_Sigmatel_Analog:
695 case AC97_Sigmatel_Dac2Invert:
696
697 break;
698 default:
699 dolog ("U nam writew %#x <- %#x\n", addr, val);
700 mixer_store (s, index, val);
701 break;
702 }
703}
704
705static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
706{
707 AC97LinkState *s = opaque;
708 dolog ("U nam writel %#x <- %#x\n", addr, val);
709 s->cas = 0;
710}
711
712
713
714
715
716static uint32_t nabm_readb (void *opaque, uint32_t addr)
717{
718 AC97LinkState *s = opaque;
719 AC97BusMasterRegs *r = NULL;
720 uint32_t index = addr;
721 uint32_t val = ~0U;
722
723 switch (index) {
724 case CAS:
725 dolog ("CAS %d\n", s->cas);
726 val = s->cas;
727 s->cas = 1;
728 break;
729 case PI_CIV:
730 case PO_CIV:
731 case MC_CIV:
732 r = &s->bm_regs[GET_BM (index)];
733 val = r->civ;
734 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
735 break;
736 case PI_LVI:
737 case PO_LVI:
738 case MC_LVI:
739 r = &s->bm_regs[GET_BM (index)];
740 val = r->lvi;
741 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
742 break;
743 case PI_PIV:
744 case PO_PIV:
745 case MC_PIV:
746 r = &s->bm_regs[GET_BM (index)];
747 val = r->piv;
748 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
749 break;
750 case PI_CR:
751 case PO_CR:
752 case MC_CR:
753 r = &s->bm_regs[GET_BM (index)];
754 val = r->cr;
755 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
756 break;
757 case PI_SR:
758 case PO_SR:
759 case MC_SR:
760 r = &s->bm_regs[GET_BM (index)];
761 val = r->sr & 0xff;
762 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
763 break;
764 default:
765 dolog ("U nabm readb %#x -> %#x\n", addr, val);
766 break;
767 }
768 return val;
769}
770
771static uint32_t nabm_readw (void *opaque, uint32_t addr)
772{
773 AC97LinkState *s = opaque;
774 AC97BusMasterRegs *r = NULL;
775 uint32_t index = addr;
776 uint32_t val = ~0U;
777
778 switch (index) {
779 case PI_SR:
780 case PO_SR:
781 case MC_SR:
782 r = &s->bm_regs[GET_BM (index)];
783 val = r->sr;
784 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
785 break;
786 case PI_PICB:
787 case PO_PICB:
788 case MC_PICB:
789 r = &s->bm_regs[GET_BM (index)];
790 val = r->picb;
791 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
792 break;
793 default:
794 dolog ("U nabm readw %#x -> %#x\n", addr, val);
795 break;
796 }
797 return val;
798}
799
800static uint32_t nabm_readl (void *opaque, uint32_t addr)
801{
802 AC97LinkState *s = opaque;
803 AC97BusMasterRegs *r = NULL;
804 uint32_t index = addr;
805 uint32_t val = ~0U;
806
807 switch (index) {
808 case PI_BDBAR:
809 case PO_BDBAR:
810 case MC_BDBAR:
811 r = &s->bm_regs[GET_BM (index)];
812 val = r->bdbar;
813 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
814 break;
815 case PI_CIV:
816 case PO_CIV:
817 case MC_CIV:
818 r = &s->bm_regs[GET_BM (index)];
819 val = r->civ | (r->lvi << 8) | (r->sr << 16);
820 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
821 r->civ, r->lvi, r->sr);
822 break;
823 case PI_PICB:
824 case PO_PICB:
825 case MC_PICB:
826 r = &s->bm_regs[GET_BM (index)];
827 val = r->picb | (r->piv << 16) | (r->cr << 24);
828 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
829 val, r->picb, r->piv, r->cr);
830 break;
831 case GLOB_CNT:
832 val = s->glob_cnt;
833 dolog ("glob_cnt -> %#x\n", val);
834 break;
835 case GLOB_STA:
836 val = s->glob_sta | GS_S0CR;
837 dolog ("glob_sta -> %#x\n", val);
838 break;
839 default:
840 dolog ("U nabm readl %#x -> %#x\n", addr, val);
841 break;
842 }
843 return val;
844}
845
846
847
848
849
850static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
851{
852 AC97LinkState *s = opaque;
853 AC97BusMasterRegs *r = NULL;
854 uint32_t index = addr;
855 switch (index) {
856 case PI_LVI:
857 case PO_LVI:
858 case MC_LVI:
859 r = &s->bm_regs[GET_BM (index)];
860 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
861 r->sr &= ~(SR_DCH | SR_CELV);
862 r->civ = r->piv;
863 r->piv = (r->piv + 1) % 32;
864 fetch_bd (s, r);
865 }
866 r->lvi = val % 32;
867 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
868 break;
869 case PI_CR:
870 case PO_CR:
871 case MC_CR:
872 r = &s->bm_regs[GET_BM (index)];
873 if (val & CR_RR) {
874 reset_bm_regs (s, r);
875 }
876 else {
877 r->cr = val & CR_VALID_MASK;
878 if (!(r->cr & CR_RPBM)) {
879 voice_set_active (s, r - s->bm_regs, 0);
880 r->sr |= SR_DCH;
881 }
882 else {
883 r->civ = r->piv;
884 r->piv = (r->piv + 1) % 32;
885 fetch_bd (s, r);
886 r->sr &= ~SR_DCH;
887 voice_set_active (s, r - s->bm_regs, 1);
888 }
889 }
890 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
891 break;
892 case PI_SR:
893 case PO_SR:
894 case MC_SR:
895 r = &s->bm_regs[GET_BM (index)];
896 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
897 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
898 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
899 break;
900 default:
901 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
902 break;
903 }
904}
905
906static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
907{
908 AC97LinkState *s = opaque;
909 AC97BusMasterRegs *r = NULL;
910 uint32_t index = addr;
911 switch (index) {
912 case PI_SR:
913 case PO_SR:
914 case MC_SR:
915 r = &s->bm_regs[GET_BM (index)];
916 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
917 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
918 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
919 break;
920 default:
921 dolog ("U nabm writew %#x <- %#x\n", addr, val);
922 break;
923 }
924}
925
926static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
927{
928 AC97LinkState *s = opaque;
929 AC97BusMasterRegs *r = NULL;
930 uint32_t index = addr;
931 switch (index) {
932 case PI_BDBAR:
933 case PO_BDBAR:
934 case MC_BDBAR:
935 r = &s->bm_regs[GET_BM (index)];
936 r->bdbar = val & ~3;
937 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
938 GET_BM (index), val, r->bdbar);
939 break;
940 case GLOB_CNT:
941 if (val & GC_WR)
942 warm_reset (s);
943 if (val & GC_CR)
944 cold_reset (s);
945 if (!(val & (GC_WR | GC_CR)))
946 s->glob_cnt = val & GC_VALID_MASK;
947 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
948 break;
949 case GLOB_STA:
950 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
951 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
952 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
953 break;
954 default:
955 dolog ("U nabm writel %#x <- %#x\n", addr, val);
956 break;
957 }
958}
959
960static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
961 int max, int *stop)
962{
963 uint8_t tmpbuf[4096];
964 uint32_t addr = r->bd.addr;
965 uint32_t temp = r->picb << 1;
966 uint32_t written = 0;
967 int to_copy = 0;
968 temp = MIN (temp, max);
969
970 if (!temp) {
971 *stop = 1;
972 return 0;
973 }
974
975 while (temp) {
976 int copied;
977 to_copy = MIN (temp, sizeof (tmpbuf));
978 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
979 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
980 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
981 max, to_copy, copied);
982 if (!copied) {
983 *stop = 1;
984 break;
985 }
986 temp -= copied;
987 addr += copied;
988 written += copied;
989 }
990
991 if (!temp) {
992 if (to_copy < 4) {
993 dolog ("whoops\n");
994 s->last_samp = 0;
995 }
996 else {
997 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
998 }
999 }
1000
1001 r->bd.addr = addr;
1002 return written;
1003}
1004
1005static void write_bup (AC97LinkState *s, int elapsed)
1006{
1007 dolog ("write_bup\n");
1008 if (!(s->bup_flag & BUP_SET)) {
1009 if (s->bup_flag & BUP_LAST) {
1010 int i;
1011 uint8_t *p = s->silence;
1012 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1013 *(uint32_t *) p = s->last_samp;
1014 }
1015 }
1016 else {
1017 memset (s->silence, 0, sizeof (s->silence));
1018 }
1019 s->bup_flag |= BUP_SET;
1020 }
1021
1022 while (elapsed) {
1023 int temp = MIN (elapsed, sizeof (s->silence));
1024 while (temp) {
1025 int copied = AUD_write (s->voice_po, s->silence, temp);
1026 if (!copied)
1027 return;
1028 temp -= copied;
1029 elapsed -= copied;
1030 }
1031 }
1032}
1033
1034static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1035 int max, int *stop)
1036{
1037 uint8_t tmpbuf[4096];
1038 uint32_t addr = r->bd.addr;
1039 uint32_t temp = r->picb << 1;
1040 uint32_t nread = 0;
1041 int to_copy = 0;
1042 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1043
1044 temp = MIN (temp, max);
1045
1046 if (!temp) {
1047 *stop = 1;
1048 return 0;
1049 }
1050
1051 while (temp) {
1052 int acquired;
1053 to_copy = MIN (temp, sizeof (tmpbuf));
1054 acquired = AUD_read (voice, tmpbuf, to_copy);
1055 if (!acquired) {
1056 *stop = 1;
1057 break;
1058 }
1059 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1060 temp -= acquired;
1061 addr += acquired;
1062 nread += acquired;
1063 }
1064
1065 r->bd.addr = addr;
1066 return nread;
1067}
1068
1069static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1070{
1071 AC97BusMasterRegs *r = &s->bm_regs[index];
1072 int stop = 0;
1073
1074 if (s->invalid_freq[index]) {
1075 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1076 index, s->invalid_freq[index]);
1077 return;
1078 }
1079
1080 if (r->sr & SR_DCH) {
1081 if (r->cr & CR_RPBM) {
1082 switch (index) {
1083 case PO_INDEX:
1084 write_bup (s, elapsed);
1085 break;
1086 }
1087 }
1088 return;
1089 }
1090
1091 while ((elapsed >> 1) && !stop) {
1092 int temp;
1093
1094 if (!r->bd_valid) {
1095 dolog ("invalid bd\n");
1096 fetch_bd (s, r);
1097 }
1098
1099 if (!r->picb) {
1100 dolog ("fresh bd %d is empty %#x %#x\n",
1101 r->civ, r->bd.addr, r->bd.ctl_len);
1102 if (r->civ == r->lvi) {
1103 r->sr |= SR_DCH;
1104 s->bup_flag = 0;
1105 break;
1106 }
1107 r->sr &= ~SR_CELV;
1108 r->civ = r->piv;
1109 r->piv = (r->piv + 1) % 32;
1110 fetch_bd (s, r);
1111 return;
1112 }
1113
1114 switch (index) {
1115 case PO_INDEX:
1116 temp = write_audio (s, r, elapsed, &stop);
1117 elapsed -= temp;
1118 r->picb -= (temp >> 1);
1119 break;
1120
1121 case PI_INDEX:
1122 case MC_INDEX:
1123 temp = read_audio (s, r, elapsed, &stop);
1124 elapsed -= temp;
1125 r->picb -= (temp >> 1);
1126 break;
1127 }
1128
1129 if (!r->picb) {
1130 uint32_t new_sr = r->sr & ~SR_CELV;
1131
1132 if (r->bd.ctl_len & BD_IOC) {
1133 new_sr |= SR_BCIS;
1134 }
1135
1136 if (r->civ == r->lvi) {
1137 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1138
1139 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1140 stop = 1;
1141 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1142 }
1143 else {
1144 r->civ = r->piv;
1145 r->piv = (r->piv + 1) % 32;
1146 fetch_bd (s, r);
1147 }
1148
1149 update_sr (s, r, new_sr);
1150 }
1151 }
1152}
1153
1154static void pi_callback (void *opaque, int avail)
1155{
1156 transfer_audio (opaque, PI_INDEX, avail);
1157}
1158
1159static void mc_callback (void *opaque, int avail)
1160{
1161 transfer_audio (opaque, MC_INDEX, avail);
1162}
1163
1164static void po_callback (void *opaque, int free)
1165{
1166 transfer_audio (opaque, PO_INDEX, free);
1167}
1168
1169static const VMStateDescription vmstate_ac97_bm_regs = {
1170 .name = "ac97_bm_regs",
1171 .version_id = 1,
1172 .minimum_version_id = 1,
1173 .fields = (VMStateField[]) {
1174 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs),
1175 VMSTATE_UINT8 (civ, AC97BusMasterRegs),
1176 VMSTATE_UINT8 (lvi, AC97BusMasterRegs),
1177 VMSTATE_UINT16 (sr, AC97BusMasterRegs),
1178 VMSTATE_UINT16 (picb, AC97BusMasterRegs),
1179 VMSTATE_UINT8 (piv, AC97BusMasterRegs),
1180 VMSTATE_UINT8 (cr, AC97BusMasterRegs),
1181 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs),
1182 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs),
1183 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs),
1184 VMSTATE_END_OF_LIST ()
1185 }
1186};
1187
1188static int ac97_post_load (void *opaque, int version_id)
1189{
1190 uint8_t active[LAST_INDEX];
1191 AC97LinkState *s = opaque;
1192
1193 record_select (s, mixer_load (s, AC97_Record_Select));
1194 set_volume (s, AC97_Master_Volume_Mute,
1195 mixer_load (s, AC97_Master_Volume_Mute));
1196 set_volume (s, AC97_PCM_Out_Volume_Mute,
1197 mixer_load (s, AC97_PCM_Out_Volume_Mute));
1198 set_volume (s, AC97_Record_Gain_Mute,
1199 mixer_load (s, AC97_Record_Gain_Mute));
1200
1201 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1202 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1203 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1204 reset_voices (s, active);
1205
1206 s->bup_flag = 0;
1207 s->last_samp = 0;
1208 return 0;
1209}
1210
1211static bool is_version_2 (void *opaque, int version_id)
1212{
1213 return version_id == 2;
1214}
1215
1216static const VMStateDescription vmstate_ac97 = {
1217 .name = "ac97",
1218 .version_id = 3,
1219 .minimum_version_id = 2,
1220 .post_load = ac97_post_load,
1221 .fields = (VMStateField[]) {
1222 VMSTATE_PCI_DEVICE (dev, AC97LinkState),
1223 VMSTATE_UINT32 (glob_cnt, AC97LinkState),
1224 VMSTATE_UINT32 (glob_sta, AC97LinkState),
1225 VMSTATE_UINT32 (cas, AC97LinkState),
1226 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1,
1227 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1228 VMSTATE_BUFFER (mixer_data, AC97LinkState),
1229 VMSTATE_UNUSED_TEST (is_version_2, 3),
1230 VMSTATE_END_OF_LIST ()
1231 }
1232};
1233
1234static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size)
1235{
1236 if ((addr / size) > 256) {
1237 return -1;
1238 }
1239
1240 switch (size) {
1241 case 1:
1242 return nam_readb(opaque, addr);
1243 case 2:
1244 return nam_readw(opaque, addr);
1245 case 4:
1246 return nam_readl(opaque, addr);
1247 default:
1248 return -1;
1249 }
1250}
1251
1252static void nam_write(void *opaque, hwaddr addr, uint64_t val,
1253 unsigned size)
1254{
1255 if ((addr / size) > 256) {
1256 return;
1257 }
1258
1259 switch (size) {
1260 case 1:
1261 nam_writeb(opaque, addr, val);
1262 break;
1263 case 2:
1264 nam_writew(opaque, addr, val);
1265 break;
1266 case 4:
1267 nam_writel(opaque, addr, val);
1268 break;
1269 }
1270}
1271
1272static const MemoryRegionOps ac97_io_nam_ops = {
1273 .read = nam_read,
1274 .write = nam_write,
1275 .impl = {
1276 .min_access_size = 1,
1277 .max_access_size = 4,
1278 },
1279 .endianness = DEVICE_LITTLE_ENDIAN,
1280};
1281
1282static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size)
1283{
1284 if ((addr / size) > 64) {
1285 return -1;
1286 }
1287
1288 switch (size) {
1289 case 1:
1290 return nabm_readb(opaque, addr);
1291 case 2:
1292 return nabm_readw(opaque, addr);
1293 case 4:
1294 return nabm_readl(opaque, addr);
1295 default:
1296 return -1;
1297 }
1298}
1299
1300static void nabm_write(void *opaque, hwaddr addr, uint64_t val,
1301 unsigned size)
1302{
1303 if ((addr / size) > 64) {
1304 return;
1305 }
1306
1307 switch (size) {
1308 case 1:
1309 nabm_writeb(opaque, addr, val);
1310 break;
1311 case 2:
1312 nabm_writew(opaque, addr, val);
1313 break;
1314 case 4:
1315 nabm_writel(opaque, addr, val);
1316 break;
1317 }
1318}
1319
1320
1321static const MemoryRegionOps ac97_io_nabm_ops = {
1322 .read = nabm_read,
1323 .write = nabm_write,
1324 .impl = {
1325 .min_access_size = 1,
1326 .max_access_size = 4,
1327 },
1328 .endianness = DEVICE_LITTLE_ENDIAN,
1329};
1330
1331static void ac97_on_reset (DeviceState *dev)
1332{
1333 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
1334
1335 reset_bm_regs (s, &s->bm_regs[0]);
1336 reset_bm_regs (s, &s->bm_regs[1]);
1337 reset_bm_regs (s, &s->bm_regs[2]);
1338
1339
1340
1341
1342
1343
1344 mixer_reset (s);
1345}
1346
1347static void ac97_realize(PCIDevice *dev, Error **errp)
1348{
1349 AC97LinkState *s = AC97(dev);
1350 uint8_t *c = s->dev.config;
1351
1352
1353 c[PCI_COMMAND] = 0x00;
1354 c[PCI_COMMAND + 1] = 0x00;
1355
1356
1357 c[PCI_STATUS] = PCI_STATUS_FAST_BACK;
1358 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1359
1360 c[PCI_CLASS_PROG] = 0x00;
1361
1362
1363
1364 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1365 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1366 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1367 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1368
1369
1370
1371 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1372 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1373 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1374 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1375
1376 if (s->use_broken_id) {
1377 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
1378 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1379 c[PCI_SUBSYSTEM_ID] = 0x00;
1380 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1381 }
1382
1383 c[PCI_INTERRUPT_LINE] = 0x00;
1384 c[PCI_INTERRUPT_PIN] = 0x01;
1385
1386 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
1387 "ac97-nam", 1024);
1388 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
1389 "ac97-nabm", 256);
1390 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1391 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1392 AUD_register_card ("ac97", &s->card);
1393 ac97_on_reset(DEVICE(s));
1394}
1395
1396static void ac97_exit(PCIDevice *dev)
1397{
1398 AC97LinkState *s = AC97(dev);
1399
1400 AUD_close_in(&s->card, s->voice_pi);
1401 AUD_close_out(&s->card, s->voice_po);
1402 AUD_close_in(&s->card, s->voice_mc);
1403 AUD_remove_card(&s->card);
1404}
1405
1406static int ac97_init (PCIBus *bus)
1407{
1408 pci_create_simple(bus, -1, TYPE_AC97);
1409 return 0;
1410}
1411
1412static Property ac97_properties[] = {
1413 DEFINE_AUDIO_PROPERTIES(AC97LinkState, card),
1414 DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0),
1415 DEFINE_PROP_END_OF_LIST (),
1416};
1417
1418static void ac97_class_init (ObjectClass *klass, void *data)
1419{
1420 DeviceClass *dc = DEVICE_CLASS (klass);
1421 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
1422
1423 k->realize = ac97_realize;
1424 k->exit = ac97_exit;
1425 k->vendor_id = PCI_VENDOR_ID_INTEL;
1426 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
1427 k->revision = 0x01;
1428 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1429 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1430 dc->desc = "Intel 82801AA AC97 Audio";
1431 dc->vmsd = &vmstate_ac97;
1432 dc->props = ac97_properties;
1433 dc->reset = ac97_on_reset;
1434}
1435
1436static const TypeInfo ac97_info = {
1437 .name = TYPE_AC97,
1438 .parent = TYPE_PCI_DEVICE,
1439 .instance_size = sizeof (AC97LinkState),
1440 .class_init = ac97_class_init,
1441 .interfaces = (InterfaceInfo[]) {
1442 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1443 { },
1444 },
1445};
1446
1447static void ac97_register_types (void)
1448{
1449 type_register_static (&ac97_info);
1450 pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init);
1451}
1452
1453type_init (ac97_register_types)
1454
