LXR qemu/hw/char/imx

   1/*
   2 * IMX31 UARTS
   3 *
   4 * Copyright (c) 2008 OKL
   5 * Originally Written by Hans Jiang
   6 * Copyright (c) 2011 NICTA Pty Ltd.
   7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 *
  12 * This is a `bare-bones' implementation of the IMX series serial ports.
  13 * TODO:
  14 *  -- implement FIFOs.  The real hardware has 32 word transmit
  15 *                       and receive FIFOs; we currently use a 1-char buffer
  16 *  -- implement DMA
  17 *  -- implement BAUD-rate and modem lines, for when the backend
  18 *     is a real serial device.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/char/imx_serial.h"
  23#include "hw/irq.h"
  24#include "hw/qdev-properties.h"
  25#include "migration/vmstate.h"
  26#include "qemu/log.h"
  27#include "qemu/module.h"
  28
  29#ifndef DEBUG_IMX_UART
  30#define DEBUG_IMX_UART 0
  31#endif
  32
  33#define DPRINTF(fmt, args...) \
  34    do { \
  35        if (DEBUG_IMX_UART) { \
  36            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
  37                                             __func__, ##args); \
  38        } \
  39    } while (0)
  40
  41static const VMStateDescription vmstate_imx_serial = {
  42    .name = TYPE_IMX_SERIAL,
  43    .version_id = 2,
  44    .minimum_version_id = 2,
  45    .fields = (VMStateField[]) {
  46        VMSTATE_INT32(readbuff, IMXSerialState),
  47        VMSTATE_UINT32(usr1, IMXSerialState),
  48        VMSTATE_UINT32(usr2, IMXSerialState),
  49        VMSTATE_UINT32(ucr1, IMXSerialState),
  50        VMSTATE_UINT32(uts1, IMXSerialState),
  51        VMSTATE_UINT32(onems, IMXSerialState),
  52        VMSTATE_UINT32(ufcr, IMXSerialState),
  53        VMSTATE_UINT32(ubmr, IMXSerialState),
  54        VMSTATE_UINT32(ubrc, IMXSerialState),
  55        VMSTATE_UINT32(ucr3, IMXSerialState),
  56        VMSTATE_UINT32(ucr4, IMXSerialState),
  57        VMSTATE_END_OF_LIST()
  58    },
  59};
  60
  61static void imx_update(IMXSerialState *s)
  62{
  63    uint32_t usr1;
  64    uint32_t usr2;
  65    uint32_t mask;
  66
  67    /*
  68     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
  69     * UCR1, so we can get away with something as simple as the
  70     * following:
  71     */
  72    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
  73    /*
  74     * Bits that we want in USR2 are not as conveniently laid out,
  75     * unfortunately.
  76     */
  77    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
  78    /*
  79     * TCEN and TXDC are both bit 3
  80     * RDR and DREN are both bit 0
  81     */
  82    mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
  83
  84    usr2 = s->usr2 & mask;
  85
  86    qemu_set_irq(s->irq, usr1 || usr2);
  87}
  88
  89static void imx_serial_reset(IMXSerialState *s)
  90{
  91
  92    s->usr1 = USR1_TRDY | USR1_RXDS;
  93    /*
  94     * Fake attachment of a terminal: assert RTS.
  95     */
  96    s->usr1 |= USR1_RTSS;
  97    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
  98    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
  99    s->ucr1 = 0;
 100    s->ucr2 = UCR2_SRST;
 101    s->ucr3 = 0x700;
 102    s->ubmr = 0;
 103    s->ubrc = 4;
 104    s->readbuff = URXD_ERR;
 105}
 106
 107static void imx_serial_reset_at_boot(DeviceState *dev)
 108{
 109    IMXSerialState *s = IMX_SERIAL(dev);
 110
 111    imx_serial_reset(s);
 112
 113    /*
 114     * enable the uart on boot, so messages from the linux decompresser
 115     * are visible.  On real hardware this is done by the boot rom
 116     * before anything else is loaded.
 117     */
 118    s->ucr1 = UCR1_UARTEN;
 119    s->ucr2 = UCR2_TXEN;
 120
 121}
 122
 123static uint64_t imx_serial_read(void *opaque, hwaddr offset,
 124                                unsigned size)
 125{
 126    IMXSerialState *s = (IMXSerialState *)opaque;
 127    uint32_t c;
 128
 129    DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
 130
 131    switch (offset >> 2) {
 132    case 0x0: /* URXD */
 133        c = s->readbuff;
 134        if (!(s->uts1 & UTS1_RXEMPTY)) {
 135            /* Character is valid */
 136            c |= URXD_CHARRDY;
 137            s->usr1 &= ~USR1_RRDY;
 138            s->usr2 &= ~USR2_RDR;
 139            s->uts1 |= UTS1_RXEMPTY;
 140            imx_update(s);
 141            qemu_chr_fe_accept_input(&s->chr);
 142        }
 143        return c;
 144
 145    case 0x20: /* UCR1 */
 146        return s->ucr1;
 147
 148    case 0x21: /* UCR2 */
 149        return s->ucr2;
 150
 151    case 0x25: /* USR1 */
 152        return s->usr1;
 153
 154    case 0x26: /* USR2 */
 155        return s->usr2;
 156
 157    case 0x2A: /* BRM Modulator */
 158        return s->ubmr;
 159
 160    case 0x2B: /* Baud Rate Count */
 161        return s->ubrc;
 162
 163    case 0x2d: /* Test register */
 164        return s->uts1;
 165
 166    case 0x24: /* UFCR */
 167        return s->ufcr;
 168
 169    case 0x2c:
 170        return s->onems;
 171
 172    case 0x22: /* UCR3 */
 173        return s->ucr3;
 174
 175    case 0x23: /* UCR4 */
 176        return s->ucr4;
 177
 178    case 0x29: /* BRM Incremental */
 179        return 0x0; /* TODO */
 180
 181    default:
 182        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 183                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 184        return 0;
 185    }
 186}
 187
 188static void imx_serial_write(void *opaque, hwaddr offset,
 189                             uint64_t value, unsigned size)
 190{
 191    IMXSerialState *s = (IMXSerialState *)opaque;
 192    Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
 193    unsigned char ch;
 194
 195    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
 196            offset, (unsigned int)value, chr ? chr->label : "NODEV");
 197
 198    switch (offset >> 2) {
 199    case 0x10: /* UTXD */
 200        ch = value;
 201        if (s->ucr2 & UCR2_TXEN) {
 202            /* XXX this blocks entire thread. Rewrite to use
 203             * qemu_chr_fe_write and background I/O callbacks */
 204            qemu_chr_fe_write_all(&s->chr, &ch, 1);
 205            s->usr1 &= ~USR1_TRDY;
 206            s->usr2 &= ~USR2_TXDC;
 207            imx_update(s);
 208            s->usr1 |= USR1_TRDY;
 209            s->usr2 |= USR2_TXDC;
 210            imx_update(s);
 211        }
 212        break;
 213
 214    case 0x20: /* UCR1 */
 215        s->ucr1 = value & 0xffff;
 216
 217        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
 218
 219        imx_update(s);
 220        break;
 221
 222    case 0x21: /* UCR2 */
 223        /*
 224         * Only a few bits in control register 2 are implemented as yet.
 225         * If it's intended to use a real serial device as a back-end, this
 226         * register will have to be implemented more fully.
 227         */
 228        if (!(value & UCR2_SRST)) {
 229            imx_serial_reset(s);
 230            imx_update(s);
 231            value |= UCR2_SRST;
 232        }
 233        if (value & UCR2_RXEN) {
 234            if (!(s->ucr2 & UCR2_RXEN)) {
 235                qemu_chr_fe_accept_input(&s->chr);
 236            }
 237        }
 238        s->ucr2 = value & 0xffff;
 239        break;
 240
 241    case 0x25: /* USR1 */
 242        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
 243                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
 244        s->usr1 &= ~value;
 245        break;
 246
 247    case 0x26: /* USR2 */
 248        /*
 249         * Writing 1 to some bits clears them; all other
 250         * values are ignored
 251         */
 252        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
 253                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |
 254                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
 255        s->usr2 &= ~value;
 256        break;
 257
 258    /*
 259     * Linux expects to see what it writes to these registers
 260     * We don't currently alter the baud rate
 261     */
 262    case 0x29: /* UBIR */
 263        s->ubrc = value & 0xffff;
 264        break;
 265
 266    case 0x2a: /* UBMR */
 267        s->ubmr = value & 0xffff;
 268        break;
 269
 270    case 0x2c: /* One ms reg */
 271        s->onems = value & 0xffff;
 272        break;
 273
 274    case 0x24: /* FIFO control register */
 275        s->ufcr = value & 0xffff;
 276        break;
 277
 278    case 0x22: /* UCR3 */
 279        s->ucr3 = value & 0xffff;
 280        break;
 281
 282    case 0x23: /* UCR4 */
 283        s->ucr4 = value & 0xffff;
 284        imx_update(s);
 285        break;
 286
 287    case 0x2d: /* UTS1 */
 288        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
 289                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 290        /* TODO */
 291        break;
 292
 293    default:
 294        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 295                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 296    }
 297}
 298
 299static int imx_can_receive(void *opaque)
 300{
 301    IMXSerialState *s = (IMXSerialState *)opaque;
 302    return !(s->usr1 & USR1_RRDY);
 303}
 304
 305static void imx_put_data(void *opaque, uint32_t value)
 306{
 307    IMXSerialState *s = (IMXSerialState *)opaque;
 308
 309    DPRINTF("received char\n");
 310
 311    s->usr1 |= USR1_RRDY;
 312    s->usr2 |= USR2_RDR;
 313    s->uts1 &= ~UTS1_RXEMPTY;
 314    s->readbuff = value;
 315    if (value & URXD_BRK) {
 316        s->usr2 |= USR2_BRCD;
 317    }
 318    imx_update(s);
 319}
 320
 321static void imx_receive(void *opaque, const uint8_t *buf, int size)
 322{
 323    imx_put_data(opaque, *buf);
 324}
 325
 326static void imx_event(void *opaque, int event)
 327{
 328    if (event == CHR_EVENT_BREAK) {
 329        imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR);
 330    }
 331}
 332
 333
 334static const struct MemoryRegionOps imx_serial_ops = {
 335    .read = imx_serial_read,
 336    .write = imx_serial_write,
 337    .endianness = DEVICE_NATIVE_ENDIAN,
 338};
 339
 340static void imx_serial_realize(DeviceState *dev, Error **errp)
 341{
 342    IMXSerialState *s = IMX_SERIAL(dev);
 343
 344    DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
 345
 346    qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
 347                             imx_event, NULL, s, NULL, true);
 348}
 349
 350static void imx_serial_init(Object *obj)
 351{
 352    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 353    IMXSerialState *s = IMX_SERIAL(obj);
 354
 355    memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
 356                          TYPE_IMX_SERIAL, 0x1000);
 357    sysbus_init_mmio(sbd, &s->iomem);
 358    sysbus_init_irq(sbd, &s->irq);
 359}
 360
 361static Property imx_serial_properties[] = {
 362    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
 363    DEFINE_PROP_END_OF_LIST(),
 364};
 365
 366static void imx_serial_class_init(ObjectClass *klass, void *data)
 367{
 368    DeviceClass *dc = DEVICE_CLASS(klass);
 369
 370    dc->realize = imx_serial_realize;
 371    dc->vmsd = &vmstate_imx_serial;
 372    dc->reset = imx_serial_reset_at_boot;
 373    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 374    dc->desc = "i.MX series UART";
 375    dc->props = imx_serial_properties;
 376}
 377
 378static const TypeInfo imx_serial_info = {
 379    .name           = TYPE_IMX_SERIAL,
 380    .parent         = TYPE_SYS_BUS_DEVICE,
 381    .instance_size  = sizeof(IMXSerialState),
 382    .instance_init  = imx_serial_init,
 383    .class_init     = imx_serial_class_init,
 384};
 385
 386static void imx_serial_register_types(void)
 387{
 388    type_register_static(&imx_serial_info);
 389}
 390
 391type_init(imx_serial_register_types)
 392