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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/irq.h"
28#include "hw/qdev-properties.h"
29#include "hw/sysbus.h"
30#include "qemu/module.h"
31#include "chardev/char-fe.h"
32
33#define DUART(x)
34
35#define R_RX 0
36#define R_TX 1
37#define R_STATUS 2
38#define R_CTRL 3
39#define R_MAX 4
40
41#define STATUS_RXVALID 0x01
42#define STATUS_RXFULL 0x02
43#define STATUS_TXEMPTY 0x04
44#define STATUS_TXFULL 0x08
45#define STATUS_IE 0x10
46#define STATUS_OVERRUN 0x20
47#define STATUS_FRAME 0x40
48#define STATUS_PARITY 0x80
49
50#define CONTROL_RST_TX 0x01
51#define CONTROL_RST_RX 0x02
52#define CONTROL_IE 0x10
53
54#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
55#define XILINX_UARTLITE(obj) \
56 OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)
57
58typedef struct XilinxUARTLite {
59 SysBusDevice parent_obj;
60
61 MemoryRegion mmio;
62 CharBackend chr;
63 qemu_irq irq;
64
65 uint8_t rx_fifo[8];
66 unsigned int rx_fifo_pos;
67 unsigned int rx_fifo_len;
68
69 uint32_t regs[R_MAX];
70} XilinxUARTLite;
71
72static void uart_update_irq(XilinxUARTLite *s)
73{
74 unsigned int irq;
75
76 if (s->rx_fifo_len)
77 s->regs[R_STATUS] |= STATUS_IE;
78
79 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
80 qemu_set_irq(s->irq, irq);
81}
82
83static void uart_update_status(XilinxUARTLite *s)
84{
85 uint32_t r;
86
87 r = s->regs[R_STATUS];
88 r &= ~7;
89 r |= 1 << 2;
90 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
91 r |= (!!s->rx_fifo_len);
92 s->regs[R_STATUS] = r;
93}
94
95static void xilinx_uartlite_reset(DeviceState *dev)
96{
97 uart_update_status(XILINX_UARTLITE(dev));
98}
99
100static uint64_t
101uart_read(void *opaque, hwaddr addr, unsigned int size)
102{
103 XilinxUARTLite *s = opaque;
104 uint32_t r = 0;
105 addr >>= 2;
106 switch (addr)
107 {
108 case R_RX:
109 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
110 if (s->rx_fifo_len)
111 s->rx_fifo_len--;
112 uart_update_status(s);
113 uart_update_irq(s);
114 qemu_chr_fe_accept_input(&s->chr);
115 break;
116
117 default:
118 if (addr < ARRAY_SIZE(s->regs))
119 r = s->regs[addr];
120 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
121 break;
122 }
123 return r;
124}
125
126static void
127uart_write(void *opaque, hwaddr addr,
128 uint64_t val64, unsigned int size)
129{
130 XilinxUARTLite *s = opaque;
131 uint32_t value = val64;
132 unsigned char ch = value;
133
134 addr >>= 2;
135 switch (addr)
136 {
137 case R_STATUS:
138 hw_error("write to UART STATUS?\n");
139 break;
140
141 case R_CTRL:
142 if (value & CONTROL_RST_RX) {
143 s->rx_fifo_pos = 0;
144 s->rx_fifo_len = 0;
145 }
146 s->regs[addr] = value;
147 break;
148
149 case R_TX:
150
151
152 qemu_chr_fe_write_all(&s->chr, &ch, 1);
153 s->regs[addr] = value;
154
155
156 s->regs[R_STATUS] |= STATUS_IE;
157 break;
158
159 default:
160 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
161 if (addr < ARRAY_SIZE(s->regs))
162 s->regs[addr] = value;
163 break;
164 }
165 uart_update_status(s);
166 uart_update_irq(s);
167}
168
169static const MemoryRegionOps uart_ops = {
170 .read = uart_read,
171 .write = uart_write,
172 .endianness = DEVICE_NATIVE_ENDIAN,
173 .valid = {
174 .min_access_size = 1,
175 .max_access_size = 4
176 }
177};
178
179static Property xilinx_uartlite_properties[] = {
180 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
181 DEFINE_PROP_END_OF_LIST(),
182};
183
184static void uart_rx(void *opaque, const uint8_t *buf, int size)
185{
186 XilinxUARTLite *s = opaque;
187
188
189 if (s->rx_fifo_len >= 8) {
190 printf("WARNING: UART dropped char.\n");
191 return;
192 }
193 s->rx_fifo[s->rx_fifo_pos] = *buf;
194 s->rx_fifo_pos++;
195 s->rx_fifo_pos &= 0x7;
196 s->rx_fifo_len++;
197
198 uart_update_status(s);
199 uart_update_irq(s);
200}
201
202static int uart_can_rx(void *opaque)
203{
204 XilinxUARTLite *s = opaque;
205
206 return s->rx_fifo_len < sizeof(s->rx_fifo);
207}
208
209static void uart_event(void *opaque, int event)
210{
211
212}
213
214static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
215{
216 XilinxUARTLite *s = XILINX_UARTLITE(dev);
217
218 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
219 uart_event, NULL, s, NULL, true);
220}
221
222static void xilinx_uartlite_init(Object *obj)
223{
224 XilinxUARTLite *s = XILINX_UARTLITE(obj);
225
226 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
227
228 memory_region_init_io(&s->mmio, obj, &uart_ops, s,
229 "xlnx.xps-uartlite", R_MAX * 4);
230 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
231}
232
233static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
234{
235 DeviceClass *dc = DEVICE_CLASS(klass);
236
237 dc->reset = xilinx_uartlite_reset;
238 dc->realize = xilinx_uartlite_realize;
239 dc->props = xilinx_uartlite_properties;
240}
241
242static const TypeInfo xilinx_uartlite_info = {
243 .name = TYPE_XILINX_UARTLITE,
244 .parent = TYPE_SYS_BUS_DEVICE,
245 .instance_size = sizeof(XilinxUARTLite),
246 .instance_init = xilinx_uartlite_init,
247 .class_init = xilinx_uartlite_class_init,
248};
249
250static void xilinx_uart_register_types(void)
251{
252 type_register_static(&xilinx_uartlite_info);
253}
254
255type_init(xilinx_uart_register_types)
256
