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21#include "qemu/osdep.h"
22#include "qemu/units.h"
23#include <zlib.h>
24
25#include "qapi/error.h"
26#include "qemu/timer.h"
27#include "qemu/queue.h"
28#include "qemu/atomic.h"
29#include "qemu/main-loop.h"
30#include "qemu/module.h"
31#include "hw/qdev-properties.h"
32#include "sysemu/runstate.h"
33#include "migration/blocker.h"
34#include "migration/vmstate.h"
35#include "trace.h"
36
37#include "qxl.h"
38
39#undef SPICE_RING_CONS_ITEM
40#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
41 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
42 if (cons >= ARRAY_SIZE((r)->items)) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
44 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
45 ret = NULL; \
46 } else { \
47 ret = &(r)->items[cons].el; \
48 } \
49 }
50
51#undef ALIGN
52#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
53
54#define PIXEL_SIZE 0.2936875
55
56#define QXL_MODE(_x, _y, _b, _o) \
57 { .x_res = _x, \
58 .y_res = _y, \
59 .bits = _b, \
60 .stride = (_x) * (_b) / 8, \
61 .x_mili = PIXEL_SIZE * (_x), \
62 .y_mili = PIXEL_SIZE * (_y), \
63 .orientation = _o, \
64 }
65
66#define QXL_MODE_16_32(x_res, y_res, orientation) \
67 QXL_MODE(x_res, y_res, 16, orientation), \
68 QXL_MODE(x_res, y_res, 32, orientation)
69
70#define QXL_MODE_EX(x_res, y_res) \
71 QXL_MODE_16_32(x_res, y_res, 0), \
72 QXL_MODE_16_32(x_res, y_res, 1)
73
74static QXLMode qxl_modes[] = {
75 QXL_MODE_EX(640, 480),
76 QXL_MODE_EX(800, 480),
77 QXL_MODE_EX(800, 600),
78 QXL_MODE_EX(832, 624),
79 QXL_MODE_EX(960, 640),
80 QXL_MODE_EX(1024, 600),
81 QXL_MODE_EX(1024, 768),
82 QXL_MODE_EX(1152, 864),
83 QXL_MODE_EX(1152, 870),
84 QXL_MODE_EX(1280, 720),
85 QXL_MODE_EX(1280, 760),
86 QXL_MODE_EX(1280, 768),
87 QXL_MODE_EX(1280, 800),
88 QXL_MODE_EX(1280, 960),
89 QXL_MODE_EX(1280, 1024),
90 QXL_MODE_EX(1360, 768),
91 QXL_MODE_EX(1366, 768),
92 QXL_MODE_EX(1400, 1050),
93 QXL_MODE_EX(1440, 900),
94 QXL_MODE_EX(1600, 900),
95 QXL_MODE_EX(1600, 1200),
96 QXL_MODE_EX(1680, 1050),
97 QXL_MODE_EX(1920, 1080),
98
99 QXL_MODE_EX(1920, 1200),
100 QXL_MODE_EX(1920, 1440),
101 QXL_MODE_EX(2000, 2000),
102 QXL_MODE_EX(2048, 1536),
103 QXL_MODE_EX(2048, 2048),
104 QXL_MODE_EX(2560, 1440),
105 QXL_MODE_EX(2560, 1600),
106
107 QXL_MODE_EX(2560, 2048),
108 QXL_MODE_EX(2800, 2100),
109 QXL_MODE_EX(3200, 2400),
110
111 QXL_MODE_EX(3840, 2160),
112 QXL_MODE_EX(4096, 2160),
113
114 QXL_MODE_EX(7680, 4320),
115
116 QXL_MODE_EX(8192, 4320),
117};
118
119static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
120static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
121static void qxl_reset_memslots(PCIQXLDevice *d);
122static void qxl_reset_surfaces(PCIQXLDevice *d);
123static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
124
125static void qxl_hw_update(void *opaque);
126
127void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
128{
129 trace_qxl_set_guest_bug(qxl->id);
130 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
131 qxl->guest_bug = 1;
132 if (qxl->guestdebug) {
133 va_list ap;
134 va_start(ap, msg);
135 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
136 vfprintf(stderr, msg, ap);
137 fprintf(stderr, "\n");
138 va_end(ap);
139 }
140}
141
142static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
143{
144 qxl->guest_bug = 0;
145}
146
147void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
148 struct QXLRect *area, struct QXLRect *dirty_rects,
149 uint32_t num_dirty_rects,
150 uint32_t clear_dirty_region,
151 qxl_async_io async, struct QXLCookie *cookie)
152{
153 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
154 area->top, area->bottom);
155 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
156 clear_dirty_region);
157 if (async == QXL_SYNC) {
158 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
159 dirty_rects, num_dirty_rects, clear_dirty_region);
160 } else {
161 assert(cookie != NULL);
162 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
163 clear_dirty_region, (uintptr_t)cookie);
164 }
165}
166
167static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
168 uint32_t id)
169{
170 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
171 qemu_mutex_lock(&qxl->track_lock);
172 qxl->guest_surfaces.cmds[id] = 0;
173 qxl->guest_surfaces.count--;
174 qemu_mutex_unlock(&qxl->track_lock);
175}
176
177static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
178 qxl_async_io async)
179{
180 QXLCookie *cookie;
181
182 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
183 if (async) {
184 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
185 QXL_IO_DESTROY_SURFACE_ASYNC);
186 cookie->u.surface_id = id;
187 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
188 } else {
189 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
190 qxl_spice_destroy_surface_wait_complete(qxl, id);
191 }
192}
193
194static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
195{
196 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
197 qxl->num_free_res);
198 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
199 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_FLUSH_SURFACES_ASYNC));
201}
202
203void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
204 uint32_t count)
205{
206 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
207 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
208}
209
210void qxl_spice_oom(PCIQXLDevice *qxl)
211{
212 trace_qxl_spice_oom(qxl->id);
213 spice_qxl_oom(&qxl->ssd.qxl);
214}
215
216void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
217{
218 trace_qxl_spice_reset_memslots(qxl->id);
219 spice_qxl_reset_memslots(&qxl->ssd.qxl);
220}
221
222static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
223{
224 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
225 qemu_mutex_lock(&qxl->track_lock);
226 memset(qxl->guest_surfaces.cmds, 0,
227 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
228 qxl->guest_surfaces.count = 0;
229 qemu_mutex_unlock(&qxl->track_lock);
230}
231
232static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
233{
234 trace_qxl_spice_destroy_surfaces(qxl->id, async);
235 if (async) {
236 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
237 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
238 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
239 } else {
240 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
241 qxl_spice_destroy_surfaces_complete(qxl);
242 }
243}
244
245static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
246{
247 QXLMonitorsConfig *cfg;
248
249 trace_qxl_spice_monitors_config(qxl->id);
250 if (replay) {
251
252
253
254
255
256
257 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
258 qxl->guest_monitors_config,
259 MEMSLOT_GROUP_GUEST,
260 (uintptr_t)qxl_cookie_new(
261 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
262 0));
263 } else {
264
265#if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
266 if (qxl->max_outputs) {
267 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
268 }
269#endif
270 qxl->guest_monitors_config = qxl->ram->monitors_config;
271 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
272 qxl->ram->monitors_config,
273 MEMSLOT_GROUP_GUEST,
274 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
275 QXL_IO_MONITORS_CONFIG_ASYNC));
276 }
277
278 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
279 if (cfg != NULL && cfg->count == 1) {
280 qxl->guest_primary.resized = 1;
281 qxl->guest_head0_width = cfg->heads[0].width;
282 qxl->guest_head0_height = cfg->heads[0].height;
283 } else {
284 qxl->guest_head0_width = 0;
285 qxl->guest_head0_height = 0;
286 }
287}
288
289void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
290{
291 trace_qxl_spice_reset_image_cache(qxl->id);
292 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
293}
294
295void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
296{
297 trace_qxl_spice_reset_cursor(qxl->id);
298 spice_qxl_reset_cursor(&qxl->ssd.qxl);
299 qemu_mutex_lock(&qxl->track_lock);
300 qxl->guest_cursor = 0;
301 qemu_mutex_unlock(&qxl->track_lock);
302 if (qxl->ssd.cursor) {
303 cursor_put(qxl->ssd.cursor);
304 }
305 qxl->ssd.cursor = cursor_builtin_hidden();
306}
307
308static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
309{
310
311
312
313
314
315 return crc32(0xffffffff, p, len) ^ 0xffffffff;
316}
317
318static ram_addr_t qxl_rom_size(void)
319{
320#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
321#define QXL_ROM_SZ 8192
322
323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
324 return QXL_ROM_SZ;
325}
326
327static void init_qxl_rom(PCIQXLDevice *d)
328{
329 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
330 QXLModes *modes = (QXLModes *)(rom + 1);
331 uint32_t ram_header_size;
332 uint32_t surface0_area_size;
333 uint32_t num_pages;
334 uint32_t fb;
335 int i, n;
336
337 memset(rom, 0, d->rom_size);
338
339 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
340 rom->id = cpu_to_le32(d->id);
341 rom->log_level = cpu_to_le32(d->guestdebug);
342 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
343
344 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
345 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
346 rom->slots_start = 1;
347 rom->slots_end = NUM_MEMSLOTS - 1;
348 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
349
350 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
351 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
352 if (fb > d->vgamem_size) {
353 continue;
354 }
355 modes->modes[n].id = cpu_to_le32(i);
356 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
357 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
358 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
359 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
360 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
361 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
362 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
363 n++;
364 }
365 modes->n_modes = cpu_to_le32(n);
366
367 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
368 surface0_area_size = ALIGN(d->vgamem_size, 4096);
369 num_pages = d->vga.vram_size;
370 num_pages -= ram_header_size;
371 num_pages -= surface0_area_size;
372 num_pages = num_pages / QXL_PAGE_SIZE;
373
374 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
375
376 rom->draw_area_offset = cpu_to_le32(0);
377 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
378 rom->pages_offset = cpu_to_le32(surface0_area_size);
379 rom->num_pages = cpu_to_le32(num_pages);
380 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
381
382 if (d->xres && d->yres) {
383
384 rom->client_monitors_config.count = 1;
385 rom->client_monitors_config.heads[0].left = 0;
386 rom->client_monitors_config.heads[0].top = 0;
387 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
388 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
389 rom->client_monitors_config_crc = qxl_crc32(
390 (const uint8_t *)&rom->client_monitors_config,
391 sizeof(rom->client_monitors_config));
392 }
393
394 d->shadow_rom = *rom;
395 d->rom = rom;
396 d->modes = modes;
397}
398
399static void init_qxl_ram(PCIQXLDevice *d)
400{
401 uint8_t *buf;
402 uint32_t prod;
403 QXLReleaseRing *ring;
404
405 buf = d->vga.vram_ptr;
406 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
407 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
408 d->ram->int_pending = cpu_to_le32(0);
409 d->ram->int_mask = cpu_to_le32(0);
410 d->ram->update_surface = 0;
411 d->ram->monitors_config = 0;
412 SPICE_RING_INIT(&d->ram->cmd_ring);
413 SPICE_RING_INIT(&d->ram->cursor_ring);
414 SPICE_RING_INIT(&d->ram->release_ring);
415
416 ring = &d->ram->release_ring;
417 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
418 assert(prod < ARRAY_SIZE(ring->items));
419 ring->items[prod].el = 0;
420
421 qxl_ring_set_dirty(d);
422}
423
424
425static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
426{
427 memory_region_set_dirty(mr, addr, end - addr);
428}
429
430static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
431{
432 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
433}
434
435
436static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
437{
438 void *base = qxl->vga.vram_ptr;
439 intptr_t offset;
440
441 offset = ptr - base;
442 assert(offset < qxl->vga.vram_size);
443 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
444}
445
446
447static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
448{
449 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
450 ram_addr_t end = qxl->vga.vram_size;
451 qxl_set_dirty(&qxl->vga.vram, addr, end);
452}
453
454
455
456
457
458static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
459{
460 switch (le32_to_cpu(ext->cmd.type)) {
461 case QXL_CMD_SURFACE:
462 {
463 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
464
465 if (!cmd) {
466 return 1;
467 }
468 uint32_t id = le32_to_cpu(cmd->surface_id);
469
470 if (id >= qxl->ssd.num_surfaces) {
471 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
472 qxl->ssd.num_surfaces);
473 return 1;
474 }
475 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
476 (cmd->u.surface_create.stride & 0x03) != 0) {
477 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
478 cmd->u.surface_create.stride);
479 return 1;
480 }
481 qemu_mutex_lock(&qxl->track_lock);
482 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
483 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
484 qxl->guest_surfaces.count++;
485 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
486 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
487 }
488 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
489 qxl->guest_surfaces.cmds[id] = 0;
490 qxl->guest_surfaces.count--;
491 }
492 qemu_mutex_unlock(&qxl->track_lock);
493 break;
494 }
495 case QXL_CMD_CURSOR:
496 {
497 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
498
499 if (!cmd) {
500 return 1;
501 }
502 if (cmd->type == QXL_CURSOR_SET) {
503 qemu_mutex_lock(&qxl->track_lock);
504 qxl->guest_cursor = ext->cmd.data;
505 qemu_mutex_unlock(&qxl->track_lock);
506 }
507 if (cmd->type == QXL_CURSOR_HIDE) {
508 qemu_mutex_lock(&qxl->track_lock);
509 qxl->guest_cursor = 0;
510 qemu_mutex_unlock(&qxl->track_lock);
511 }
512 break;
513 }
514 }
515 return 0;
516}
517
518
519
520static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
521{
522 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
523
524 trace_qxl_interface_attach_worker(qxl->id);
525}
526
527static void interface_set_compression_level(QXLInstance *sin, int level)
528{
529 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
530
531 trace_qxl_interface_set_compression_level(qxl->id, level);
532 qxl->shadow_rom.compression_level = cpu_to_le32(level);
533 qxl->rom->compression_level = cpu_to_le32(level);
534 qxl_rom_set_dirty(qxl);
535}
536
537#if SPICE_NEEDS_SET_MM_TIME
538static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
539{
540 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
541
542 if (!qemu_spice_display_is_running(&qxl->ssd)) {
543 return;
544 }
545
546 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
547 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
548 qxl->rom->mm_clock = cpu_to_le32(mm_time);
549 qxl_rom_set_dirty(qxl);
550}
551#endif
552
553static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
554{
555 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
556
557 trace_qxl_interface_get_init_info(qxl->id);
558 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
559 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
560 info->num_memslots = NUM_MEMSLOTS;
561 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
562 info->internal_groupslot_id = 0;
563 info->qxl_ram_size =
564 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
565 info->n_surfaces = qxl->ssd.num_surfaces;
566}
567
568static const char *qxl_mode_to_string(int mode)
569{
570 switch (mode) {
571 case QXL_MODE_COMPAT:
572 return "compat";
573 case QXL_MODE_NATIVE:
574 return "native";
575 case QXL_MODE_UNDEFINED:
576 return "undefined";
577 case QXL_MODE_VGA:
578 return "vga";
579 }
580 return "INVALID";
581}
582
583static const char *io_port_to_string(uint32_t io_port)
584{
585 if (io_port >= QXL_IO_RANGE_SIZE) {
586 return "out of range";
587 }
588 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
589 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
590 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
591 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
592 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
593 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
594 [QXL_IO_RESET] = "QXL_IO_RESET",
595 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
596 [QXL_IO_LOG] = "QXL_IO_LOG",
597 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
598 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
599 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
600 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
601 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
602 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
603 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
604 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
605 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
606 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
607 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
608 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
609 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
610 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
611 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
612 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
613 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
614 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
615 };
616 return io_port_to_string[io_port];
617}
618
619
620static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
621{
622 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
623 SimpleSpiceUpdate *update;
624 QXLCommandRing *ring;
625 QXLCommand *cmd;
626 int notify, ret;
627
628 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
629
630 switch (qxl->mode) {
631 case QXL_MODE_VGA:
632 ret = false;
633 qemu_mutex_lock(&qxl->ssd.lock);
634 update = QTAILQ_FIRST(&qxl->ssd.updates);
635 if (update != NULL) {
636 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
637 *ext = update->ext;
638 ret = true;
639 }
640 qemu_mutex_unlock(&qxl->ssd.lock);
641 if (ret) {
642 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
643 qxl_log_command(qxl, "vga", ext);
644 }
645 return ret;
646 case QXL_MODE_COMPAT:
647 case QXL_MODE_NATIVE:
648 case QXL_MODE_UNDEFINED:
649 ring = &qxl->ram->cmd_ring;
650 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
651 return false;
652 }
653 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
654 if (!cmd) {
655 return false;
656 }
657 ext->cmd = *cmd;
658 ext->group_id = MEMSLOT_GROUP_GUEST;
659 ext->flags = qxl->cmdflags;
660 SPICE_RING_POP(ring, notify);
661 qxl_ring_set_dirty(qxl);
662 if (notify) {
663 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
664 }
665 qxl->guest_primary.commands++;
666 qxl_track_command(qxl, ext);
667 qxl_log_command(qxl, "cmd", ext);
668 {
669
670
671
672
673
674
675
676
677 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
678 if (msg != NULL && (
679 msg < (void *)qxl->vga.vram_ptr ||
680 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
681 if (!qxl->migration_blocker) {
682 Error *local_err = NULL;
683 error_setg(&qxl->migration_blocker,
684 "qxl: guest bug: command not in ram bar");
685 migrate_add_blocker(qxl->migration_blocker, &local_err);
686 if (local_err) {
687 error_report_err(local_err);
688 }
689 }
690 }
691 }
692 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
693 return true;
694 default:
695 return false;
696 }
697}
698
699
700static int interface_req_cmd_notification(QXLInstance *sin)
701{
702 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
703 int wait = 1;
704
705 trace_qxl_ring_command_req_notification(qxl->id);
706 switch (qxl->mode) {
707 case QXL_MODE_COMPAT:
708 case QXL_MODE_NATIVE:
709 case QXL_MODE_UNDEFINED:
710 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
711 qxl_ring_set_dirty(qxl);
712 break;
713 default:
714
715 break;
716 }
717 return wait;
718}
719
720
721static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
722{
723 QXLReleaseRing *ring = &d->ram->release_ring;
724 uint32_t prod;
725 int notify;
726
727#define QXL_FREE_BUNCH_SIZE 32
728
729 if (ring->prod - ring->cons + 1 == ring->num_items) {
730
731 return;
732 }
733 if (!flush && d->oom_running) {
734
735 return;
736 }
737 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
738
739 return;
740 }
741
742 SPICE_RING_PUSH(ring, notify);
743 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
744 d->guest_surfaces.count, d->num_free_res,
745 d->last_release, notify ? "yes" : "no");
746 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
747 ring->num_items, ring->prod, ring->cons);
748 if (notify) {
749 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
750 }
751
752 ring = &d->ram->release_ring;
753 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
754 if (prod >= ARRAY_SIZE(ring->items)) {
755 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
756 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
757 return;
758 }
759 ring->items[prod].el = 0;
760 d->num_free_res = 0;
761 d->last_release = NULL;
762 qxl_ring_set_dirty(d);
763}
764
765
766static void interface_release_resource(QXLInstance *sin,
767 QXLReleaseInfoExt ext)
768{
769 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
770 QXLReleaseRing *ring;
771 uint32_t prod;
772 uint64_t id;
773
774 if (!ext.info) {
775 return;
776 }
777 if (ext.group_id == MEMSLOT_GROUP_HOST) {
778
779 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
780 SimpleSpiceUpdate *update;
781 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
782 update = container_of(cmdext, SimpleSpiceUpdate, ext);
783 qemu_spice_destroy_update(&qxl->ssd, update);
784 return;
785 }
786
787
788
789
790
791 ring = &qxl->ram->release_ring;
792 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
793 if (prod >= ARRAY_SIZE(ring->items)) {
794 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
795 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
796 return;
797 }
798 if (ring->items[prod].el == 0) {
799
800 id = ext.info->id;
801 ext.info->next = 0;
802 qxl_ram_set_dirty(qxl, &ext.info->next);
803 ring->items[prod].el = id;
804 qxl_ring_set_dirty(qxl);
805 } else {
806
807 qxl->last_release->next = ext.info->id;
808 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
809 ext.info->next = 0;
810 qxl_ram_set_dirty(qxl, &ext.info->next);
811 }
812 qxl->last_release = ext.info;
813 qxl->num_free_res++;
814 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
815 qxl_push_free_res(qxl, 0);
816}
817
818
819static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
820{
821 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
822 QXLCursorRing *ring;
823 QXLCommand *cmd;
824 int notify;
825
826 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
827
828 switch (qxl->mode) {
829 case QXL_MODE_COMPAT:
830 case QXL_MODE_NATIVE:
831 case QXL_MODE_UNDEFINED:
832 ring = &qxl->ram->cursor_ring;
833 if (SPICE_RING_IS_EMPTY(ring)) {
834 return false;
835 }
836 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
837 if (!cmd) {
838 return false;
839 }
840 ext->cmd = *cmd;
841 ext->group_id = MEMSLOT_GROUP_GUEST;
842 ext->flags = qxl->cmdflags;
843 SPICE_RING_POP(ring, notify);
844 qxl_ring_set_dirty(qxl);
845 if (notify) {
846 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
847 }
848 qxl->guest_primary.commands++;
849 qxl_track_command(qxl, ext);
850 qxl_log_command(qxl, "csr", ext);
851 if (qxl->have_vga) {
852 qxl_render_cursor(qxl, ext);
853 }
854 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
855 return true;
856 default:
857 return false;
858 }
859}
860
861
862static int interface_req_cursor_notification(QXLInstance *sin)
863{
864 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
865 int wait = 1;
866
867 trace_qxl_ring_cursor_req_notification(qxl->id);
868 switch (qxl->mode) {
869 case QXL_MODE_COMPAT:
870 case QXL_MODE_NATIVE:
871 case QXL_MODE_UNDEFINED:
872 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
873 qxl_ring_set_dirty(qxl);
874 break;
875 default:
876
877 break;
878 }
879 return wait;
880}
881
882
883static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
884{
885
886
887
888
889
890
891 fprintf(stderr, "%s: deprecated\n", __func__);
892}
893
894
895static int interface_flush_resources(QXLInstance *sin)
896{
897 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
898 int ret;
899
900 ret = qxl->num_free_res;
901 if (ret) {
902 qxl_push_free_res(qxl, 1);
903 }
904 return ret;
905}
906
907static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
908
909
910static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
911{
912 uint32_t current_async;
913
914 qemu_mutex_lock(&qxl->async_lock);
915 current_async = qxl->current_async;
916 qxl->current_async = QXL_UNDEFINED_IO;
917 qemu_mutex_unlock(&qxl->async_lock);
918
919 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
920 if (!cookie) {
921 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
922 return;
923 }
924 if (cookie && current_async != cookie->io) {
925 fprintf(stderr,
926 "qxl: %s: error: current_async = %d != %"
927 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
928 }
929 switch (current_async) {
930 case QXL_IO_MEMSLOT_ADD_ASYNC:
931 case QXL_IO_DESTROY_PRIMARY_ASYNC:
932 case QXL_IO_UPDATE_AREA_ASYNC:
933 case QXL_IO_FLUSH_SURFACES_ASYNC:
934 case QXL_IO_MONITORS_CONFIG_ASYNC:
935 break;
936 case QXL_IO_CREATE_PRIMARY_ASYNC:
937 qxl_create_guest_primary_complete(qxl);
938 break;
939 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
940 qxl_spice_destroy_surfaces_complete(qxl);
941 break;
942 case QXL_IO_DESTROY_SURFACE_ASYNC:
943 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
944 break;
945 default:
946 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
947 current_async);
948 }
949 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
950}
951
952
953static void interface_update_area_complete(QXLInstance *sin,
954 uint32_t surface_id,
955 QXLRect *dirty, uint32_t num_updated_rects)
956{
957 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
958 int i;
959 int qxl_i;
960
961 qemu_mutex_lock(&qxl->ssd.lock);
962 if (surface_id != 0 || !num_updated_rects ||
963 !qxl->render_update_cookie_num) {
964 qemu_mutex_unlock(&qxl->ssd.lock);
965 return;
966 }
967 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
968 dirty->right, dirty->top, dirty->bottom);
969 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
970 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
971
972
973
974 trace_qxl_interface_update_area_complete_overflow(qxl->id,
975 QXL_NUM_DIRTY_RECTS);
976 qxl->guest_primary.resized = 1;
977 }
978 if (qxl->guest_primary.resized) {
979
980
981
982
983 qemu_mutex_unlock(&qxl->ssd.lock);
984 return;
985 }
986 qxl_i = qxl->num_dirty_rects;
987 for (i = 0; i < num_updated_rects; i++) {
988 qxl->dirty[qxl_i++] = dirty[i];
989 }
990 qxl->num_dirty_rects += num_updated_rects;
991 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
992 qxl->num_dirty_rects);
993 qemu_bh_schedule(qxl->update_area_bh);
994 qemu_mutex_unlock(&qxl->ssd.lock);
995}
996
997
998static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
999{
1000 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1001 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
1002
1003 switch (cookie->type) {
1004 case QXL_COOKIE_TYPE_IO:
1005 interface_async_complete_io(qxl, cookie);
1006 g_free(cookie);
1007 break;
1008 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1009 qxl_render_update_area_done(qxl, cookie);
1010 break;
1011 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1012 break;
1013 default:
1014 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1015 __func__, cookie->type);
1016 g_free(cookie);
1017 }
1018}
1019
1020
1021static void interface_set_client_capabilities(QXLInstance *sin,
1022 uint8_t client_present,
1023 uint8_t caps[58])
1024{
1025 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1026
1027 if (qxl->revision < 4) {
1028 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1029 qxl->revision);
1030 return;
1031 }
1032
1033 if (runstate_check(RUN_STATE_INMIGRATE) ||
1034 runstate_check(RUN_STATE_POSTMIGRATE)) {
1035 return;
1036 }
1037
1038 qxl->shadow_rom.client_present = client_present;
1039 memcpy(qxl->shadow_rom.client_capabilities, caps,
1040 sizeof(qxl->shadow_rom.client_capabilities));
1041 qxl->rom->client_present = client_present;
1042 memcpy(qxl->rom->client_capabilities, caps,
1043 sizeof(qxl->rom->client_capabilities));
1044 qxl_rom_set_dirty(qxl);
1045
1046 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1047}
1048
1049static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1050 VDAgentMonitorsConfig *monitors_config,
1051 unsigned int max_outputs)
1052{
1053 int i;
1054 unsigned int monitors_count;
1055
1056 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1057
1058 if (rom->client_monitors_config.count != monitors_count) {
1059 return true;
1060 }
1061
1062 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1063 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1064 QXLURect *rect = &rom->client_monitors_config.heads[i];
1065
1066 if ((rect->left != monitor->x) ||
1067 (rect->top != monitor->y) ||
1068 (rect->right != monitor->x + monitor->width) ||
1069 (rect->bottom != monitor->y + monitor->height)) {
1070 return true;
1071 }
1072 }
1073
1074 return false;
1075}
1076
1077
1078static int interface_client_monitors_config(QXLInstance *sin,
1079 VDAgentMonitorsConfig *monitors_config)
1080{
1081 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1082 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1083 int i;
1084 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1085 bool config_changed = false;
1086
1087 if (qxl->revision < 4) {
1088 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1089 qxl->revision);
1090 return 0;
1091 }
1092
1093
1094
1095
1096
1097
1098 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1099 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1100 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1101 qxl->ram->int_mask,
1102 monitors_config);
1103 return 0;
1104 }
1105 if (!monitors_config) {
1106 return 1;
1107 }
1108
1109#if SPICE_SERVER_VERSION >= 0x000c06
1110
1111 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1112 max_outputs = qxl->max_outputs;
1113 }
1114#endif
1115
1116 config_changed = qxl_rom_monitors_config_changed(rom,
1117 monitors_config,
1118 max_outputs);
1119
1120 memset(&rom->client_monitors_config, 0,
1121 sizeof(rom->client_monitors_config));
1122 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1123
1124 if (rom->client_monitors_config.count >= max_outputs) {
1125 trace_qxl_client_monitors_config_capped(qxl->id,
1126 monitors_config->num_of_monitors,
1127 max_outputs);
1128 rom->client_monitors_config.count = max_outputs;
1129 }
1130 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1131 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1132 QXLURect *rect = &rom->client_monitors_config.heads[i];
1133
1134 rect->left = monitor->x;
1135 rect->top = monitor->y;
1136 rect->right = monitor->x + monitor->width;
1137 rect->bottom = monitor->y + monitor->height;
1138 }
1139 rom->client_monitors_config_crc = qxl_crc32(
1140 (const uint8_t *)&rom->client_monitors_config,
1141 sizeof(rom->client_monitors_config));
1142 trace_qxl_client_monitors_config_crc(qxl->id,
1143 sizeof(rom->client_monitors_config),
1144 rom->client_monitors_config_crc);
1145
1146 trace_qxl_interrupt_client_monitors_config(qxl->id,
1147 rom->client_monitors_config.count,
1148 rom->client_monitors_config.heads);
1149 if (config_changed) {
1150 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1151 }
1152 return 1;
1153}
1154
1155static const QXLInterface qxl_interface = {
1156 .base.type = SPICE_INTERFACE_QXL,
1157 .base.description = "qxl gpu",
1158 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1159 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1160
1161 .attache_worker = interface_attach_worker,
1162 .set_compression_level = interface_set_compression_level,
1163#if SPICE_NEEDS_SET_MM_TIME
1164 .set_mm_time = interface_set_mm_time,
1165#endif
1166 .get_init_info = interface_get_init_info,
1167
1168
1169 .get_command = interface_get_command,
1170 .req_cmd_notification = interface_req_cmd_notification,
1171 .release_resource = interface_release_resource,
1172 .get_cursor_command = interface_get_cursor_command,
1173 .req_cursor_notification = interface_req_cursor_notification,
1174 .notify_update = interface_notify_update,
1175 .flush_resources = interface_flush_resources,
1176 .async_complete = interface_async_complete,
1177 .update_area_complete = interface_update_area_complete,
1178 .set_client_capabilities = interface_set_client_capabilities,
1179 .client_monitors_config = interface_client_monitors_config,
1180};
1181
1182static const GraphicHwOps qxl_ops = {
1183 .gfx_update = qxl_hw_update,
1184};
1185
1186static void qxl_enter_vga_mode(PCIQXLDevice *d)
1187{
1188 if (d->mode == QXL_MODE_VGA) {
1189 return;
1190 }
1191 trace_qxl_enter_vga_mode(d->id);
1192 spice_qxl_driver_unload(&d->ssd.qxl);
1193 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1194 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1195 qemu_spice_create_host_primary(&d->ssd);
1196 d->mode = QXL_MODE_VGA;
1197 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1198 vga_dirty_log_start(&d->vga);
1199 graphic_hw_update(d->vga.con);
1200}
1201
1202static void qxl_exit_vga_mode(PCIQXLDevice *d)
1203{
1204 if (d->mode != QXL_MODE_VGA) {
1205 return;
1206 }
1207 trace_qxl_exit_vga_mode(d->id);
1208 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1209 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1210 vga_dirty_log_stop(&d->vga);
1211 qxl_destroy_primary(d, QXL_SYNC);
1212}
1213
1214static void qxl_update_irq(PCIQXLDevice *d)
1215{
1216 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1217 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1218 int level = !!(pending & mask);
1219 pci_set_irq(&d->pci, level);
1220 qxl_ring_set_dirty(d);
1221}
1222
1223static void qxl_check_state(PCIQXLDevice *d)
1224{
1225 QXLRam *ram = d->ram;
1226 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1227
1228 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1229 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1230}
1231
1232static void qxl_reset_state(PCIQXLDevice *d)
1233{
1234 QXLRom *rom = d->rom;
1235
1236 qxl_check_state(d);
1237 d->shadow_rom.update_id = cpu_to_le32(0);
1238 *rom = d->shadow_rom;
1239 qxl_rom_set_dirty(d);
1240 init_qxl_ram(d);
1241 d->num_free_res = 0;
1242 d->last_release = NULL;
1243 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1244 qxl_update_irq(d);
1245}
1246
1247static void qxl_soft_reset(PCIQXLDevice *d)
1248{
1249 trace_qxl_soft_reset(d->id);
1250 qxl_check_state(d);
1251 qxl_clear_guest_bug(d);
1252 qemu_mutex_lock(&d->async_lock);
1253 d->current_async = QXL_UNDEFINED_IO;
1254 qemu_mutex_unlock(&d->async_lock);
1255
1256 if (d->have_vga) {
1257 qxl_enter_vga_mode(d);
1258 } else {
1259 d->mode = QXL_MODE_UNDEFINED;
1260 }
1261}
1262
1263static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1264{
1265 bool startstop = qemu_spice_display_is_running(&d->ssd);
1266
1267 trace_qxl_hard_reset(d->id, loadvm);
1268
1269 if (startstop) {
1270 qemu_spice_display_stop();
1271 }
1272
1273 qxl_spice_reset_cursor(d);
1274 qxl_spice_reset_image_cache(d);
1275 qxl_reset_surfaces(d);
1276 qxl_reset_memslots(d);
1277
1278
1279
1280
1281 if (!loadvm) {
1282 qxl_reset_state(d);
1283 }
1284 qemu_spice_create_host_memslot(&d->ssd);
1285 qxl_soft_reset(d);
1286
1287 if (d->migration_blocker) {
1288 migrate_del_blocker(d->migration_blocker);
1289 error_free(d->migration_blocker);
1290 d->migration_blocker = NULL;
1291 }
1292
1293 if (startstop) {
1294 qemu_spice_display_start();
1295 }
1296}
1297
1298static void qxl_reset_handler(DeviceState *dev)
1299{
1300 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1301
1302 qxl_hard_reset(d, 0);
1303}
1304
1305static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1306{
1307 VGACommonState *vga = opaque;
1308 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1309
1310 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1311 if (qxl->mode != QXL_MODE_VGA) {
1312 qxl_destroy_primary(qxl, QXL_SYNC);
1313 qxl_soft_reset(qxl);
1314 }
1315 vga_ioport_write(opaque, addr, val);
1316}
1317
1318static const MemoryRegionPortio qxl_vga_portio_list[] = {
1319 { 0x04, 2, 1, .read = vga_ioport_read,
1320 .write = qxl_vga_ioport_write },
1321 { 0x0a, 1, 1, .read = vga_ioport_read,
1322 .write = qxl_vga_ioport_write },
1323 { 0x10, 16, 1, .read = vga_ioport_read,
1324 .write = qxl_vga_ioport_write },
1325 { 0x24, 2, 1, .read = vga_ioport_read,
1326 .write = qxl_vga_ioport_write },
1327 { 0x2a, 1, 1, .read = vga_ioport_read,
1328 .write = qxl_vga_ioport_write },
1329 PORTIO_END_OF_LIST(),
1330};
1331
1332static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1333 qxl_async_io async)
1334{
1335 static const int regions[] = {
1336 QXL_RAM_RANGE_INDEX,
1337 QXL_VRAM_RANGE_INDEX,
1338 QXL_VRAM64_RANGE_INDEX,
1339 };
1340 uint64_t guest_start;
1341 uint64_t guest_end;
1342 int pci_region;
1343 pcibus_t pci_start;
1344 pcibus_t pci_end;
1345 MemoryRegion *mr;
1346 intptr_t virt_start;
1347 QXLDevMemSlot memslot;
1348 int i;
1349
1350 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1351 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1352
1353 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1354
1355 if (slot_id >= NUM_MEMSLOTS) {
1356 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1357 slot_id, NUM_MEMSLOTS);
1358 return 1;
1359 }
1360 if (guest_start > guest_end) {
1361 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1362 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1363 return 1;
1364 }
1365
1366 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1367 pci_region = regions[i];
1368 pci_start = d->pci.io_regions[pci_region].addr;
1369 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1370
1371 if (pci_start == -1) {
1372 continue;
1373 }
1374
1375 if (guest_start < pci_start || guest_start > pci_end) {
1376 continue;
1377 }
1378
1379 if (guest_end > pci_end) {
1380 continue;
1381 }
1382
1383 break;
1384 }
1385 if (i == ARRAY_SIZE(regions)) {
1386 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1387 return 1;
1388 }
1389
1390 switch (pci_region) {
1391 case QXL_RAM_RANGE_INDEX:
1392 mr = &d->vga.vram;
1393 break;
1394 case QXL_VRAM_RANGE_INDEX:
1395 case 4 :
1396 mr = &d->vram_bar;
1397 break;
1398 default:
1399
1400 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1401 return 1;
1402 }
1403
1404 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1405 memslot.slot_id = slot_id;
1406 memslot.slot_group_id = MEMSLOT_GROUP_GUEST;
1407 memslot.virt_start = virt_start + (guest_start - pci_start);
1408 memslot.virt_end = virt_start + (guest_end - pci_start);
1409 memslot.addr_delta = memslot.virt_start - delta;
1410 memslot.generation = d->rom->slot_generation = 0;
1411 qxl_rom_set_dirty(d);
1412
1413 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1414 d->guest_slots[slot_id].mr = mr;
1415 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1416 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1417 d->guest_slots[slot_id].delta = delta;
1418 d->guest_slots[slot_id].active = 1;
1419 return 0;
1420}
1421
1422static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1423{
1424 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1425 d->guest_slots[slot_id].active = 0;
1426}
1427
1428static void qxl_reset_memslots(PCIQXLDevice *d)
1429{
1430 qxl_spice_reset_memslots(d);
1431 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1432}
1433
1434static void qxl_reset_surfaces(PCIQXLDevice *d)
1435{
1436 trace_qxl_reset_surfaces(d->id);
1437 d->mode = QXL_MODE_UNDEFINED;
1438 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1439}
1440
1441
1442static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1443 uint32_t *s, uint64_t *o)
1444{
1445 uint64_t phys = le64_to_cpu(pqxl);
1446 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1447 uint64_t offset = phys & 0xffffffffffff;
1448
1449 if (slot >= NUM_MEMSLOTS) {
1450 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1451 NUM_MEMSLOTS);
1452 return false;
1453 }
1454 if (!qxl->guest_slots[slot].active) {
1455 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1456 return false;
1457 }
1458 if (offset < qxl->guest_slots[slot].delta) {
1459 qxl_set_guest_bug(qxl,
1460 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1461 slot, offset, qxl->guest_slots[slot].delta);
1462 return false;
1463 }
1464 offset -= qxl->guest_slots[slot].delta;
1465 if (offset > qxl->guest_slots[slot].size) {
1466 qxl_set_guest_bug(qxl,
1467 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1468 slot, offset, qxl->guest_slots[slot].size);
1469 return false;
1470 }
1471
1472 *s = slot;
1473 *o = offset;
1474 return true;
1475}
1476
1477
1478void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1479{
1480 uint64_t offset;
1481 uint32_t slot;
1482 void *ptr;
1483
1484 switch (group_id) {
1485 case MEMSLOT_GROUP_HOST:
1486 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1487 return (void *)(intptr_t)offset;
1488 case MEMSLOT_GROUP_GUEST:
1489 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
1490 return NULL;
1491 }
1492 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1493 ptr += qxl->guest_slots[slot].offset;
1494 ptr += offset;
1495 return ptr;
1496 }
1497 return NULL;
1498}
1499
1500static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1501{
1502
1503 qxl_render_resize(qxl);
1504}
1505
1506static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1507 qxl_async_io async)
1508{
1509 QXLDevSurfaceCreate surface;
1510 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1511 uint32_t requested_height = le32_to_cpu(sc->height);
1512 int requested_stride = le32_to_cpu(sc->stride);
1513
1514 if (requested_stride == INT32_MIN ||
1515 abs(requested_stride) * (uint64_t)requested_height
1516 > qxl->vgamem_size) {
1517 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1518 " stride %d x height %" PRIu32 " > %" PRIu32,
1519 __func__, requested_stride, requested_height,
1520 qxl->vgamem_size);
1521 return;
1522 }
1523
1524 if (qxl->mode == QXL_MODE_NATIVE) {
1525 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1526 __func__);
1527 }
1528 qxl_exit_vga_mode(qxl);
1529
1530 surface.format = le32_to_cpu(sc->format);
1531 surface.height = le32_to_cpu(sc->height);
1532 surface.mem = le64_to_cpu(sc->mem);
1533 surface.position = le32_to_cpu(sc->position);
1534 surface.stride = le32_to_cpu(sc->stride);
1535 surface.width = le32_to_cpu(sc->width);
1536 surface.type = le32_to_cpu(sc->type);
1537 surface.flags = le32_to_cpu(sc->flags);
1538 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1539 sc->format, sc->position);
1540 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1541 sc->flags);
1542
1543 if ((surface.stride & 0x3) != 0) {
1544 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1545 surface.stride);
1546 return;
1547 }
1548
1549 surface.mouse_mode = true;
1550 surface.group_id = MEMSLOT_GROUP_GUEST;
1551 if (loadvm) {
1552 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1553 }
1554
1555 qxl->mode = QXL_MODE_NATIVE;
1556 qxl->cmdflags = 0;
1557 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1558
1559 if (async == QXL_SYNC) {
1560 qxl_create_guest_primary_complete(qxl);
1561 }
1562}
1563
1564
1565
1566static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1567{
1568 if (d->mode == QXL_MODE_UNDEFINED) {
1569 return 0;
1570 }
1571 trace_qxl_destroy_primary(d->id);
1572 d->mode = QXL_MODE_UNDEFINED;
1573 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1574 qxl_spice_reset_cursor(d);
1575 return 1;
1576}
1577
1578static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1579{
1580 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1581 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1582 QXLMode *mode = d->modes->modes + modenr;
1583 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1584 QXLMemSlot slot = {
1585 .mem_start = start,
1586 .mem_end = end
1587 };
1588
1589 if (modenr >= d->modes->n_modes) {
1590 qxl_set_guest_bug(d, "mode number out of range");
1591 return;
1592 }
1593
1594 QXLSurfaceCreate surface = {
1595 .width = mode->x_res,
1596 .height = mode->y_res,
1597 .stride = -mode->x_res * 4,
1598 .format = SPICE_SURFACE_FMT_32_xRGB,
1599 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1600 .mouse_mode = true,
1601 .mem = devmem + d->shadow_rom.draw_area_offset,
1602 };
1603
1604 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1605 devmem);
1606 if (!loadvm) {
1607 qxl_hard_reset(d, 0);
1608 }
1609
1610 d->guest_slots[0].slot = slot;
1611 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1612
1613 d->guest_primary.surface = surface;
1614 qxl_create_guest_primary(d, 0, QXL_SYNC);
1615
1616 d->mode = QXL_MODE_COMPAT;
1617 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1618 if (mode->bits == 16) {
1619 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1620 }
1621 d->shadow_rom.mode = cpu_to_le32(modenr);
1622 d->rom->mode = cpu_to_le32(modenr);
1623 qxl_rom_set_dirty(d);
1624}
1625
1626static void ioport_write(void *opaque, hwaddr addr,
1627 uint64_t val, unsigned size)
1628{
1629 PCIQXLDevice *d = opaque;
1630 uint32_t io_port = addr;
1631 qxl_async_io async = QXL_SYNC;
1632 uint32_t orig_io_port = io_port;
1633
1634 if (d->guest_bug && io_port != QXL_IO_RESET) {
1635 return;
1636 }
1637
1638 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1639 io_port > QXL_IO_FLUSH_RELEASE) {
1640 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1641 io_port, d->revision);
1642 return;
1643 }
1644
1645 switch (io_port) {
1646 case QXL_IO_RESET:
1647 case QXL_IO_SET_MODE:
1648 case QXL_IO_MEMSLOT_ADD:
1649 case QXL_IO_MEMSLOT_DEL:
1650 case QXL_IO_CREATE_PRIMARY:
1651 case QXL_IO_UPDATE_IRQ:
1652 case QXL_IO_LOG:
1653 case QXL_IO_MEMSLOT_ADD_ASYNC:
1654 case QXL_IO_CREATE_PRIMARY_ASYNC:
1655 break;
1656 default:
1657 if (d->mode != QXL_MODE_VGA) {
1658 break;
1659 }
1660 trace_qxl_io_unexpected_vga_mode(d->id,
1661 addr, val, io_port_to_string(io_port));
1662
1663 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1664 io_port < QXL_IO_RANGE_SIZE) {
1665 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1666 }
1667 return;
1668 }
1669
1670
1671 orig_io_port = io_port;
1672 switch (io_port) {
1673 case QXL_IO_UPDATE_AREA_ASYNC:
1674 io_port = QXL_IO_UPDATE_AREA;
1675 goto async_common;
1676 case QXL_IO_MEMSLOT_ADD_ASYNC:
1677 io_port = QXL_IO_MEMSLOT_ADD;
1678 goto async_common;
1679 case QXL_IO_CREATE_PRIMARY_ASYNC:
1680 io_port = QXL_IO_CREATE_PRIMARY;
1681 goto async_common;
1682 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1683 io_port = QXL_IO_DESTROY_PRIMARY;
1684 goto async_common;
1685 case QXL_IO_DESTROY_SURFACE_ASYNC:
1686 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1687 goto async_common;
1688 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1689 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1690 goto async_common;
1691 case QXL_IO_FLUSH_SURFACES_ASYNC:
1692 case QXL_IO_MONITORS_CONFIG_ASYNC:
1693async_common:
1694 async = QXL_ASYNC;
1695 qemu_mutex_lock(&d->async_lock);
1696 if (d->current_async != QXL_UNDEFINED_IO) {
1697 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1698 io_port, d->current_async);
1699 qemu_mutex_unlock(&d->async_lock);
1700 return;
1701 }
1702 d->current_async = orig_io_port;
1703 qemu_mutex_unlock(&d->async_lock);
1704 break;
1705 default:
1706 break;
1707 }
1708 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1709 addr, io_port_to_string(addr),
1710 val, size, async);
1711
1712 switch (io_port) {
1713 case QXL_IO_UPDATE_AREA:
1714 {
1715 QXLCookie *cookie = NULL;
1716 QXLRect update = d->ram->update_area;
1717
1718 if (d->ram->update_surface > d->ssd.num_surfaces) {
1719 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1720 d->ram->update_surface);
1721 break;
1722 }
1723 if (update.left >= update.right || update.top >= update.bottom ||
1724 update.left < 0 || update.top < 0) {
1725 qxl_set_guest_bug(d,
1726 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1727 update.left, update.top, update.right, update.bottom);
1728 if (update.left == update.right || update.top == update.bottom) {
1729
1730 qxl_clear_guest_bug(d);
1731 goto cancel_async;
1732 }
1733 break;
1734 }
1735 if (async == QXL_ASYNC) {
1736 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1737 QXL_IO_UPDATE_AREA_ASYNC);
1738 cookie->u.area = update;
1739 }
1740 qxl_spice_update_area(d, d->ram->update_surface,
1741 cookie ? &cookie->u.area : &update,
1742 NULL, 0, 0, async, cookie);
1743 break;
1744 }
1745 case QXL_IO_NOTIFY_CMD:
1746 qemu_spice_wakeup(&d->ssd);
1747 break;
1748 case QXL_IO_NOTIFY_CURSOR:
1749 qemu_spice_wakeup(&d->ssd);
1750 break;
1751 case QXL_IO_UPDATE_IRQ:
1752 qxl_update_irq(d);
1753 break;
1754 case QXL_IO_NOTIFY_OOM:
1755 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1756 break;
1757 }
1758 d->oom_running = 1;
1759 qxl_spice_oom(d);
1760 d->oom_running = 0;
1761 break;
1762 case QXL_IO_SET_MODE:
1763 qxl_set_mode(d, val, 0);
1764 break;
1765 case QXL_IO_LOG:
1766 if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1767
1768 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1769 sizeof(d->ram->log_buf));
1770 trace_qxl_io_log(d->id, log_buf);
1771 if (d->guestdebug) {
1772 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1773 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1774 }
1775 g_free(log_buf);
1776 }
1777 break;
1778 case QXL_IO_RESET:
1779 qxl_hard_reset(d, 0);
1780 break;
1781 case QXL_IO_MEMSLOT_ADD:
1782 if (val >= NUM_MEMSLOTS) {
1783 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1784 break;
1785 }
1786 if (d->guest_slots[val].active) {
1787 qxl_set_guest_bug(d,
1788 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1789 break;
1790 }
1791 d->guest_slots[val].slot = d->ram->mem_slot;
1792 qxl_add_memslot(d, val, 0, async);
1793 break;
1794 case QXL_IO_MEMSLOT_DEL:
1795 if (val >= NUM_MEMSLOTS) {
1796 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1797 break;
1798 }
1799 qxl_del_memslot(d, val);
1800 break;
1801 case QXL_IO_CREATE_PRIMARY:
1802 if (val != 0) {
1803 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1804 async);
1805 goto cancel_async;
1806 }
1807 d->guest_primary.surface = d->ram->create_surface;
1808 qxl_create_guest_primary(d, 0, async);
1809 break;
1810 case QXL_IO_DESTROY_PRIMARY:
1811 if (val != 0) {
1812 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1813 async);
1814 goto cancel_async;
1815 }
1816 if (!qxl_destroy_primary(d, async)) {
1817 trace_qxl_io_destroy_primary_ignored(d->id,
1818 qxl_mode_to_string(d->mode));
1819 goto cancel_async;
1820 }
1821 break;
1822 case QXL_IO_DESTROY_SURFACE_WAIT:
1823 if (val >= d->ssd.num_surfaces) {
1824 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1825 "%" PRIu64 " >= NUM_SURFACES", async, val);
1826 goto cancel_async;
1827 }
1828 qxl_spice_destroy_surface_wait(d, val, async);
1829 break;
1830 case QXL_IO_FLUSH_RELEASE: {
1831 QXLReleaseRing *ring = &d->ram->release_ring;
1832 if (ring->prod - ring->cons + 1 == ring->num_items) {
1833 fprintf(stderr,
1834 "ERROR: no flush, full release ring [p%d,%dc]\n",
1835 ring->prod, ring->cons);
1836 }
1837 qxl_push_free_res(d, 1 );
1838 break;
1839 }
1840 case QXL_IO_FLUSH_SURFACES_ASYNC:
1841 qxl_spice_flush_surfaces_async(d);
1842 break;
1843 case QXL_IO_DESTROY_ALL_SURFACES:
1844 d->mode = QXL_MODE_UNDEFINED;
1845 qxl_spice_destroy_surfaces(d, async);
1846 break;
1847 case QXL_IO_MONITORS_CONFIG_ASYNC:
1848 qxl_spice_monitors_config_async(d, 0);
1849 break;
1850 default:
1851 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1852 }
1853 return;
1854cancel_async:
1855 if (async) {
1856 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1857 qemu_mutex_lock(&d->async_lock);
1858 d->current_async = QXL_UNDEFINED_IO;
1859 qemu_mutex_unlock(&d->async_lock);
1860 }
1861}
1862
1863static uint64_t ioport_read(void *opaque, hwaddr addr,
1864 unsigned size)
1865{
1866 PCIQXLDevice *qxl = opaque;
1867
1868 trace_qxl_io_read_unexpected(qxl->id);
1869 return 0xff;
1870}
1871
1872static const MemoryRegionOps qxl_io_ops = {
1873 .read = ioport_read,
1874 .write = ioport_write,
1875 .valid = {
1876 .min_access_size = 1,
1877 .max_access_size = 1,
1878 },
1879};
1880
1881static void qxl_update_irq_bh(void *opaque)
1882{
1883 PCIQXLDevice *d = opaque;
1884 qxl_update_irq(d);
1885}
1886
1887static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1888{
1889 uint32_t old_pending;
1890 uint32_t le_events = cpu_to_le32(events);
1891
1892 trace_qxl_send_events(d->id, events);
1893 if (!qemu_spice_display_is_running(&d->ssd)) {
1894
1895 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1896 __func__);
1897 trace_qxl_send_events_vm_stopped(d->id, events);
1898 return;
1899 }
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917#ifdef HAS_ASSUME_ALIGNED
1918#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1919#else
1920#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1921#endif
1922
1923 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1924 le_events);
1925 if ((old_pending & le_events) == le_events) {
1926 return;
1927 }
1928 qemu_bh_schedule(d->update_irq);
1929}
1930
1931
1932
1933static void qxl_hw_update(void *opaque)
1934{
1935 PCIQXLDevice *qxl = opaque;
1936
1937 qxl_render_update(qxl);
1938}
1939
1940static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1941 uint32_t height, int32_t stride)
1942{
1943 uint64_t offset, size;
1944 uint32_t slot;
1945 bool rc;
1946
1947 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1948 assert(rc == true);
1949 size = (uint64_t)height * abs(stride);
1950 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1951 qxl_set_dirty(qxl->guest_slots[slot].mr,
1952 qxl->guest_slots[slot].offset + offset,
1953 qxl->guest_slots[slot].offset + offset + size);
1954}
1955
1956static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1957{
1958 int i;
1959
1960 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1961 return;
1962 }
1963
1964
1965 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1966 qxl->guest_primary.surface.height,
1967 qxl->guest_primary.surface.stride);
1968
1969
1970 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1971 QXLSurfaceCmd *cmd;
1972
1973 if (qxl->guest_surfaces.cmds[i] == 0) {
1974 continue;
1975 }
1976
1977 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1978 MEMSLOT_GROUP_GUEST);
1979 assert(cmd);
1980 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1981 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1982 cmd->u.surface_create.height,
1983 cmd->u.surface_create.stride);
1984 }
1985}
1986
1987static void qxl_vm_change_state_handler(void *opaque, int running,
1988 RunState state)
1989{
1990 PCIQXLDevice *qxl = opaque;
1991
1992 if (running) {
1993
1994
1995
1996
1997
1998 qxl_update_irq(qxl);
1999 } else {
2000
2001 qxl_dirty_surfaces(qxl);
2002 }
2003}
2004
2005
2006
2007static void display_update(DisplayChangeListener *dcl,
2008 int x, int y, int w, int h)
2009{
2010 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2011
2012 if (qxl->mode == QXL_MODE_VGA) {
2013 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2014 }
2015}
2016
2017static void display_switch(DisplayChangeListener *dcl,
2018 struct DisplaySurface *surface)
2019{
2020 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2021
2022 qxl->ssd.ds = surface;
2023 if (qxl->mode == QXL_MODE_VGA) {
2024 qemu_spice_display_switch(&qxl->ssd, surface);
2025 }
2026}
2027
2028static void display_refresh(DisplayChangeListener *dcl)
2029{
2030 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2031
2032 if (qxl->mode == QXL_MODE_VGA) {
2033 qemu_spice_display_refresh(&qxl->ssd);
2034 }
2035}
2036
2037static DisplayChangeListenerOps display_listener_ops = {
2038 .dpy_name = "spice/qxl",
2039 .dpy_gfx_update = display_update,
2040 .dpy_gfx_switch = display_switch,
2041 .dpy_refresh = display_refresh,
2042};
2043
2044static void qxl_init_ramsize(PCIQXLDevice *qxl)
2045{
2046
2047 if (qxl->vgamem_size_mb < 8) {
2048 qxl->vgamem_size_mb = 8;
2049 }
2050
2051
2052
2053 if (qxl->vgamem_size_mb > 256) {
2054 qxl->vgamem_size_mb = 256;
2055 }
2056 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2057
2058
2059 if (qxl->ram_size_mb != -1) {
2060 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2061 }
2062 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2063 qxl->vga.vram_size = qxl->vgamem_size * 2;
2064 }
2065
2066
2067 if (qxl->vram32_size_mb != -1) {
2068 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2069 }
2070 if (qxl->vram32_size < 4096) {
2071 qxl->vram32_size = 4096;
2072 }
2073
2074
2075 if (qxl->vram_size_mb != -1) {
2076 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2077 }
2078 if (qxl->vram_size < qxl->vram32_size) {
2079 qxl->vram_size = qxl->vram32_size;
2080 }
2081
2082 if (qxl->revision == 1) {
2083 qxl->vram32_size = 4096;
2084 qxl->vram_size = 4096;
2085 }
2086 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2087 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2088 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2089 qxl->vram_size = pow2ceil(qxl->vram_size);
2090}
2091
2092static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2093{
2094 uint8_t* config = qxl->pci.config;
2095 uint32_t pci_device_rev;
2096 uint32_t io_size;
2097
2098 qemu_spice_display_init_common(&qxl->ssd);
2099 qxl->mode = QXL_MODE_UNDEFINED;
2100 qxl->num_memslots = NUM_MEMSLOTS;
2101 qemu_mutex_init(&qxl->track_lock);
2102 qemu_mutex_init(&qxl->async_lock);
2103 qxl->current_async = QXL_UNDEFINED_IO;
2104 qxl->guest_bug = 0;
2105
2106 switch (qxl->revision) {
2107 case 1:
2108 pci_device_rev = QXL_REVISION_STABLE_V04;
2109 io_size = 8;
2110 break;
2111 case 2:
2112 pci_device_rev = QXL_REVISION_STABLE_V06;
2113 io_size = 16;
2114 break;
2115 case 3:
2116 pci_device_rev = QXL_REVISION_STABLE_V10;
2117 io_size = 32;
2118 break;
2119 case 4:
2120 pci_device_rev = QXL_REVISION_STABLE_V12;
2121 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2122 break;
2123 default:
2124 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2125 qxl->revision, QXL_DEFAULT_REVISION);
2126 return;
2127 }
2128
2129 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2130 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2131
2132 qxl->rom_size = qxl_rom_size();
2133 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2134 qxl->rom_size, &error_fatal);
2135 init_qxl_rom(qxl);
2136 init_qxl_ram(qxl);
2137
2138 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2139 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2140 qxl->vram_size, &error_fatal);
2141 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2142 &qxl->vram_bar, 0, qxl->vram32_size);
2143
2144 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2145 "qxl-ioports", io_size);
2146 if (qxl->have_vga) {
2147 vga_dirty_log_start(&qxl->vga);
2148 }
2149 memory_region_set_flush_coalesced(&qxl->io_bar);
2150
2151
2152 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2153 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2154
2155 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2156 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2157
2158 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2159 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2160
2161 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2162 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2163
2164 if (qxl->vram32_size < qxl->vram_size) {
2165
2166
2167
2168
2169 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2170 PCI_BASE_ADDRESS_SPACE_MEMORY |
2171 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2172 PCI_BASE_ADDRESS_MEM_PREFETCH,
2173 &qxl->vram_bar);
2174 }
2175
2176
2177 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2178 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2179 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2180 qxl->vram32_size / MiB);
2181 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2182 qxl->vram_size / MiB,
2183 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2184
2185 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2186 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2187 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2188 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2189 return;
2190 }
2191
2192#if SPICE_SERVER_VERSION >= 0x000e02
2193 char device_address[256] = "";
2194 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2195 spice_qxl_set_device_info(&qxl->ssd.qxl,
2196 device_address,
2197 0,
2198 qxl->max_outputs);
2199 }
2200#endif
2201
2202 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2203
2204 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2205 qxl_reset_state(qxl);
2206
2207 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2208 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2209}
2210
2211static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2212{
2213 PCIQXLDevice *qxl = PCI_QXL(dev);
2214 VGACommonState *vga = &qxl->vga;
2215 Error *local_err = NULL;
2216
2217 qxl_init_ramsize(qxl);
2218 vga->vbe_size = qxl->vgamem_size;
2219 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2220 vga_common_init(vga, OBJECT(dev));
2221 vga_init(vga, OBJECT(dev),
2222 pci_address_space(dev), pci_address_space_io(dev), false);
2223 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2224 vga, "vga");
2225 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2226 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2227 qxl->have_vga = true;
2228
2229 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2230 qxl->id = qemu_console_get_index(vga->con);
2231 if (qxl->id != 0) {
2232 error_setg(errp, "primary qxl-vga device must be console 0 "
2233 "(first display device on the command line)");
2234 return;
2235 }
2236
2237 qxl_realize_common(qxl, &local_err);
2238 if (local_err) {
2239 error_propagate(errp, local_err);
2240 return;
2241 }
2242
2243 qxl->ssd.dcl.ops = &display_listener_ops;
2244 qxl->ssd.dcl.con = vga->con;
2245 register_displaychangelistener(&qxl->ssd.dcl);
2246}
2247
2248static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2249{
2250 PCIQXLDevice *qxl = PCI_QXL(dev);
2251
2252 qxl_init_ramsize(qxl);
2253 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2254 qxl->vga.vram_size, &error_fatal);
2255 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2256 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2257 qxl->id = qemu_console_get_index(qxl->vga.con);
2258
2259 qxl_realize_common(qxl, errp);
2260}
2261
2262static int qxl_pre_save(void *opaque)
2263{
2264 PCIQXLDevice* d = opaque;
2265 uint8_t *ram_start = d->vga.vram_ptr;
2266
2267 trace_qxl_pre_save(d->id);
2268 if (d->last_release == NULL) {
2269 d->last_release_offset = 0;
2270 } else {
2271 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2272 }
2273 assert(d->last_release_offset < d->vga.vram_size);
2274
2275 return 0;
2276}
2277
2278static int qxl_pre_load(void *opaque)
2279{
2280 PCIQXLDevice* d = opaque;
2281
2282 trace_qxl_pre_load(d->id);
2283 qxl_hard_reset(d, 1);
2284 qxl_exit_vga_mode(d);
2285 return 0;
2286}
2287
2288static void qxl_create_memslots(PCIQXLDevice *d)
2289{
2290 int i;
2291
2292 for (i = 0; i < NUM_MEMSLOTS; i++) {
2293 if (!d->guest_slots[i].active) {
2294 continue;
2295 }
2296 qxl_add_memslot(d, i, 0, QXL_SYNC);
2297 }
2298}
2299
2300static int qxl_post_load(void *opaque, int version)
2301{
2302 PCIQXLDevice* d = opaque;
2303 uint8_t *ram_start = d->vga.vram_ptr;
2304 QXLCommandExt *cmds;
2305 int in, out, newmode;
2306
2307 assert(d->last_release_offset < d->vga.vram_size);
2308 if (d->last_release_offset == 0) {
2309 d->last_release = NULL;
2310 } else {
2311 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2312 }
2313
2314 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2315
2316 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2317 newmode = d->mode;
2318 d->mode = QXL_MODE_UNDEFINED;
2319
2320 switch (newmode) {
2321 case QXL_MODE_UNDEFINED:
2322 qxl_create_memslots(d);
2323 break;
2324 case QXL_MODE_VGA:
2325 qxl_create_memslots(d);
2326 qxl_enter_vga_mode(d);
2327 break;
2328 case QXL_MODE_NATIVE:
2329 qxl_create_memslots(d);
2330 qxl_create_guest_primary(d, 1, QXL_SYNC);
2331
2332
2333 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2334 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2335 if (d->guest_surfaces.cmds[in] == 0) {
2336 continue;
2337 }
2338 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2339 cmds[out].cmd.type = QXL_CMD_SURFACE;
2340 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2341 out++;
2342 }
2343 if (d->guest_cursor) {
2344 cmds[out].cmd.data = d->guest_cursor;
2345 cmds[out].cmd.type = QXL_CMD_CURSOR;
2346 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2347 out++;
2348 }
2349 qxl_spice_loadvm_commands(d, cmds, out);
2350 g_free(cmds);
2351 if (d->guest_monitors_config) {
2352 qxl_spice_monitors_config_async(d, 1);
2353 }
2354 break;
2355 case QXL_MODE_COMPAT:
2356
2357
2358 qxl_set_mode(d, d->shadow_rom.mode, 1);
2359 break;
2360 }
2361 return 0;
2362}
2363
2364#define QXL_SAVE_VERSION 21
2365
2366static bool qxl_monitors_config_needed(void *opaque)
2367{
2368 PCIQXLDevice *qxl = opaque;
2369
2370 return qxl->guest_monitors_config != 0;
2371}
2372
2373
2374static VMStateDescription qxl_memslot = {
2375 .name = "qxl-memslot",
2376 .version_id = QXL_SAVE_VERSION,
2377 .minimum_version_id = QXL_SAVE_VERSION,
2378 .fields = (VMStateField[]) {
2379 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2380 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2381 VMSTATE_UINT32(active, struct guest_slots),
2382 VMSTATE_END_OF_LIST()
2383 }
2384};
2385
2386static VMStateDescription qxl_surface = {
2387 .name = "qxl-surface",
2388 .version_id = QXL_SAVE_VERSION,
2389 .minimum_version_id = QXL_SAVE_VERSION,
2390 .fields = (VMStateField[]) {
2391 VMSTATE_UINT32(width, QXLSurfaceCreate),
2392 VMSTATE_UINT32(height, QXLSurfaceCreate),
2393 VMSTATE_INT32(stride, QXLSurfaceCreate),
2394 VMSTATE_UINT32(format, QXLSurfaceCreate),
2395 VMSTATE_UINT32(position, QXLSurfaceCreate),
2396 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2397 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2398 VMSTATE_UINT32(type, QXLSurfaceCreate),
2399 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2400 VMSTATE_END_OF_LIST()
2401 }
2402};
2403
2404static VMStateDescription qxl_vmstate_monitors_config = {
2405 .name = "qxl/monitors-config",
2406 .version_id = 1,
2407 .minimum_version_id = 1,
2408 .needed = qxl_monitors_config_needed,
2409 .fields = (VMStateField[]) {
2410 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2411 VMSTATE_END_OF_LIST()
2412 },
2413};
2414
2415static VMStateDescription qxl_vmstate = {
2416 .name = "qxl",
2417 .version_id = QXL_SAVE_VERSION,
2418 .minimum_version_id = QXL_SAVE_VERSION,
2419 .pre_save = qxl_pre_save,
2420 .pre_load = qxl_pre_load,
2421 .post_load = qxl_post_load,
2422 .fields = (VMStateField[]) {
2423 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2424 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2425 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2426 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2427 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2428 VMSTATE_UINT32(mode, PCIQXLDevice),
2429 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2430 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2431 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2432 qxl_memslot, struct guest_slots),
2433 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2434 qxl_surface, QXLSurfaceCreate),
2435 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2436 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2437 ssd.num_surfaces, 0,
2438 vmstate_info_uint64, uint64_t),
2439 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2440 VMSTATE_END_OF_LIST()
2441 },
2442 .subsections = (const VMStateDescription*[]) {
2443 &qxl_vmstate_monitors_config,
2444 NULL
2445 }
2446};
2447
2448static Property qxl_properties[] = {
2449 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2450 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2451 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2452 QXL_DEFAULT_REVISION),
2453 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2454 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2455 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2456 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2457 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2458 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2459 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2460 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2461#if SPICE_SERVER_VERSION >= 0x000c06
2462 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2463#endif
2464 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2465 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2466 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2467 DEFINE_PROP_END_OF_LIST(),
2468};
2469
2470static void qxl_pci_class_init(ObjectClass *klass, void *data)
2471{
2472 DeviceClass *dc = DEVICE_CLASS(klass);
2473 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2474
2475 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2476 k->device_id = QXL_DEVICE_ID_STABLE;
2477 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2478 dc->reset = qxl_reset_handler;
2479 dc->vmsd = &qxl_vmstate;
2480 dc->props = qxl_properties;
2481}
2482
2483static const TypeInfo qxl_pci_type_info = {
2484 .name = TYPE_PCI_QXL,
2485 .parent = TYPE_PCI_DEVICE,
2486 .instance_size = sizeof(PCIQXLDevice),
2487 .abstract = true,
2488 .class_init = qxl_pci_class_init,
2489 .interfaces = (InterfaceInfo[]) {
2490 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2491 { },
2492 },
2493};
2494
2495static void qxl_primary_class_init(ObjectClass *klass, void *data)
2496{
2497 DeviceClass *dc = DEVICE_CLASS(klass);
2498 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2499
2500 k->realize = qxl_realize_primary;
2501 k->romfile = "vgabios-qxl.bin";
2502 k->class_id = PCI_CLASS_DISPLAY_VGA;
2503 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2504 dc->hotpluggable = false;
2505}
2506
2507static const TypeInfo qxl_primary_info = {
2508 .name = "qxl-vga",
2509 .parent = TYPE_PCI_QXL,
2510 .class_init = qxl_primary_class_init,
2511};
2512
2513static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2514{
2515 DeviceClass *dc = DEVICE_CLASS(klass);
2516 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2517
2518 k->realize = qxl_realize_secondary;
2519 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2520 dc->desc = "Spice QXL GPU (secondary)";
2521}
2522
2523static const TypeInfo qxl_secondary_info = {
2524 .name = "qxl",
2525 .parent = TYPE_PCI_QXL,
2526 .class_init = qxl_secondary_class_init,
2527};
2528
2529static void qxl_register_types(void)
2530{
2531 type_register_static(&qxl_pci_type_info);
2532 type_register_static(&qxl_primary_info);
2533 type_register_static(&qxl_secondary_info);
2534}
2535
2536type_init(qxl_register_types)
2537