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27#include "qemu/osdep.h"
28#include "hw/pci/pci.h"
29#include "hw/qdev-properties.h"
30#include "migration/vmstate.h"
31#include "vga_int.h"
32#include "ui/pixel_ops.h"
33#include "qemu/module.h"
34#include "qemu/timer.h"
35#include "hw/loader.h"
36#include "hw/display/edid.h"
37
38enum vga_pci_flags {
39 PCI_VGA_FLAG_ENABLE_MMIO = 1,
40 PCI_VGA_FLAG_ENABLE_QEXT = 2,
41 PCI_VGA_FLAG_ENABLE_EDID = 3,
42};
43
44typedef struct PCIVGAState {
45 PCIDevice dev;
46 VGACommonState vga;
47 uint32_t flags;
48 qemu_edid_info edid_info;
49 MemoryRegion mmio;
50 MemoryRegion mrs[4];
51 uint8_t edid[256];
52} PCIVGAState;
53
54#define TYPE_PCI_VGA "pci-vga"
55#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
56
57static const VMStateDescription vmstate_vga_pci = {
58 .name = "vga",
59 .version_id = 2,
60 .minimum_version_id = 2,
61 .fields = (VMStateField[]) {
62 VMSTATE_PCI_DEVICE(dev, PCIVGAState),
63 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
64 VMSTATE_END_OF_LIST()
65 }
66};
67
68static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
69 unsigned size)
70{
71 VGACommonState *s = ptr;
72 uint64_t ret = 0;
73
74 switch (size) {
75 case 1:
76 ret = vga_ioport_read(s, addr + 0x3c0);
77 break;
78 case 2:
79 ret = vga_ioport_read(s, addr + 0x3c0);
80 ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
81 break;
82 }
83 return ret;
84}
85
86static void pci_vga_ioport_write(void *ptr, hwaddr addr,
87 uint64_t val, unsigned size)
88{
89 VGACommonState *s = ptr;
90
91 switch (size) {
92 case 1:
93 vga_ioport_write(s, addr + 0x3c0, val);
94 break;
95 case 2:
96
97
98
99
100
101 vga_ioport_write(s, addr + 0x3c0, val & 0xff);
102 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
103 break;
104 }
105}
106
107static const MemoryRegionOps pci_vga_ioport_ops = {
108 .read = pci_vga_ioport_read,
109 .write = pci_vga_ioport_write,
110 .valid.min_access_size = 1,
111 .valid.max_access_size = 4,
112 .impl.min_access_size = 1,
113 .impl.max_access_size = 2,
114 .endianness = DEVICE_LITTLE_ENDIAN,
115};
116
117static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
118 unsigned size)
119{
120 VGACommonState *s = ptr;
121 int index = addr >> 1;
122
123 vbe_ioport_write_index(s, 0, index);
124 return vbe_ioport_read_data(s, 0);
125}
126
127static void pci_vga_bochs_write(void *ptr, hwaddr addr,
128 uint64_t val, unsigned size)
129{
130 VGACommonState *s = ptr;
131 int index = addr >> 1;
132
133 vbe_ioport_write_index(s, 0, index);
134 vbe_ioport_write_data(s, 0, val);
135}
136
137static const MemoryRegionOps pci_vga_bochs_ops = {
138 .read = pci_vga_bochs_read,
139 .write = pci_vga_bochs_write,
140 .valid.min_access_size = 1,
141 .valid.max_access_size = 4,
142 .impl.min_access_size = 2,
143 .impl.max_access_size = 2,
144 .endianness = DEVICE_LITTLE_ENDIAN,
145};
146
147static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
148{
149 VGACommonState *s = ptr;
150
151 switch (addr) {
152 case PCI_VGA_QEXT_REG_SIZE:
153 return PCI_VGA_QEXT_SIZE;
154 case PCI_VGA_QEXT_REG_BYTEORDER:
155 return s->big_endian_fb ?
156 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
157 default:
158 return 0;
159 }
160}
161
162static void pci_vga_qext_write(void *ptr, hwaddr addr,
163 uint64_t val, unsigned size)
164{
165 VGACommonState *s = ptr;
166
167 switch (addr) {
168 case PCI_VGA_QEXT_REG_BYTEORDER:
169 if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
170 s->big_endian_fb = true;
171 }
172 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
173 s->big_endian_fb = false;
174 }
175 break;
176 }
177}
178
179static bool vga_get_big_endian_fb(Object *obj, Error **errp)
180{
181 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
182
183 return d->vga.big_endian_fb;
184}
185
186static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
187{
188 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
189
190 d->vga.big_endian_fb = value;
191}
192
193static const MemoryRegionOps pci_vga_qext_ops = {
194 .read = pci_vga_qext_read,
195 .write = pci_vga_qext_write,
196 .valid.min_access_size = 4,
197 .valid.max_access_size = 4,
198 .endianness = DEVICE_LITTLE_ENDIAN,
199};
200
201void pci_std_vga_mmio_region_init(VGACommonState *s,
202 Object *owner,
203 MemoryRegion *parent,
204 MemoryRegion *subs,
205 bool qext, bool edid)
206{
207 PCIVGAState *d = container_of(s, PCIVGAState, vga);
208
209 memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
210 "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
211 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
212 &subs[0]);
213
214 memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
215 "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
216 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
217 &subs[1]);
218
219 if (qext) {
220 memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
221 "qemu extended regs", PCI_VGA_QEXT_SIZE);
222 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
223 &subs[2]);
224 }
225
226 if (edid) {
227 qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
228 qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
229 memory_region_add_subregion(parent, 0, &subs[3]);
230 }
231}
232
233static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
234{
235 PCIVGAState *d = PCI_VGA(dev);
236 VGACommonState *s = &d->vga;
237 bool qext = false;
238 bool edid = false;
239
240
241 vga_common_init(s, OBJECT(dev));
242 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
243 true);
244
245 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
246
247
248 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
249
250
251 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
252 memory_region_init(&d->mmio, NULL, "vga.mmio",
253 PCI_VGA_MMIO_SIZE);
254
255 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
256 qext = true;
257 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
258 }
259 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
260 edid = true;
261 }
262 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
263 qext, edid);
264
265 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
266 }
267
268 if (!dev->rom_bar) {
269
270 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
271 }
272}
273
274static void pci_std_vga_init(Object *obj)
275{
276
277 object_property_add_bool(obj, "big-endian-framebuffer",
278 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
279}
280
281static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
282{
283 PCIVGAState *d = PCI_VGA(dev);
284 VGACommonState *s = &d->vga;
285 bool qext = false;
286 bool edid = false;
287
288
289 vga_common_init(s, OBJECT(dev));
290 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
291
292
293 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio",
294 PCI_VGA_MMIO_SIZE);
295
296 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
297 qext = true;
298 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
299 }
300 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
301 edid = true;
302 }
303 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
304
305 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
306 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
307}
308
309static void pci_secondary_vga_exit(PCIDevice *dev)
310{
311 PCIVGAState *d = PCI_VGA(dev);
312 VGACommonState *s = &d->vga;
313
314 graphic_console_close(s->con);
315 memory_region_del_subregion(&d->mmio, &d->mrs[0]);
316 memory_region_del_subregion(&d->mmio, &d->mrs[1]);
317 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
318 memory_region_del_subregion(&d->mmio, &d->mrs[2]);
319 }
320 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
321 memory_region_del_subregion(&d->mmio, &d->mrs[3]);
322 }
323}
324
325static void pci_secondary_vga_init(Object *obj)
326{
327
328 object_property_add_bool(obj, "big-endian-framebuffer",
329 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
330}
331
332static void pci_secondary_vga_reset(DeviceState *dev)
333{
334 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
335 vga_common_reset(&d->vga);
336}
337
338static Property vga_pci_properties[] = {
339 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
340 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
341 DEFINE_PROP_BIT("qemu-extended-regs",
342 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
343 DEFINE_PROP_BIT("edid",
344 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
345 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
346 DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
347 DEFINE_PROP_END_OF_LIST(),
348};
349
350static Property secondary_pci_properties[] = {
351 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
352 DEFINE_PROP_BIT("qemu-extended-regs",
353 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
354 DEFINE_PROP_BIT("edid",
355 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
356 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
357 DEFINE_PROP_END_OF_LIST(),
358};
359
360static void vga_pci_class_init(ObjectClass *klass, void *data)
361{
362 DeviceClass *dc = DEVICE_CLASS(klass);
363 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
364
365 k->vendor_id = PCI_VENDOR_ID_QEMU;
366 k->device_id = PCI_DEVICE_ID_QEMU_VGA;
367 dc->vmsd = &vmstate_vga_pci;
368 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
369}
370
371static const TypeInfo vga_pci_type_info = {
372 .name = TYPE_PCI_VGA,
373 .parent = TYPE_PCI_DEVICE,
374 .instance_size = sizeof(PCIVGAState),
375 .abstract = true,
376 .class_init = vga_pci_class_init,
377 .interfaces = (InterfaceInfo[]) {
378 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
379 { },
380 },
381};
382
383static void vga_class_init(ObjectClass *klass, void *data)
384{
385 DeviceClass *dc = DEVICE_CLASS(klass);
386 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
387
388 k->realize = pci_std_vga_realize;
389 k->romfile = "vgabios-stdvga.bin";
390 k->class_id = PCI_CLASS_DISPLAY_VGA;
391 dc->props = vga_pci_properties;
392 dc->hotpluggable = false;
393}
394
395static void secondary_class_init(ObjectClass *klass, void *data)
396{
397 DeviceClass *dc = DEVICE_CLASS(klass);
398 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
399
400 k->realize = pci_secondary_vga_realize;
401 k->exit = pci_secondary_vga_exit;
402 k->class_id = PCI_CLASS_DISPLAY_OTHER;
403 dc->props = secondary_pci_properties;
404 dc->reset = pci_secondary_vga_reset;
405}
406
407static const TypeInfo vga_info = {
408 .name = "VGA",
409 .parent = TYPE_PCI_VGA,
410 .instance_init = pci_std_vga_init,
411 .class_init = vga_class_init,
412};
413
414static const TypeInfo secondary_info = {
415 .name = "secondary-vga",
416 .parent = TYPE_PCI_VGA,
417 .instance_init = pci_secondary_vga_init,
418 .class_init = secondary_class_init,
419};
420
421static void vga_register_types(void)
422{
423 type_register_static(&vga_pci_type_info);
424 type_register_static(&vga_info);
425 type_register_static(&secondary_info);
426}
427
428type_init(vga_register_types)
429
