LXR qemu/hw/i386/fw

   1/*
   2 * QEMU fw_cfg helpers (X86 specific)
   3 *
   4 * Copyright (c) 2019 Red Hat, Inc.
   5 *
   6 * Author:
   7 *   Philippe Mathieu-Daudé <philmd@redhat.com>
   8 *
   9 * SPDX-License-Identifier: GPL-2.0-or-later
  10 *
  11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12 * See the COPYING file in the top-level directory.
  13 */
  14
  15#include "qemu/osdep.h"
  16#include "sysemu/numa.h"
  17#include "hw/acpi/acpi.h"
  18#include "hw/firmware/smbios.h"
  19#include "hw/i386/pc.h"
  20#include "hw/i386/fw_cfg.h"
  21#include "hw/timer/hpet.h"
  22#include "hw/nvram/fw_cfg.h"
  23#include "e820_memory_layout.h"
  24#include "kvm_i386.h"
  25
  26const char *fw_cfg_arch_key_name(uint16_t key)
  27{
  28    static const struct {
  29        uint16_t key;
  30        const char *name;
  31    } fw_cfg_arch_wellknown_keys[] = {
  32        {FW_CFG_ACPI_TABLES, "acpi_tables"},
  33        {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
  34        {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
  35        {FW_CFG_E820_TABLE, "e820_table"},
  36        {FW_CFG_HPET, "hpet"},
  37    };
  38
  39    for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
  40        if (fw_cfg_arch_wellknown_keys[i].key == key) {
  41            return fw_cfg_arch_wellknown_keys[i].name;
  42        }
  43    }
  44    return NULL;
  45}
  46
  47void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
  48{
  49    uint8_t *smbios_tables, *smbios_anchor;
  50    size_t smbios_tables_len, smbios_anchor_len;
  51    struct smbios_phys_mem_area *mem_array;
  52    unsigned i, array_count;
  53    X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
  54
  55    /* tell smbios about cpuid version and features */
  56    smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
  57
  58    smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
  59    if (smbios_tables) {
  60        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  61                         smbios_tables, smbios_tables_len);
  62    }
  63
  64    /* build the array of physical mem area from e820 table */
  65    mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
  66    for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
  67        uint64_t addr, len;
  68
  69        if (e820_get_entry(i, E820_RAM, &addr, &len)) {
  70            mem_array[array_count].address = addr;
  71            mem_array[array_count].length = len;
  72            array_count++;
  73        }
  74    }
  75    smbios_get_tables(ms, mem_array, array_count,
  76                      &smbios_tables, &smbios_tables_len,
  77                      &smbios_anchor, &smbios_anchor_len);
  78    g_free(mem_array);
  79
  80    if (smbios_anchor) {
  81        fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
  82                        smbios_tables, smbios_tables_len);
  83        fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
  84                        smbios_anchor, smbios_anchor_len);
  85    }
  86}
  87
  88FWCfgState *fw_cfg_arch_create(MachineState *ms,
  89                                      uint16_t boot_cpus,
  90                                      uint16_t apic_id_limit)
  91{
  92    FWCfgState *fw_cfg;
  93    uint64_t *numa_fw_cfg;
  94    int i;
  95    MachineClass *mc = MACHINE_GET_CLASS(ms);
  96    const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
  97    int nb_numa_nodes = ms->numa_state->num_nodes;
  98
  99    fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 100                                &address_space_memory);
 101    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
 102
 103    /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 104     *
 105     * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 106     * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 107     * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 108     * for CPU hotplug also uses APIC ID and not "CPU index".
 109     * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 110     * but the "limit to the APIC ID values SeaBIOS may see".
 111     *
 112     * So for compatibility reasons with old BIOSes we are stuck with
 113     * "etc/max-cpus" actually being apic_id_limit
 114     */
 115    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
 116    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 117    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 118                     acpi_tables, acpi_tables_len);
 119    fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 120
 121    fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 122                     &e820_reserve, sizeof(e820_reserve));
 123    fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 124                    sizeof(struct e820_entry) * e820_get_num_entries());
 125
 126    fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 127    /* allocate memory for the NUMA channel: one (64bit) word for the number
 128     * of nodes, one word for each VCPU->node and one word for each node to
 129     * hold the amount of memory.
 130     */
 131    numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 132    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 133    for (i = 0; i < cpus->len; i++) {
 134        unsigned int apic_id = cpus->cpus[i].arch_id;
 135        assert(apic_id < apic_id_limit);
 136        numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 137    }
 138    for (i = 0; i < nb_numa_nodes; i++) {
 139        numa_fw_cfg[apic_id_limit + 1 + i] =
 140            cpu_to_le64(ms->numa_state->nodes[i].node_mem);
 141    }
 142    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 143                     (1 + apic_id_limit + nb_numa_nodes) *
 144                     sizeof(*numa_fw_cfg));
 145
 146    return fw_cfg;
 147}
 148
 149void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
 150{
 151    X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 152    CPUX86State *env = &cpu->env;
 153    uint32_t unused, ecx, edx;
 154    uint64_t feature_control_bits = 0;
 155    uint64_t *val;
 156
 157    cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
 158    if (ecx & CPUID_EXT_VMX) {
 159        feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 160    }
 161
 162    if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
 163        (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
 164        (env->mcg_cap & MCG_LMCE_P)) {
 165        feature_control_bits |= FEATURE_CONTROL_LMCE;
 166    }
 167
 168    if (!feature_control_bits) {
 169        return;
 170    }
 171
 172    val = g_malloc(sizeof(*val));
 173    *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
 174    fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
 175}
 176