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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/module.h"
24#include "hw/intc/arm_gicv3_its_common.h"
25#include "hw/qdev-properties.h"
26#include "sysemu/runstate.h"
27#include "sysemu/kvm.h"
28#include "kvm_arm.h"
29#include "migration/blocker.h"
30
31#define TYPE_KVM_ARM_ITS "arm-its-kvm"
32#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
33#define KVM_ARM_ITS_CLASS(klass) \
34 OBJECT_CLASS_CHECK(KVMARMITSClass, (klass), TYPE_KVM_ARM_ITS)
35#define KVM_ARM_ITS_GET_CLASS(obj) \
36 OBJECT_GET_CLASS(KVMARMITSClass, (obj), TYPE_KVM_ARM_ITS)
37
38typedef struct KVMARMITSClass {
39 GICv3ITSCommonClass parent_class;
40 void (*parent_reset)(DeviceState *dev);
41} KVMARMITSClass;
42
43
44static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
45{
46 struct kvm_msi msi;
47
48 if (unlikely(!s->translater_gpa_known)) {
49 MemoryRegion *mr = &s->iomem_its_translation;
50 MemoryRegionSection mrs;
51
52 mrs = memory_region_find(mr, 0, 1);
53 memory_region_unref(mrs.mr);
54 s->gits_translater_gpa = mrs.offset_within_address_space + 0x40;
55 s->translater_gpa_known = true;
56 }
57
58 msi.address_lo = extract64(s->gits_translater_gpa, 0, 32);
59 msi.address_hi = extract64(s->gits_translater_gpa, 32, 32);
60 msi.data = le32_to_cpu(value);
61 msi.flags = KVM_MSI_VALID_DEVID;
62 msi.devid = devid;
63 memset(msi.pad, 0, sizeof(msi.pad));
64
65 return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
66}
67
68
69
70
71
72
73
74static void vm_change_state_handler(void *opaque, int running,
75 RunState state)
76{
77 GICv3ITSState *s = (GICv3ITSState *)opaque;
78 Error *err = NULL;
79
80 if (running) {
81 return;
82 }
83
84 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
85 KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
86 if (err) {
87 error_report_err(err);
88 }
89}
90
91static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
92{
93 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
94 Error *local_err = NULL;
95
96 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
97 if (s->dev_fd < 0) {
98 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
99 return;
100 }
101
102
103 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
104 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
105
106
107 kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
108 KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
109
110 gicv3_its_init_mmio(s, NULL);
111
112 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
113 GITS_CTLR)) {
114 error_setg(&s->migration_blocker, "This operating system kernel "
115 "does not support vITS migration");
116 migrate_add_blocker(s->migration_blocker, &local_err);
117 if (local_err) {
118 error_propagate(errp, local_err);
119 error_free(s->migration_blocker);
120 return;
121 }
122 } else {
123 qemu_add_vm_change_state_handler(vm_change_state_handler, s);
124 }
125
126 kvm_msi_use_devid = true;
127 kvm_gsi_direct_mapping = false;
128 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
129}
130
131
132
133
134
135
136
137static void kvm_arm_its_pre_save(GICv3ITSState *s)
138{
139 int i;
140
141 for (i = 0; i < 8; i++) {
142 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
143 GITS_BASER + i * 8, &s->baser[i], false,
144 &error_abort);
145 }
146
147 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
148 GITS_CTLR, &s->ctlr, false, &error_abort);
149
150 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
151 GITS_CBASER, &s->cbaser, false, &error_abort);
152
153 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
154 GITS_CREADR, &s->creadr, false, &error_abort);
155
156 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
157 GITS_CWRITER, &s->cwriter, false, &error_abort);
158
159 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
160 GITS_IIDR, &s->iidr, false, &error_abort);
161}
162
163
164
165
166static void kvm_arm_its_post_load(GICv3ITSState *s)
167{
168 int i;
169
170 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
171 GITS_IIDR, &s->iidr, true, &error_abort);
172
173
174
175
176
177 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
178 GITS_CBASER, &s->cbaser, true, &error_abort);
179
180 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
181 GITS_CREADR, &s->creadr, true, &error_abort);
182
183 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
184 GITS_CWRITER, &s->cwriter, true, &error_abort);
185
186
187 for (i = 0; i < 8; i++) {
188 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
189 GITS_BASER + i * 8, &s->baser[i], true,
190 &error_abort);
191 }
192
193 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
194 KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
195 &error_abort);
196
197 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
198 GITS_CTLR, &s->ctlr, true, &error_abort);
199}
200
201static void kvm_arm_its_reset(DeviceState *dev)
202{
203 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
204 KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
205 int i;
206
207 c->parent_reset(dev);
208
209 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
210 KVM_DEV_ARM_ITS_CTRL_RESET)) {
211 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
212 KVM_DEV_ARM_ITS_CTRL_RESET, NULL, true, &error_abort);
213 return;
214 }
215
216 warn_report("ITS KVM: full reset is not supported by the host kernel");
217
218 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
219 GITS_CTLR)) {
220 return;
221 }
222
223 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
224 GITS_CTLR, &s->ctlr, true, &error_abort);
225
226 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
227 GITS_CBASER, &s->cbaser, true, &error_abort);
228
229 for (i = 0; i < 8; i++) {
230 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
231 GITS_BASER + i * 8, &s->baser[i], true,
232 &error_abort);
233 }
234}
235
236static Property kvm_arm_its_props[] = {
237 DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
238 GICv3State *),
239 DEFINE_PROP_END_OF_LIST(),
240};
241
242static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
243{
244 DeviceClass *dc = DEVICE_CLASS(klass);
245 GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
246 KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
247
248 dc->realize = kvm_arm_its_realize;
249 dc->props = kvm_arm_its_props;
250 device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
251 icc->send_msi = kvm_its_send_msi;
252 icc->pre_save = kvm_arm_its_pre_save;
253 icc->post_load = kvm_arm_its_post_load;
254}
255
256static const TypeInfo kvm_arm_its_info = {
257 .name = TYPE_KVM_ARM_ITS,
258 .parent = TYPE_ARM_GICV3_ITS_COMMON,
259 .instance_size = sizeof(GICv3ITSState),
260 .class_init = kvm_arm_its_class_init,
261 .class_size = sizeof(KVMARMITSClass),
262};
263
264static void kvm_arm_its_register_types(void)
265{
266 type_register_static(&kvm_arm_its_info);
267}
268
269type_init(kvm_arm_its_register_types)
270