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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "hw/pci/pci.h"
28#include "hw/hw.h"
29#include "hw/pci/msi.h"
30#include "qemu/timer.h"
31#include "qemu/main-loop.h"
32#include "qemu/module.h"
33#include "qapi/visitor.h"
34
35#define TYPE_PCI_EDU_DEVICE "edu"
36#define EDU(obj) OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE)
37
38#define FACT_IRQ 0x00000001
39#define DMA_IRQ 0x00000100
40
41#define DMA_START 0x40000
42#define DMA_SIZE 4096
43
44typedef struct {
45 PCIDevice pdev;
46 MemoryRegion mmio;
47
48 QemuThread thread;
49 QemuMutex thr_mutex;
50 QemuCond thr_cond;
51 bool stopping;
52
53 uint32_t addr4;
54 uint32_t fact;
55#define EDU_STATUS_COMPUTING 0x01
56#define EDU_STATUS_IRQFACT 0x80
57 uint32_t status;
58
59 uint32_t irq_status;
60
61#define EDU_DMA_RUN 0x1
62#define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
63# define EDU_DMA_FROM_PCI 0
64# define EDU_DMA_TO_PCI 1
65#define EDU_DMA_IRQ 0x4
66 struct dma_state {
67 dma_addr_t src;
68 dma_addr_t dst;
69 dma_addr_t cnt;
70 dma_addr_t cmd;
71 } dma;
72 QEMUTimer dma_timer;
73 char dma_buf[DMA_SIZE];
74 uint64_t dma_mask;
75} EduState;
76
77static bool edu_msi_enabled(EduState *edu)
78{
79 return msi_enabled(&edu->pdev);
80}
81
82static void edu_raise_irq(EduState *edu, uint32_t val)
83{
84 edu->irq_status |= val;
85 if (edu->irq_status) {
86 if (edu_msi_enabled(edu)) {
87 msi_notify(&edu->pdev, 0);
88 } else {
89 pci_set_irq(&edu->pdev, 1);
90 }
91 }
92}
93
94static void edu_lower_irq(EduState *edu, uint32_t val)
95{
96 edu->irq_status &= ~val;
97
98 if (!edu->irq_status && !edu_msi_enabled(edu)) {
99 pci_set_irq(&edu->pdev, 0);
100 }
101}
102
103static bool within(uint64_t addr, uint64_t start, uint64_t end)
104{
105 return start <= addr && addr < end;
106}
107
108static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
109 uint64_t size2)
110{
111 uint64_t end1 = addr + size1;
112 uint64_t end2 = start + size2;
113
114 if (within(addr, start, end2) &&
115 end1 > addr && within(end1, start, end2)) {
116 return;
117 }
118
119 hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
120 " out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
121 addr, end1 - 1, start, end2 - 1);
122}
123
124static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
125{
126 dma_addr_t res = addr & edu->dma_mask;
127
128 if (addr != res) {
129 printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
130 }
131
132 return res;
133}
134
135static void edu_dma_timer(void *opaque)
136{
137 EduState *edu = opaque;
138 bool raise_irq = false;
139
140 if (!(edu->dma.cmd & EDU_DMA_RUN)) {
141 return;
142 }
143
144 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
145 uint64_t dst = edu->dma.dst;
146 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
147 dst -= DMA_START;
148 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
149 edu->dma_buf + dst, edu->dma.cnt);
150 } else {
151 uint64_t src = edu->dma.src;
152 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
153 src -= DMA_START;
154 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
155 edu->dma_buf + src, edu->dma.cnt);
156 }
157
158 edu->dma.cmd &= ~EDU_DMA_RUN;
159 if (edu->dma.cmd & EDU_DMA_IRQ) {
160 raise_irq = true;
161 }
162
163 if (raise_irq) {
164 edu_raise_irq(edu, DMA_IRQ);
165 }
166}
167
168static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,
169 bool timer)
170{
171 if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
172 return;
173 }
174
175 if (write) {
176 *dma = *val;
177 } else {
178 *val = *dma;
179 }
180
181 if (timer) {
182 timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
183 }
184}
185
186static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
187{
188 EduState *edu = opaque;
189 uint64_t val = ~0ULL;
190
191 if (addr < 0x80 && size != 4) {
192 return val;
193 }
194
195 if (addr >= 0x80 && size != 4 && size != 8) {
196 return val;
197 }
198
199 switch (addr) {
200 case 0x00:
201 val = 0x010000edu;
202 break;
203 case 0x04:
204 val = edu->addr4;
205 break;
206 case 0x08:
207 qemu_mutex_lock(&edu->thr_mutex);
208 val = edu->fact;
209 qemu_mutex_unlock(&edu->thr_mutex);
210 break;
211 case 0x20:
212 val = atomic_read(&edu->status);
213 break;
214 case 0x24:
215 val = edu->irq_status;
216 break;
217 case 0x80:
218 dma_rw(edu, false, &val, &edu->dma.src, false);
219 break;
220 case 0x88:
221 dma_rw(edu, false, &val, &edu->dma.dst, false);
222 break;
223 case 0x90:
224 dma_rw(edu, false, &val, &edu->dma.cnt, false);
225 break;
226 case 0x98:
227 dma_rw(edu, false, &val, &edu->dma.cmd, false);
228 break;
229 }
230
231 return val;
232}
233
234static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
235 unsigned size)
236{
237 EduState *edu = opaque;
238
239 if (addr < 0x80 && size != 4) {
240 return;
241 }
242
243 if (addr >= 0x80 && size != 4 && size != 8) {
244 return;
245 }
246
247 switch (addr) {
248 case 0x04:
249 edu->addr4 = ~val;
250 break;
251 case 0x08:
252 if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
253 break;
254 }
255
256
257
258 qemu_mutex_lock(&edu->thr_mutex);
259 edu->fact = val;
260 atomic_or(&edu->status, EDU_STATUS_COMPUTING);
261 qemu_cond_signal(&edu->thr_cond);
262 qemu_mutex_unlock(&edu->thr_mutex);
263 break;
264 case 0x20:
265 if (val & EDU_STATUS_IRQFACT) {
266 atomic_or(&edu->status, EDU_STATUS_IRQFACT);
267 } else {
268 atomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
269 }
270 break;
271 case 0x60:
272 edu_raise_irq(edu, val);
273 break;
274 case 0x64:
275 edu_lower_irq(edu, val);
276 break;
277 case 0x80:
278 dma_rw(edu, true, &val, &edu->dma.src, false);
279 break;
280 case 0x88:
281 dma_rw(edu, true, &val, &edu->dma.dst, false);
282 break;
283 case 0x90:
284 dma_rw(edu, true, &val, &edu->dma.cnt, false);
285 break;
286 case 0x98:
287 if (!(val & EDU_DMA_RUN)) {
288 break;
289 }
290 dma_rw(edu, true, &val, &edu->dma.cmd, true);
291 break;
292 }
293}
294
295static const MemoryRegionOps edu_mmio_ops = {
296 .read = edu_mmio_read,
297 .write = edu_mmio_write,
298 .endianness = DEVICE_NATIVE_ENDIAN,
299 .valid = {
300 .min_access_size = 4,
301 .max_access_size = 8,
302 },
303 .impl = {
304 .min_access_size = 4,
305 .max_access_size = 8,
306 },
307
308};
309
310
311
312
313
314static void *edu_fact_thread(void *opaque)
315{
316 EduState *edu = opaque;
317
318 while (1) {
319 uint32_t val, ret = 1;
320
321 qemu_mutex_lock(&edu->thr_mutex);
322 while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
323 !edu->stopping) {
324 qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
325 }
326
327 if (edu->stopping) {
328 qemu_mutex_unlock(&edu->thr_mutex);
329 break;
330 }
331
332 val = edu->fact;
333 qemu_mutex_unlock(&edu->thr_mutex);
334
335 while (val > 0) {
336 ret *= val--;
337 }
338
339
340
341
342
343
344 qemu_mutex_lock(&edu->thr_mutex);
345 edu->fact = ret;
346 qemu_mutex_unlock(&edu->thr_mutex);
347 atomic_and(&edu->status, ~EDU_STATUS_COMPUTING);
348
349 if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
350 qemu_mutex_lock_iothread();
351 edu_raise_irq(edu, FACT_IRQ);
352 qemu_mutex_unlock_iothread();
353 }
354 }
355
356 return NULL;
357}
358
359static void pci_edu_realize(PCIDevice *pdev, Error **errp)
360{
361 EduState *edu = EDU(pdev);
362 uint8_t *pci_conf = pdev->config;
363
364 pci_config_set_interrupt_pin(pci_conf, 1);
365
366 if (msi_init(pdev, 0, 1, true, false, errp)) {
367 return;
368 }
369
370 timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);
371
372 qemu_mutex_init(&edu->thr_mutex);
373 qemu_cond_init(&edu->thr_cond);
374 qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
375 edu, QEMU_THREAD_JOINABLE);
376
377 memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
378 "edu-mmio", 1 * MiB);
379 pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
380}
381
382static void pci_edu_uninit(PCIDevice *pdev)
383{
384 EduState *edu = EDU(pdev);
385
386 qemu_mutex_lock(&edu->thr_mutex);
387 edu->stopping = true;
388 qemu_mutex_unlock(&edu->thr_mutex);
389 qemu_cond_signal(&edu->thr_cond);
390 qemu_thread_join(&edu->thread);
391
392 qemu_cond_destroy(&edu->thr_cond);
393 qemu_mutex_destroy(&edu->thr_mutex);
394
395 timer_del(&edu->dma_timer);
396 msi_uninit(pdev);
397}
398
399static void edu_obj_uint64(Object *obj, Visitor *v, const char *name,
400 void *opaque, Error **errp)
401{
402 uint64_t *val = opaque;
403
404 visit_type_uint64(v, name, val, errp);
405}
406
407static void edu_instance_init(Object *obj)
408{
409 EduState *edu = EDU(obj);
410
411 edu->dma_mask = (1UL << 28) - 1;
412 object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64,
413 edu_obj_uint64, NULL, &edu->dma_mask, NULL);
414}
415
416static void edu_class_init(ObjectClass *class, void *data)
417{
418 DeviceClass *dc = DEVICE_CLASS(class);
419 PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
420
421 k->realize = pci_edu_realize;
422 k->exit = pci_edu_uninit;
423 k->vendor_id = PCI_VENDOR_ID_QEMU;
424 k->device_id = 0x11e8;
425 k->revision = 0x10;
426 k->class_id = PCI_CLASS_OTHERS;
427 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
428}
429
430static void pci_edu_register_types(void)
431{
432 static InterfaceInfo interfaces[] = {
433 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
434 { },
435 };
436 static const TypeInfo edu_info = {
437 .name = TYPE_PCI_EDU_DEVICE,
438 .parent = TYPE_PCI_DEVICE,
439 .instance_size = sizeof(EduState),
440 .instance_init = edu_instance_init,
441 .class_init = edu_class_init,
442 .interfaces = interfaces,
443 };
444
445 type_register_static(&edu_info);
446}
447type_init(pci_edu_register_types)
448
