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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "qemu/log.h"
23#include "qemu/module.h"
24#include "qapi/error.h"
25#include "cpu.h"
26#include "exec/exec-all.h"
27#include "hw/misc/mips_itu.h"
28#include "hw/qdev-properties.h"
29
30#define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
31
32
33#define ITC_STORAGE_ADDRSPACE_SZ 0x1000
34
35#define ITC_FIFO_NUM_MAX 16
36#define ITC_SEMAPH_NUM_MAX 16
37#define ITC_AM1_NUMENTRIES_OFS 20
38
39#define ITC_CELL_PV_MAX_VAL 0xFFFF
40
41#define ITC_CELL_TAG_FIFO_DEPTH 28
42#define ITC_CELL_TAG_FIFO_PTR 18
43#define ITC_CELL_TAG_FIFO 17
44#define ITC_CELL_TAG_T 16
45#define ITC_CELL_TAG_F 1
46#define ITC_CELL_TAG_E 0
47
48#define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
49#define ITC_AM0_EN_MASK 0x1
50
51#define ITC_AM1_ADDR_MASK_MASK 0x1FC00
52#define ITC_AM1_ENTRY_GRAIN_MASK 0x7
53
54typedef enum ITCView {
55 ITCVIEW_BYPASS = 0,
56 ITCVIEW_CONTROL = 1,
57 ITCVIEW_EF_SYNC = 2,
58 ITCVIEW_EF_TRY = 3,
59 ITCVIEW_PV_SYNC = 4,
60 ITCVIEW_PV_TRY = 5,
61 ITCVIEW_PV_ICR0 = 15,
62} ITCView;
63
64#define ITC_ICR0_CELL_NUM 16
65#define ITC_ICR0_BLK_GRAIN 8
66#define ITC_ICR0_BLK_GRAIN_MASK 0x7
67#define ITC_ICR0_ERR_AXI 2
68#define ITC_ICR0_ERR_PARITY 1
69#define ITC_ICR0_ERR_EXEC 0
70
71MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
72{
73 return &itu->tag_io;
74}
75
76static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
77{
78 MIPSITUState *tag = (MIPSITUState *)opaque;
79 uint64_t index = addr >> 3;
80
81 if (index >= ITC_ADDRESSMAP_NUM) {
82 qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
83 return 0;
84 }
85
86 return tag->ITCAddressMap[index];
87}
88
89void itc_reconfigure(MIPSITUState *tag)
90{
91 uint64_t *am = &tag->ITCAddressMap[0];
92 MemoryRegion *mr = &tag->storage_io;
93 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
94 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
95 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
96
97 if (tag->saar_present) {
98 address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
99 size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
100 is_enabled = *(uint64_t *) tag->saar & 1;
101 }
102
103 memory_region_transaction_begin();
104 if (!(size & (size - 1))) {
105 memory_region_set_size(mr, size);
106 }
107 memory_region_set_address(mr, address);
108 memory_region_set_enabled(mr, is_enabled);
109 memory_region_transaction_commit();
110}
111
112static void itc_tag_write(void *opaque, hwaddr addr,
113 uint64_t data, unsigned size)
114{
115 MIPSITUState *tag = (MIPSITUState *)opaque;
116 uint64_t *am = &tag->ITCAddressMap[0];
117 uint64_t am_old, mask;
118 uint64_t index = addr >> 3;
119
120 switch (index) {
121 case 0:
122 mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
123 break;
124 case 1:
125 mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
126 break;
127 default:
128 qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
129 return;
130 }
131
132 am_old = am[index];
133 am[index] = (data & mask) | (am_old & ~mask);
134 if (am_old != am[index]) {
135 itc_reconfigure(tag);
136 }
137}
138
139static const MemoryRegionOps itc_tag_ops = {
140 .read = itc_tag_read,
141 .write = itc_tag_write,
142 .impl = {
143 .max_access_size = 8,
144 },
145 .endianness = DEVICE_NATIVE_ENDIAN,
146};
147
148static inline uint32_t get_num_cells(MIPSITUState *s)
149{
150 return s->num_fifo + s->num_semaphores;
151}
152
153static inline ITCView get_itc_view(hwaddr addr)
154{
155 return (addr >> 3) & 0xf;
156}
157
158static inline int get_cell_stride_shift(const MIPSITUState *s)
159{
160
161 if (s->saar_present) {
162 return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
163 ITC_ICR0_BLK_GRAIN_MASK);
164 } else {
165 return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
166 }
167}
168
169static inline ITCStorageCell *get_cell(MIPSITUState *s,
170 hwaddr addr)
171{
172 uint32_t cell_idx = addr >> get_cell_stride_shift(s);
173 uint32_t num_cells = get_num_cells(s);
174
175 if (cell_idx >= num_cells) {
176 cell_idx = num_cells - 1;
177 }
178
179 return &s->cell[cell_idx];
180}
181
182static void wake_blocked_threads(ITCStorageCell *c)
183{
184 CPUState *cs;
185 CPU_FOREACH(cs) {
186 if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
187 cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
188 }
189 }
190 c->blocked_threads = 0;
191}
192
193static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
194{
195 c->blocked_threads |= 1ULL << current_cpu->cpu_index;
196 current_cpu->halted = 1;
197 current_cpu->exception_index = EXCP_HLT;
198 cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
199}
200
201
202
203static inline uint64_t view_bypass_read(ITCStorageCell *c)
204{
205 if (c->tag.FIFO) {
206 return c->data[c->fifo_out];
207 } else {
208 return c->data[0];
209 }
210}
211
212static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
213{
214 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
215 int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
216 c->data[idx] = val;
217 }
218
219
220}
221
222
223
224static inline uint64_t view_control_read(ITCStorageCell *c)
225{
226 return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
227 (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
228 (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
229 (c->tag.T << ITC_CELL_TAG_T) |
230 (c->tag.E << ITC_CELL_TAG_E) |
231 (c->tag.F << ITC_CELL_TAG_F);
232}
233
234static inline void view_control_write(ITCStorageCell *c, uint64_t val)
235{
236 c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
237 c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
238 c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
239
240 if (c->tag.E) {
241 c->tag.FIFOPtr = 0;
242 }
243}
244
245
246
247static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
248{
249 uint64_t ret = 0;
250
251 if (!c->tag.FIFO) {
252 return 0;
253 }
254
255 c->tag.F = 0;
256
257 if (blocking && c->tag.E) {
258 block_thread_and_exit(c);
259 }
260
261 if (c->blocked_threads) {
262 wake_blocked_threads(c);
263 }
264
265 if (c->tag.FIFOPtr > 0) {
266 ret = c->data[c->fifo_out];
267 c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
268 c->tag.FIFOPtr--;
269 }
270
271 if (c->tag.FIFOPtr == 0) {
272 c->tag.E = 1;
273 }
274
275 return ret;
276}
277
278static uint64_t view_ef_sync_read(ITCStorageCell *c)
279{
280 return view_ef_common_read(c, true);
281}
282
283static uint64_t view_ef_try_read(ITCStorageCell *c)
284{
285 return view_ef_common_read(c, false);
286}
287
288static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
289 bool blocking)
290{
291 if (!c->tag.FIFO) {
292 return;
293 }
294
295 c->tag.E = 0;
296
297 if (blocking && c->tag.F) {
298 block_thread_and_exit(c);
299 }
300
301 if (c->blocked_threads) {
302 wake_blocked_threads(c);
303 }
304
305 if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
306 int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
307 c->data[idx] = val;
308 c->tag.FIFOPtr++;
309 }
310
311 if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
312 c->tag.F = 1;
313 }
314}
315
316static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
317{
318 view_ef_common_write(c, val, true);
319}
320
321static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
322{
323 view_ef_common_write(c, val, false);
324}
325
326
327
328static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
329{
330 uint64_t ret = c->data[0];
331
332 if (c->tag.FIFO) {
333 return 0;
334 }
335
336 if (c->data[0] > 0) {
337 c->data[0]--;
338 } else if (blocking) {
339 block_thread_and_exit(c);
340 }
341
342 return ret;
343}
344
345static uint64_t view_pv_sync_read(ITCStorageCell *c)
346{
347 return view_pv_common_read(c, true);
348}
349
350static uint64_t view_pv_try_read(ITCStorageCell *c)
351{
352 return view_pv_common_read(c, false);
353}
354
355static inline void view_pv_common_write(ITCStorageCell *c)
356{
357 if (c->tag.FIFO) {
358 return;
359 }
360
361 if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
362 c->data[0]++;
363 }
364
365 if (c->blocked_threads) {
366 wake_blocked_threads(c);
367 }
368}
369
370static void view_pv_sync_write(ITCStorageCell *c)
371{
372 view_pv_common_write(c);
373}
374
375static void view_pv_try_write(ITCStorageCell *c)
376{
377 view_pv_common_write(c);
378}
379
380static void raise_exception(int excp)
381{
382 current_cpu->exception_index = excp;
383 cpu_loop_exit(current_cpu);
384}
385
386static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
387{
388 MIPSITUState *s = (MIPSITUState *)opaque;
389 ITCStorageCell *cell = get_cell(s, addr);
390 ITCView view = get_itc_view(addr);
391 uint64_t ret = -1;
392
393 switch (size) {
394 case 1:
395 case 2:
396 s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
397 raise_exception(EXCP_DBE);
398 return 0;
399 }
400
401 switch (view) {
402 case ITCVIEW_BYPASS:
403 ret = view_bypass_read(cell);
404 break;
405 case ITCVIEW_CONTROL:
406 ret = view_control_read(cell);
407 break;
408 case ITCVIEW_EF_SYNC:
409 ret = view_ef_sync_read(cell);
410 break;
411 case ITCVIEW_EF_TRY:
412 ret = view_ef_try_read(cell);
413 break;
414 case ITCVIEW_PV_SYNC:
415 ret = view_pv_sync_read(cell);
416 break;
417 case ITCVIEW_PV_TRY:
418 ret = view_pv_try_read(cell);
419 break;
420 case ITCVIEW_PV_ICR0:
421 ret = s->icr0;
422 break;
423 default:
424 qemu_log_mask(LOG_GUEST_ERROR,
425 "itc_storage_read: Bad ITC View %d\n", (int)view);
426 break;
427 }
428
429 return ret;
430}
431
432static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
433 unsigned size)
434{
435 MIPSITUState *s = (MIPSITUState *)opaque;
436 ITCStorageCell *cell = get_cell(s, addr);
437 ITCView view = get_itc_view(addr);
438
439 switch (size) {
440 case 1:
441 case 2:
442 s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
443 raise_exception(EXCP_DBE);
444 return;
445 }
446
447 switch (view) {
448 case ITCVIEW_BYPASS:
449 view_bypass_write(cell, data);
450 break;
451 case ITCVIEW_CONTROL:
452 view_control_write(cell, data);
453 break;
454 case ITCVIEW_EF_SYNC:
455 view_ef_sync_write(cell, data);
456 break;
457 case ITCVIEW_EF_TRY:
458 view_ef_try_write(cell, data);
459 break;
460 case ITCVIEW_PV_SYNC:
461 view_pv_sync_write(cell);
462 break;
463 case ITCVIEW_PV_TRY:
464 view_pv_try_write(cell);
465 break;
466 case ITCVIEW_PV_ICR0:
467 if (data & 0x7) {
468
469 s->icr0 &= ~(data & 0x7);
470 }
471
472 s->icr0 &= ~0x700;
473 s->icr0 |= data & 0x700;
474 break;
475 default:
476 qemu_log_mask(LOG_GUEST_ERROR,
477 "itc_storage_write: Bad ITC View %d\n", (int)view);
478 break;
479 }
480
481}
482
483static const MemoryRegionOps itc_storage_ops = {
484 .read = itc_storage_read,
485 .write = itc_storage_write,
486 .endianness = DEVICE_NATIVE_ENDIAN,
487};
488
489static void itc_reset_cells(MIPSITUState *s)
490{
491 int i;
492
493 memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
494
495 for (i = 0; i < s->num_fifo; i++) {
496 s->cell[i].tag.E = 1;
497 s->cell[i].tag.FIFO = 1;
498 s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
499 }
500}
501
502static void mips_itu_init(Object *obj)
503{
504 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
505 MIPSITUState *s = MIPS_ITU(obj);
506
507 memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
508 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
509 sysbus_init_mmio(sbd, &s->storage_io);
510
511 memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
512 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
513}
514
515static void mips_itu_realize(DeviceState *dev, Error **errp)
516{
517 MIPSITUState *s = MIPS_ITU(dev);
518
519 if (s->num_fifo > ITC_FIFO_NUM_MAX) {
520 error_setg(errp, "Exceed maximum number of FIFO cells: %d",
521 s->num_fifo);
522 return;
523 }
524 if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
525 error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
526 s->num_semaphores);
527 return;
528 }
529
530 s->cell = g_new(ITCStorageCell, get_num_cells(s));
531}
532
533static void mips_itu_reset(DeviceState *dev)
534{
535 MIPSITUState *s = MIPS_ITU(dev);
536
537 if (s->saar_present) {
538 *(uint64_t *) s->saar = 0x11 << 1;
539 s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
540 } else {
541 s->ITCAddressMap[0] = 0;
542 s->ITCAddressMap[1] =
543 ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
544 (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
545 }
546 itc_reconfigure(s);
547
548 itc_reset_cells(s);
549}
550
551static Property mips_itu_properties[] = {
552 DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
553 ITC_FIFO_NUM_MAX),
554 DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
555 ITC_SEMAPH_NUM_MAX),
556 DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false),
557 DEFINE_PROP_END_OF_LIST(),
558};
559
560static void mips_itu_class_init(ObjectClass *klass, void *data)
561{
562 DeviceClass *dc = DEVICE_CLASS(klass);
563
564 dc->props = mips_itu_properties;
565 dc->realize = mips_itu_realize;
566 dc->reset = mips_itu_reset;
567}
568
569static const TypeInfo mips_itu_info = {
570 .name = TYPE_MIPS_ITU,
571 .parent = TYPE_SYS_BUS_DEVICE,
572 .instance_size = sizeof(MIPSITUState),
573 .instance_init = mips_itu_init,
574 .class_init = mips_itu_class_init,
575};
576
577static void mips_itu_register_types(void)
578{
579 type_register_static(&mips_itu_info);
580}
581
582type_init(mips_itu_register_types)
583
