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25#include "qemu/osdep.h"
26#include "qemu-common.h"
27#include "sysemu/sysemu.h"
28#include "sysemu/dma.h"
29#include "sysemu/reset.h"
30#include "hw/boards.h"
31#include "hw/nvram/fw_cfg.h"
32#include "hw/qdev-properties.h"
33#include "hw/sysbus.h"
34#include "migration/qemu-file-types.h"
35#include "migration/vmstate.h"
36#include "trace.h"
37#include "qemu/error-report.h"
38#include "qemu/option.h"
39#include "qemu/config-file.h"
40#include "qemu/cutils.h"
41#include "qapi/error.h"
42
43#define FW_CFG_FILE_SLOTS_DFLT 0x20
44
45
46#define FW_CFG_VERSION 0x01
47#define FW_CFG_VERSION_DMA 0x02
48
49
50#define FW_CFG_DMA_CTL_ERROR 0x01
51#define FW_CFG_DMA_CTL_READ 0x02
52#define FW_CFG_DMA_CTL_SKIP 0x04
53#define FW_CFG_DMA_CTL_SELECT 0x08
54#define FW_CFG_DMA_CTL_WRITE 0x10
55
56#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL
57
58struct FWCfgEntry {
59 uint32_t len;
60 bool allow_write;
61 uint8_t *data;
62 void *callback_opaque;
63 FWCfgCallback select_cb;
64 FWCfgWriteCallback write_cb;
65};
66
67
68
69
70
71
72
73
74
75static const char *key_name(uint16_t key)
76{
77 static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = {
78 [FW_CFG_SIGNATURE] = "signature",
79 [FW_CFG_ID] = "id",
80 [FW_CFG_UUID] = "uuid",
81 [FW_CFG_RAM_SIZE] = "ram_size",
82 [FW_CFG_NOGRAPHIC] = "nographic",
83 [FW_CFG_NB_CPUS] = "nb_cpus",
84 [FW_CFG_MACHINE_ID] = "machine_id",
85 [FW_CFG_KERNEL_ADDR] = "kernel_addr",
86 [FW_CFG_KERNEL_SIZE] = "kernel_size",
87 [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline",
88 [FW_CFG_INITRD_ADDR] = "initrd_addr",
89 [FW_CFG_INITRD_SIZE] = "initdr_size",
90 [FW_CFG_BOOT_DEVICE] = "boot_device",
91 [FW_CFG_NUMA] = "numa",
92 [FW_CFG_BOOT_MENU] = "boot_menu",
93 [FW_CFG_MAX_CPUS] = "max_cpus",
94 [FW_CFG_KERNEL_ENTRY] = "kernel_entry",
95 [FW_CFG_KERNEL_DATA] = "kernel_data",
96 [FW_CFG_INITRD_DATA] = "initrd_data",
97 [FW_CFG_CMDLINE_ADDR] = "cmdline_addr",
98 [FW_CFG_CMDLINE_SIZE] = "cmdline_size",
99 [FW_CFG_CMDLINE_DATA] = "cmdline_data",
100 [FW_CFG_SETUP_ADDR] = "setup_addr",
101 [FW_CFG_SETUP_SIZE] = "setup_size",
102 [FW_CFG_SETUP_DATA] = "setup_data",
103 [FW_CFG_FILE_DIR] = "file_dir",
104 };
105
106 if (key & FW_CFG_ARCH_LOCAL) {
107 return fw_cfg_arch_key_name(key);
108 }
109 if (key < FW_CFG_FILE_FIRST) {
110 return fw_cfg_wellknown_keys[key];
111 }
112
113 return NULL;
114}
115
116static inline const char *trace_key_name(uint16_t key)
117{
118 const char *name = key_name(key);
119
120 return name ? name : "unknown";
121}
122
123#define JPG_FILE 0
124#define BMP_FILE 1
125
126static char *read_splashfile(char *filename, gsize *file_sizep,
127 int *file_typep)
128{
129 GError *err = NULL;
130 gchar *content;
131 int file_type;
132 unsigned int filehead;
133 int bmp_bpp;
134
135 if (!g_file_get_contents(filename, &content, file_sizep, &err)) {
136 error_report("failed to read splash file '%s': %s",
137 filename, err->message);
138 g_error_free(err);
139 return NULL;
140 }
141
142
143 if (*file_sizep < 30) {
144 goto error;
145 }
146
147
148 filehead = lduw_le_p(content);
149 if (filehead == 0xd8ff) {
150 file_type = JPG_FILE;
151 } else if (filehead == 0x4d42) {
152 file_type = BMP_FILE;
153 } else {
154 goto error;
155 }
156
157
158 if (file_type == BMP_FILE) {
159 bmp_bpp = lduw_le_p(&content[28]);
160 if (bmp_bpp != 24) {
161 goto error;
162 }
163 }
164
165
166 *file_typep = file_type;
167
168 return content;
169
170error:
171 error_report("splash file '%s' format not recognized; must be JPEG "
172 "or 24 bit BMP", filename);
173 g_free(content);
174 return NULL;
175}
176
177static void fw_cfg_bootsplash(FWCfgState *s)
178{
179 const char *boot_splash_filename = NULL;
180 const char *boot_splash_time = NULL;
181 char *filename, *file_data;
182 gsize file_size;
183 int file_type;
184
185
186 QemuOptsList *plist = qemu_find_opts("boot-opts");
187 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
188 boot_splash_filename = qemu_opt_get(opts, "splash");
189 boot_splash_time = qemu_opt_get(opts, "splash-time");
190
191
192 if (boot_splash_time) {
193 int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1);
194 uint16_t bst_le16;
195
196
197 if (bst_val < 0 || bst_val > 0xffff) {
198 error_report("splash-time is invalid,"
199 "it should be a value between 0 and 65535");
200 exit(1);
201 }
202
203 bst_le16 = cpu_to_le16(bst_val);
204 fw_cfg_add_file(s, "etc/boot-menu-wait",
205 g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16);
206 }
207
208
209 if (boot_splash_filename) {
210 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
211 if (filename == NULL) {
212 error_report("failed to find file '%s'", boot_splash_filename);
213 return;
214 }
215
216
217 file_data = read_splashfile(filename, &file_size, &file_type);
218 if (file_data == NULL) {
219 g_free(filename);
220 return;
221 }
222 g_free(boot_splash_filedata);
223 boot_splash_filedata = (uint8_t *)file_data;
224
225
226 if (file_type == JPG_FILE) {
227 fw_cfg_add_file(s, "bootsplash.jpg",
228 boot_splash_filedata, file_size);
229 } else {
230 fw_cfg_add_file(s, "bootsplash.bmp",
231 boot_splash_filedata, file_size);
232 }
233 g_free(filename);
234 }
235}
236
237static void fw_cfg_reboot(FWCfgState *s)
238{
239 const char *reboot_timeout = NULL;
240 uint64_t rt_val = -1;
241 uint32_t rt_le32;
242
243
244 QemuOptsList *plist = qemu_find_opts("boot-opts");
245 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
246 reboot_timeout = qemu_opt_get(opts, "reboot-timeout");
247
248 if (reboot_timeout) {
249 rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1);
250
251
252 if (rt_val > 0xffff && rt_val != (uint64_t)-1) {
253 error_report("reboot timeout is invalid,"
254 "it should be a value between -1 and 65535");
255 exit(1);
256 }
257 }
258
259 rt_le32 = cpu_to_le32(rt_val);
260 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4);
261}
262
263static void fw_cfg_write(FWCfgState *s, uint8_t value)
264{
265
266}
267
268static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
269{
270 return s->file_slots;
271}
272
273
274static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
275{
276 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
277}
278
279static int fw_cfg_select(FWCfgState *s, uint16_t key)
280{
281 int arch, ret;
282 FWCfgEntry *e;
283
284 s->cur_offset = 0;
285 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
286 s->cur_entry = FW_CFG_INVALID;
287 ret = 0;
288 } else {
289 s->cur_entry = key;
290 ret = 1;
291
292 arch = !!(key & FW_CFG_ARCH_LOCAL);
293 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
294 if (e->select_cb) {
295 e->select_cb(e->callback_opaque);
296 }
297 }
298
299 trace_fw_cfg_select(s, key, trace_key_name(key), ret);
300 return ret;
301}
302
303static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
304{
305 FWCfgState *s = opaque;
306 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
307 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
308 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
309 uint64_t value = 0;
310
311 assert(size > 0 && size <= sizeof(value));
312 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
313
314
315
316
317
318
319 do {
320 value = (value << 8) | e->data[s->cur_offset++];
321 } while (--size && s->cur_offset < e->len);
322
323
324
325
326 value <<= 8 * size;
327 }
328
329 trace_fw_cfg_read(s, value);
330 return value;
331}
332
333static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
334 uint64_t value, unsigned size)
335{
336 FWCfgState *s = opaque;
337 unsigned i = size;
338
339 do {
340 fw_cfg_write(s, value >> (8 * --i));
341 } while (i);
342}
343
344static void fw_cfg_dma_transfer(FWCfgState *s)
345{
346 dma_addr_t len;
347 FWCfgDmaAccess dma;
348 int arch;
349 FWCfgEntry *e;
350 int read = 0, write = 0;
351 dma_addr_t dma_addr;
352
353
354 dma_addr = s->dma_addr;
355 s->dma_addr = 0;
356
357 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
358 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
359 FW_CFG_DMA_CTL_ERROR);
360 return;
361 }
362
363 dma.address = be64_to_cpu(dma.address);
364 dma.length = be32_to_cpu(dma.length);
365 dma.control = be32_to_cpu(dma.control);
366
367 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
368 fw_cfg_select(s, dma.control >> 16);
369 }
370
371 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
372 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
373 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
374
375 if (dma.control & FW_CFG_DMA_CTL_READ) {
376 read = 1;
377 write = 0;
378 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
379 read = 0;
380 write = 1;
381 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
382 read = 0;
383 write = 0;
384 } else {
385 dma.length = 0;
386 }
387
388 dma.control = 0;
389
390 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
391 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
392 s->cur_offset >= e->len) {
393 len = dma.length;
394
395
396
397
398 if (read) {
399 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
400 dma.control |= FW_CFG_DMA_CTL_ERROR;
401 }
402 }
403 if (write) {
404 dma.control |= FW_CFG_DMA_CTL_ERROR;
405 }
406 } else {
407 if (dma.length <= (e->len - s->cur_offset)) {
408 len = dma.length;
409 } else {
410 len = (e->len - s->cur_offset);
411 }
412
413
414
415
416 if (read) {
417 if (dma_memory_write(s->dma_as, dma.address,
418 &e->data[s->cur_offset], len)) {
419 dma.control |= FW_CFG_DMA_CTL_ERROR;
420 }
421 }
422 if (write) {
423 if (!e->allow_write ||
424 len != dma.length ||
425 dma_memory_read(s->dma_as, dma.address,
426 &e->data[s->cur_offset], len)) {
427 dma.control |= FW_CFG_DMA_CTL_ERROR;
428 } else if (e->write_cb) {
429 e->write_cb(e->callback_opaque, s->cur_offset, len);
430 }
431 }
432
433 s->cur_offset += len;
434 }
435
436 dma.address += len;
437 dma.length -= len;
438
439 }
440
441 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
442 dma.control);
443
444 trace_fw_cfg_read(s, 0);
445}
446
447static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
448 unsigned size)
449{
450
451 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
452}
453
454static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
455 uint64_t value, unsigned size)
456{
457 FWCfgState *s = opaque;
458
459 if (size == 4) {
460 if (addr == 0) {
461
462 s->dma_addr = value << 32;
463 } else if (addr == 4) {
464
465 s->dma_addr |= value;
466 fw_cfg_dma_transfer(s);
467 }
468 } else if (size == 8 && addr == 0) {
469 s->dma_addr = value;
470 fw_cfg_dma_transfer(s);
471 }
472}
473
474static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
475 unsigned size, bool is_write,
476 MemTxAttrs attrs)
477{
478 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
479 (size == 8 && addr == 0));
480}
481
482static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
483 unsigned size, bool is_write,
484 MemTxAttrs attrs)
485{
486 return addr == 0;
487}
488
489static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size)
490{
491 return 0;
492}
493
494static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
495 uint64_t value, unsigned size)
496{
497 fw_cfg_select(opaque, (uint16_t)value);
498}
499
500static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
501 unsigned size, bool is_write,
502 MemTxAttrs attrs)
503{
504 return is_write && size == 2;
505}
506
507static void fw_cfg_comb_write(void *opaque, hwaddr addr,
508 uint64_t value, unsigned size)
509{
510 switch (size) {
511 case 1:
512 fw_cfg_write(opaque, (uint8_t)value);
513 break;
514 case 2:
515 fw_cfg_select(opaque, (uint16_t)value);
516 break;
517 }
518}
519
520static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
521 unsigned size, bool is_write,
522 MemTxAttrs attrs)
523{
524 return (size == 1) || (is_write && size == 2);
525}
526
527static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
528 .read = fw_cfg_ctl_mem_read,
529 .write = fw_cfg_ctl_mem_write,
530 .endianness = DEVICE_BIG_ENDIAN,
531 .valid.accepts = fw_cfg_ctl_mem_valid,
532};
533
534static const MemoryRegionOps fw_cfg_data_mem_ops = {
535 .read = fw_cfg_data_read,
536 .write = fw_cfg_data_mem_write,
537 .endianness = DEVICE_BIG_ENDIAN,
538 .valid = {
539 .min_access_size = 1,
540 .max_access_size = 1,
541 .accepts = fw_cfg_data_mem_valid,
542 },
543};
544
545static const MemoryRegionOps fw_cfg_comb_mem_ops = {
546 .read = fw_cfg_data_read,
547 .write = fw_cfg_comb_write,
548 .endianness = DEVICE_LITTLE_ENDIAN,
549 .valid.accepts = fw_cfg_comb_valid,
550};
551
552static const MemoryRegionOps fw_cfg_dma_mem_ops = {
553 .read = fw_cfg_dma_mem_read,
554 .write = fw_cfg_dma_mem_write,
555 .endianness = DEVICE_BIG_ENDIAN,
556 .valid.accepts = fw_cfg_dma_mem_valid,
557 .valid.max_access_size = 8,
558 .impl.max_access_size = 8,
559};
560
561static void fw_cfg_reset(DeviceState *d)
562{
563 FWCfgState *s = FW_CFG(d);
564
565
566 fw_cfg_select(s, FW_CFG_SIGNATURE);
567}
568
569
570
571
572
573
574static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
575 const VMStateField *field)
576{
577 uint32_t *v = pv;
578 *v = qemu_get_be16(f);
579 return 0;
580}
581
582static int put_unused(QEMUFile *f, void *pv, size_t size,
583 const VMStateField *field, QJSON *vmdesc)
584{
585 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
586 fprintf(stderr, "This functions shouldn't be called.\n");
587
588 return 0;
589}
590
591static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
592 .name = "int32_as_uint16",
593 .get = get_uint32_as_uint16,
594 .put = put_unused,
595};
596
597#define VMSTATE_UINT16_HACK(_f, _s, _t) \
598 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
599
600
601static bool is_version_1(void *opaque, int version_id)
602{
603 return version_id == 1;
604}
605
606bool fw_cfg_dma_enabled(void *opaque)
607{
608 FWCfgState *s = opaque;
609
610 return s->dma_enabled;
611}
612
613static const VMStateDescription vmstate_fw_cfg_dma = {
614 .name = "fw_cfg/dma",
615 .needed = fw_cfg_dma_enabled,
616 .fields = (VMStateField[]) {
617 VMSTATE_UINT64(dma_addr, FWCfgState),
618 VMSTATE_END_OF_LIST()
619 },
620};
621
622static const VMStateDescription vmstate_fw_cfg = {
623 .name = "fw_cfg",
624 .version_id = 2,
625 .minimum_version_id = 1,
626 .fields = (VMStateField[]) {
627 VMSTATE_UINT16(cur_entry, FWCfgState),
628 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
629 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
630 VMSTATE_END_OF_LIST()
631 },
632 .subsections = (const VMStateDescription*[]) {
633 &vmstate_fw_cfg_dma,
634 NULL,
635 }
636};
637
638static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key,
639 FWCfgCallback select_cb,
640 FWCfgWriteCallback write_cb,
641 void *callback_opaque,
642 void *data, size_t len,
643 bool read_only)
644{
645 int arch = !!(key & FW_CFG_ARCH_LOCAL);
646
647 key &= FW_CFG_ENTRY_MASK;
648
649 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
650 assert(s->entries[arch][key].data == NULL);
651
652 s->entries[arch][key].data = data;
653 s->entries[arch][key].len = (uint32_t)len;
654 s->entries[arch][key].select_cb = select_cb;
655 s->entries[arch][key].write_cb = write_cb;
656 s->entries[arch][key].callback_opaque = callback_opaque;
657 s->entries[arch][key].allow_write = !read_only;
658}
659
660static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
661 void *data, size_t len)
662{
663 void *ptr;
664 int arch = !!(key & FW_CFG_ARCH_LOCAL);
665
666 key &= FW_CFG_ENTRY_MASK;
667
668 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
669
670
671 ptr = s->entries[arch][key].data;
672 s->entries[arch][key].data = data;
673 s->entries[arch][key].len = len;
674 s->entries[arch][key].callback_opaque = NULL;
675 s->entries[arch][key].allow_write = false;
676
677 return ptr;
678}
679
680void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
681{
682 trace_fw_cfg_add_bytes(key, trace_key_name(key), len);
683 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true);
684}
685
686void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
687{
688 size_t sz = strlen(value) + 1;
689
690 trace_fw_cfg_add_string(key, trace_key_name(key), value);
691 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
692}
693
694void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value)
695{
696 size_t sz = strlen(value) + 1;
697 char *old;
698
699 old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz);
700 g_free(old);
701}
702
703void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
704{
705 uint16_t *copy;
706
707 copy = g_malloc(sizeof(value));
708 *copy = cpu_to_le16(value);
709 trace_fw_cfg_add_i16(key, trace_key_name(key), value);
710 fw_cfg_add_bytes(s, key, copy, sizeof(value));
711}
712
713void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
714{
715 uint16_t *copy, *old;
716
717 copy = g_malloc(sizeof(value));
718 *copy = cpu_to_le16(value);
719 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
720 g_free(old);
721}
722
723void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
724{
725 uint32_t *copy;
726
727 copy = g_malloc(sizeof(value));
728 *copy = cpu_to_le32(value);
729 trace_fw_cfg_add_i32(key, trace_key_name(key), value);
730 fw_cfg_add_bytes(s, key, copy, sizeof(value));
731}
732
733void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value)
734{
735 uint32_t *copy, *old;
736
737 copy = g_malloc(sizeof(value));
738 *copy = cpu_to_le32(value);
739 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
740 g_free(old);
741}
742
743void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
744{
745 uint64_t *copy;
746
747 copy = g_malloc(sizeof(value));
748 *copy = cpu_to_le64(value);
749 trace_fw_cfg_add_i64(key, trace_key_name(key), value);
750 fw_cfg_add_bytes(s, key, copy, sizeof(value));
751}
752
753void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
754{
755 uint64_t *copy, *old;
756
757 copy = g_malloc(sizeof(value));
758 *copy = cpu_to_le64(value);
759 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
760 g_free(old);
761}
762
763void fw_cfg_set_order_override(FWCfgState *s, int order)
764{
765 assert(s->fw_cfg_order_override == 0);
766 s->fw_cfg_order_override = order;
767}
768
769void fw_cfg_reset_order_override(FWCfgState *s)
770{
771 assert(s->fw_cfg_order_override != 0);
772 s->fw_cfg_order_override = 0;
773}
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789static struct {
790 const char *name;
791 int order;
792} fw_cfg_order[] = {
793 { "etc/boot-menu-wait", 10 },
794 { "bootsplash.jpg", 11 },
795 { "bootsplash.bmp", 12 },
796 { "etc/boot-fail-wait", 15 },
797 { "etc/smbios/smbios-tables", 20 },
798 { "etc/smbios/smbios-anchor", 30 },
799 { "etc/e820", 40 },
800 { "etc/reserved-memory-end", 50 },
801 { "genroms/kvmvapic.bin", 55 },
802 { "genroms/linuxboot.bin", 60 },
803 { },
804 { },
805 { "etc/system-states", 90 },
806 { },
807 { },
808 { "etc/extra-pci-roots", 120 },
809 { "etc/acpi/tables", 130 },
810 { "etc/table-loader", 140 },
811 { "etc/tpm/log", 150 },
812 { "etc/acpi/rsdp", 160 },
813 { "bootorder", 170 },
814
815#define FW_CFG_ORDER_OVERRIDE_LAST 200
816};
817
818static int get_fw_cfg_order(FWCfgState *s, const char *name)
819{
820 int i;
821
822 if (s->fw_cfg_order_override > 0) {
823 return s->fw_cfg_order_override;
824 }
825
826 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
827 if (fw_cfg_order[i].name == NULL) {
828 continue;
829 }
830
831 if (strcmp(name, fw_cfg_order[i].name) == 0) {
832 return fw_cfg_order[i].order;
833 }
834 }
835
836
837 warn_report("Unknown firmware file in legacy mode: %s", name);
838 return FW_CFG_ORDER_OVERRIDE_LAST;
839}
840
841void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
842 FWCfgCallback select_cb,
843 FWCfgWriteCallback write_cb,
844 void *callback_opaque,
845 void *data, size_t len, bool read_only)
846{
847 int i, index, count;
848 size_t dsize;
849 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
850 int order = 0;
851
852 if (!s->files) {
853 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
854 s->files = g_malloc0(dsize);
855 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
856 }
857
858 count = be32_to_cpu(s->files->count);
859 assert(count < fw_cfg_file_slots(s));
860
861
862 if (mc->legacy_fw_cfg_order) {
863
864
865
866
867 order = get_fw_cfg_order(s, filename);
868 for (index = count;
869 index > 0 && order < s->entry_order[index - 1];
870 index--);
871 } else {
872
873 for (index = count;
874 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
875 index--);
876 }
877
878
879
880
881
882
883
884
885 for (i = count; i > index; i--) {
886 s->files->f[i] = s->files->f[i - 1];
887 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
888 s->entries[0][FW_CFG_FILE_FIRST + i] =
889 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
890 s->entry_order[i] = s->entry_order[i - 1];
891 }
892
893 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
894 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
895
896 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
897 for (i = 0; i <= count; i++) {
898 if (i != index &&
899 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
900 error_report("duplicate fw_cfg file name: %s",
901 s->files->f[index].name);
902 exit(1);
903 }
904 }
905
906 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index,
907 select_cb, write_cb,
908 callback_opaque, data, len,
909 read_only);
910
911 s->files->f[index].size = cpu_to_be32(len);
912 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
913 s->entry_order[index] = order;
914 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
915
916 s->files->count = cpu_to_be32(count+1);
917}
918
919void fw_cfg_add_file(FWCfgState *s, const char *filename,
920 void *data, size_t len)
921{
922 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
923}
924
925void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
926 void *data, size_t len)
927{
928 int i, index;
929 void *ptr = NULL;
930
931 assert(s->files);
932
933 index = be32_to_cpu(s->files->count);
934
935 for (i = 0; i < index; i++) {
936 if (strcmp(filename, s->files->f[i].name) == 0) {
937 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
938 data, len);
939 s->files->f[i].size = cpu_to_be32(len);
940 return ptr;
941 }
942 }
943
944 assert(index < fw_cfg_file_slots(s));
945
946
947 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
948 return NULL;
949}
950
951static void fw_cfg_machine_reset(void *opaque)
952{
953 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
954 FWCfgState *s = opaque;
955 void *ptr;
956 size_t len;
957 char *buf;
958
959 buf = get_boot_devices_list(&len);
960 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len);
961 g_free(ptr);
962
963 if (!mc->legacy_fw_cfg_order) {
964 buf = get_boot_devices_lchs_list(&len);
965 ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
966 g_free(ptr);
967 }
968}
969
970static void fw_cfg_machine_ready(struct Notifier *n, void *data)
971{
972 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
973 qemu_register_reset(fw_cfg_machine_reset, s);
974}
975
976
977
978static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
979{
980 FWCfgState *s = FW_CFG(dev);
981 MachineState *machine = MACHINE(qdev_get_machine());
982 uint32_t version = FW_CFG_VERSION;
983
984 if (!fw_cfg_find()) {
985 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
986 return;
987 }
988
989 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
990 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
991 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
992 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
993 fw_cfg_bootsplash(s);
994 fw_cfg_reboot(s);
995
996 if (s->dma_enabled) {
997 version |= FW_CFG_VERSION_DMA;
998 }
999
1000 fw_cfg_add_i32(s, FW_CFG_ID, version);
1001
1002 s->machine_ready.notify = fw_cfg_machine_ready;
1003 qemu_add_machine_init_done_notifier(&s->machine_ready);
1004}
1005
1006FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
1007 AddressSpace *dma_as)
1008{
1009 DeviceState *dev;
1010 SysBusDevice *sbd;
1011 FWCfgIoState *ios;
1012 FWCfgState *s;
1013 bool dma_requested = dma_iobase && dma_as;
1014
1015 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
1016 if (!dma_requested) {
1017 qdev_prop_set_bit(dev, "dma_enabled", false);
1018 }
1019
1020 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1021 OBJECT(dev), NULL);
1022 qdev_init_nofail(dev);
1023
1024 sbd = SYS_BUS_DEVICE(dev);
1025 ios = FW_CFG_IO(dev);
1026 sysbus_add_io(sbd, iobase, &ios->comb_iomem);
1027
1028 s = FW_CFG(dev);
1029
1030 if (s->dma_enabled) {
1031
1032 s->dma_as = dma_as;
1033 s->dma_addr = 0;
1034 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem);
1035 }
1036
1037 return s;
1038}
1039
1040FWCfgState *fw_cfg_init_io(uint32_t iobase)
1041{
1042 return fw_cfg_init_io_dma(iobase, 0, NULL);
1043}
1044
1045FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
1046 hwaddr data_addr, uint32_t data_width,
1047 hwaddr dma_addr, AddressSpace *dma_as)
1048{
1049 DeviceState *dev;
1050 SysBusDevice *sbd;
1051 FWCfgState *s;
1052 bool dma_requested = dma_addr && dma_as;
1053
1054 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1055 qdev_prop_set_uint32(dev, "data_width", data_width);
1056 if (!dma_requested) {
1057 qdev_prop_set_bit(dev, "dma_enabled", false);
1058 }
1059
1060 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1061 OBJECT(dev), NULL);
1062 qdev_init_nofail(dev);
1063
1064 sbd = SYS_BUS_DEVICE(dev);
1065 sysbus_mmio_map(sbd, 0, ctl_addr);
1066 sysbus_mmio_map(sbd, 1, data_addr);
1067
1068 s = FW_CFG(dev);
1069
1070 if (s->dma_enabled) {
1071 s->dma_as = dma_as;
1072 s->dma_addr = 0;
1073 sysbus_mmio_map(sbd, 2, dma_addr);
1074 }
1075
1076 return s;
1077}
1078
1079FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
1080{
1081 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
1082 fw_cfg_data_mem_ops.valid.max_access_size,
1083 0, NULL);
1084}
1085
1086
1087FWCfgState *fw_cfg_find(void)
1088{
1089
1090 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
1091}
1092
1093
1094static void fw_cfg_class_init(ObjectClass *klass, void *data)
1095{
1096 DeviceClass *dc = DEVICE_CLASS(klass);
1097
1098 dc->reset = fw_cfg_reset;
1099 dc->vmsd = &vmstate_fw_cfg;
1100}
1101
1102static const TypeInfo fw_cfg_info = {
1103 .name = TYPE_FW_CFG,
1104 .parent = TYPE_SYS_BUS_DEVICE,
1105 .abstract = true,
1106 .instance_size = sizeof(FWCfgState),
1107 .class_init = fw_cfg_class_init,
1108};
1109
1110static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1111{
1112 uint16_t file_slots_max;
1113
1114 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1115 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1116 FW_CFG_FILE_SLOTS_MIN);
1117 return;
1118 }
1119
1120
1121
1122
1123 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1124 if (fw_cfg_file_slots(s) > file_slots_max) {
1125 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1126 file_slots_max);
1127 return;
1128 }
1129
1130 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1131 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1132 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1133}
1134
1135static Property fw_cfg_io_properties[] = {
1136 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1137 true),
1138 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1139 FW_CFG_FILE_SLOTS_DFLT),
1140 DEFINE_PROP_END_OF_LIST(),
1141};
1142
1143static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1144{
1145 FWCfgIoState *s = FW_CFG_IO(dev);
1146 Error *local_err = NULL;
1147
1148 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1149 if (local_err) {
1150 error_propagate(errp, local_err);
1151 return;
1152 }
1153
1154
1155
1156
1157 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1158 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1159
1160 if (FW_CFG(s)->dma_enabled) {
1161 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1162 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1163 sizeof(dma_addr_t));
1164 }
1165
1166 fw_cfg_common_realize(dev, errp);
1167}
1168
1169static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1170{
1171 DeviceClass *dc = DEVICE_CLASS(klass);
1172
1173 dc->realize = fw_cfg_io_realize;
1174 dc->props = fw_cfg_io_properties;
1175}
1176
1177static const TypeInfo fw_cfg_io_info = {
1178 .name = TYPE_FW_CFG_IO,
1179 .parent = TYPE_FW_CFG,
1180 .instance_size = sizeof(FWCfgIoState),
1181 .class_init = fw_cfg_io_class_init,
1182};
1183
1184
1185static Property fw_cfg_mem_properties[] = {
1186 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1187 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1188 true),
1189 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1190 FW_CFG_FILE_SLOTS_DFLT),
1191 DEFINE_PROP_END_OF_LIST(),
1192};
1193
1194static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1195{
1196 FWCfgMemState *s = FW_CFG_MEM(dev);
1197 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1198 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1199 Error *local_err = NULL;
1200
1201 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1202 if (local_err) {
1203 error_propagate(errp, local_err);
1204 return;
1205 }
1206
1207 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1208 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1209 sysbus_init_mmio(sbd, &s->ctl_iomem);
1210
1211 if (s->data_width > data_ops->valid.max_access_size) {
1212 s->wide_data_ops = *data_ops;
1213
1214 s->wide_data_ops.valid.max_access_size = s->data_width;
1215 s->wide_data_ops.impl.max_access_size = s->data_width;
1216 data_ops = &s->wide_data_ops;
1217 }
1218 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1219 "fwcfg.data", data_ops->valid.max_access_size);
1220 sysbus_init_mmio(sbd, &s->data_iomem);
1221
1222 if (FW_CFG(s)->dma_enabled) {
1223 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1224 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1225 sizeof(dma_addr_t));
1226 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1227 }
1228
1229 fw_cfg_common_realize(dev, errp);
1230}
1231
1232static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1233{
1234 DeviceClass *dc = DEVICE_CLASS(klass);
1235
1236 dc->realize = fw_cfg_mem_realize;
1237 dc->props = fw_cfg_mem_properties;
1238}
1239
1240static const TypeInfo fw_cfg_mem_info = {
1241 .name = TYPE_FW_CFG_MEM,
1242 .parent = TYPE_FW_CFG,
1243 .instance_size = sizeof(FWCfgMemState),
1244 .class_init = fw_cfg_mem_class_init,
1245};
1246
1247
1248static void fw_cfg_register_types(void)
1249{
1250 type_register_static(&fw_cfg_info);
1251 type_register_static(&fw_cfg_io_info);
1252 type_register_static(&fw_cfg_mem_info);
1253}
1254
1255type_init(fw_cfg_register_types)
1256