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25#include "qemu/osdep.h"
26#include "hw/i386/pc.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_host.h"
29#include "hw/pci-host/i440fx.h"
30#include "hw/qdev-properties.h"
31#include "hw/sysbus.h"
32#include "qapi/error.h"
33#include "migration/vmstate.h"
34#include "hw/pci-host/pam.h"
35#include "qapi/visitor.h"
36#include "qemu/error-report.h"
37
38
39
40
41
42
43#define I440FX_PCI_HOST_BRIDGE(obj) \
44 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
45
46typedef struct I440FXState {
47 PCIHostState parent_obj;
48 Range pci_hole;
49 uint64_t pci_hole64_size;
50 bool pci_hole64_fix;
51 uint32_t short_root_bus;
52} I440FXState;
53
54#define I440FX_PCI_DEVICE(obj) \
55 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
56
57struct PCII440FXState {
58
59 PCIDevice parent_obj;
60
61
62 MemoryRegion *system_memory;
63 MemoryRegion *pci_address_space;
64 MemoryRegion *ram_memory;
65 PAMMemoryRegion pam_regions[13];
66 MemoryRegion smram_region;
67 MemoryRegion smram, low_smram;
68};
69
70
71#define I440FX_PAM 0x59
72#define I440FX_PAM_SIZE 7
73#define I440FX_SMRAM 0x72
74
75
76#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
77
78
79
80
81#define I440FX_COREBOOT_RAM_SIZE 0x57
82
83static void i440fx_update_memory_mappings(PCII440FXState *d)
84{
85 int i;
86 PCIDevice *pd = PCI_DEVICE(d);
87
88 memory_region_transaction_begin();
89 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
90 pam_update(&d->pam_regions[i], i,
91 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
92 }
93 memory_region_set_enabled(&d->smram_region,
94 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
95 memory_region_set_enabled(&d->smram,
96 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
97 memory_region_transaction_commit();
98}
99
100
101static void i440fx_write_config(PCIDevice *dev,
102 uint32_t address, uint32_t val, int len)
103{
104 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
105
106
107 pci_default_write_config(dev, address, val, len);
108 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
109 range_covers_byte(address, len, I440FX_SMRAM)) {
110 i440fx_update_memory_mappings(d);
111 }
112}
113
114static int i440fx_post_load(void *opaque, int version_id)
115{
116 PCII440FXState *d = opaque;
117
118 i440fx_update_memory_mappings(d);
119 return 0;
120}
121
122static const VMStateDescription vmstate_i440fx = {
123 .name = "I440FX",
124 .version_id = 3,
125 .minimum_version_id = 3,
126 .post_load = i440fx_post_load,
127 .fields = (VMStateField[]) {
128 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
129
130
131
132 VMSTATE_UNUSED(1),
133 VMSTATE_END_OF_LIST()
134 }
135};
136
137static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
138 const char *name, void *opaque,
139 Error **errp)
140{
141 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
142 uint64_t val64;
143 uint32_t value;
144
145 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
146 value = val64;
147 assert(value == val64);
148 visit_type_uint32(v, name, &value, errp);
149}
150
151static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
152 const char *name, void *opaque,
153 Error **errp)
154{
155 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
156 uint64_t val64;
157 uint32_t value;
158
159 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
160 value = val64;
161 assert(value == val64);
162 visit_type_uint32(v, name, &value, errp);
163}
164
165
166
167
168
169
170
171
172static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
173{
174 PCIHostState *h = PCI_HOST_BRIDGE(obj);
175 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
176 Range w64;
177 uint64_t value;
178
179 pci_bus_get_w64_range(h->bus, &w64);
180 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
181 if (!value && s->pci_hole64_fix) {
182 value = pc_pci_hole64_start();
183 }
184 return value;
185}
186
187static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
188 const char *name,
189 void *opaque, Error **errp)
190{
191 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
192
193 visit_type_uint64(v, name, &hole64_start, errp);
194}
195
196
197
198
199
200
201
202static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
203 const char *name, void *opaque,
204 Error **errp)
205{
206 PCIHostState *h = PCI_HOST_BRIDGE(obj);
207 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
208 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
209 Range w64;
210 uint64_t value, hole64_end;
211
212 pci_bus_get_w64_range(h->bus, &w64);
213 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
214 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
215 if (s->pci_hole64_fix && value < hole64_end) {
216 value = hole64_end;
217 }
218 visit_type_uint64(v, name, &value, errp);
219}
220
221static void i440fx_pcihost_initfn(Object *obj)
222{
223 PCIHostState *s = PCI_HOST_BRIDGE(obj);
224
225 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
226 "pci-conf-idx", 4);
227 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
228 "pci-conf-data", 4);
229
230 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
231 i440fx_pcihost_get_pci_hole_start,
232 NULL, NULL, NULL, NULL);
233
234 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
235 i440fx_pcihost_get_pci_hole_end,
236 NULL, NULL, NULL, NULL);
237
238 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
239 i440fx_pcihost_get_pci_hole64_start,
240 NULL, NULL, NULL, NULL);
241
242 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
243 i440fx_pcihost_get_pci_hole64_end,
244 NULL, NULL, NULL, NULL);
245}
246
247static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
248{
249 PCIHostState *s = PCI_HOST_BRIDGE(dev);
250 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
251
252 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
253 sysbus_init_ioports(sbd, 0xcf8, 4);
254
255 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
256 sysbus_init_ioports(sbd, 0xcfc, 4);
257
258
259 memory_region_set_flush_coalesced(&s->data_mem);
260 memory_region_add_coalescing(&s->conf_mem, 0, 4);
261}
262
263static void i440fx_realize(PCIDevice *dev, Error **errp)
264{
265 dev->config[I440FX_SMRAM] = 0x02;
266
267 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
268 warn_report("i440fx doesn't support emulated iommu");
269 }
270}
271
272PCIBus *i440fx_init(const char *host_type, const char *pci_type,
273 PCII440FXState **pi440fx_state,
274 MemoryRegion *address_space_mem,
275 MemoryRegion *address_space_io,
276 ram_addr_t ram_size,
277 ram_addr_t below_4g_mem_size,
278 ram_addr_t above_4g_mem_size,
279 MemoryRegion *pci_address_space,
280 MemoryRegion *ram_memory)
281{
282 DeviceState *dev;
283 PCIBus *b;
284 PCIDevice *d;
285 PCIHostState *s;
286 PCII440FXState *f;
287 unsigned i;
288 I440FXState *i440fx;
289
290 dev = qdev_create(NULL, host_type);
291 s = PCI_HOST_BRIDGE(dev);
292 b = pci_root_bus_new(dev, NULL, pci_address_space,
293 address_space_io, 0, TYPE_PCI_BUS);
294 s->bus = b;
295 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
296 qdev_init_nofail(dev);
297
298 d = pci_create_simple(b, 0, pci_type);
299 *pi440fx_state = I440FX_PCI_DEVICE(d);
300 f = *pi440fx_state;
301 f->system_memory = address_space_mem;
302 f->pci_address_space = pci_address_space;
303 f->ram_memory = ram_memory;
304
305 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
306 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
307 IO_APIC_DEFAULT_ADDRESS - 1);
308
309
310 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
311 f->pci_address_space);
312
313
314 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
315 f->pci_address_space, 0xa0000, 0x20000);
316 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
317 &f->smram_region, 1);
318 memory_region_set_enabled(&f->smram_region, true);
319
320
321 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
322 memory_region_set_enabled(&f->smram, true);
323 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
324 f->ram_memory, 0xa0000, 0x20000);
325 memory_region_set_enabled(&f->low_smram, true);
326 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
327 object_property_add_const_link(qdev_get_machine(), "smram",
328 OBJECT(&f->smram), &error_abort);
329
330 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
331 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
332 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
333 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
334 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
335 PAM_EXPAN_SIZE);
336 }
337
338 ram_size = ram_size / 8 / 1024 / 1024;
339 if (ram_size > 255) {
340 ram_size = 255;
341 }
342 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
343
344 i440fx_update_memory_mappings(f);
345
346 return b;
347}
348
349PCIBus *find_i440fx(void)
350{
351 PCIHostState *s = OBJECT_CHECK(PCIHostState,
352 object_resolve_path("/machine/i440fx", NULL),
353 TYPE_PCI_HOST_BRIDGE);
354 return s ? s->bus : NULL;
355}
356
357static void i440fx_class_init(ObjectClass *klass, void *data)
358{
359 DeviceClass *dc = DEVICE_CLASS(klass);
360 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
361
362 k->realize = i440fx_realize;
363 k->config_write = i440fx_write_config;
364 k->vendor_id = PCI_VENDOR_ID_INTEL;
365 k->device_id = PCI_DEVICE_ID_INTEL_82441;
366 k->revision = 0x02;
367 k->class_id = PCI_CLASS_BRIDGE_HOST;
368 dc->desc = "Host bridge";
369 dc->vmsd = &vmstate_i440fx;
370
371
372
373
374 dc->user_creatable = false;
375 dc->hotpluggable = false;
376}
377
378static const TypeInfo i440fx_info = {
379 .name = TYPE_I440FX_PCI_DEVICE,
380 .parent = TYPE_PCI_DEVICE,
381 .instance_size = sizeof(PCII440FXState),
382 .class_init = i440fx_class_init,
383 .interfaces = (InterfaceInfo[]) {
384 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
385 { },
386 },
387};
388
389
390typedef struct {
391 uint8_t offset;
392 uint8_t len;
393} IGDHostInfo;
394
395
396static const IGDHostInfo igd_host_bridge_infos[] = {
397 {0x08, 2},
398 {0x2c, 2},
399 {0x2e, 2},
400 {0x50, 2},
401 {0x52, 2},
402 {0xa4, 4},
403 {0xa8, 4},
404};
405
406static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp)
407{
408 int rc, config_fd;
409
410 char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
411 0, 0, 0, 0, "config");
412
413 config_fd = open(path, O_RDWR);
414 if (config_fd < 0) {
415 error_setg_errno(errp, errno, "Failed to open: %s", path);
416 goto out;
417 }
418
419 if (lseek(config_fd, pos, SEEK_SET) != pos) {
420 error_setg_errno(errp, errno, "Failed to seek: %s", path);
421 goto out_close_fd;
422 }
423
424 do {
425 rc = read(config_fd, (uint8_t *)val, len);
426 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
427 if (rc != len) {
428 error_setg_errno(errp, errno, "Failed to read: %s", path);
429 }
430
431out_close_fd:
432 close(config_fd);
433out:
434 g_free(path);
435}
436
437static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
438{
439 uint32_t val = 0;
440 int i, num;
441 int pos, len;
442 Error *local_err = NULL;
443
444 num = ARRAY_SIZE(igd_host_bridge_infos);
445 for (i = 0; i < num; i++) {
446 pos = igd_host_bridge_infos[i].offset;
447 len = igd_host_bridge_infos[i].len;
448 host_pci_config_read(pos, len, &val, &local_err);
449 if (local_err) {
450 error_propagate(errp, local_err);
451 return;
452 }
453 pci_default_write_config(pci_dev, pos, val, len);
454 }
455}
456
457static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
458{
459 DeviceClass *dc = DEVICE_CLASS(klass);
460 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
461
462 k->realize = igd_pt_i440fx_realize;
463 dc->desc = "IGD Passthrough Host bridge";
464}
465
466static const TypeInfo igd_passthrough_i440fx_info = {
467 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
468 .parent = TYPE_I440FX_PCI_DEVICE,
469 .instance_size = sizeof(PCII440FXState),
470 .class_init = igd_passthrough_i440fx_class_init,
471};
472
473static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
474 PCIBus *rootbus)
475{
476 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
477
478
479 if (s->short_root_bus) {
480 return "0000";
481 }
482 return "0000:00";
483}
484
485static Property i440fx_props[] = {
486 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
487 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
488 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
489 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
490 DEFINE_PROP_END_OF_LIST(),
491};
492
493static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
494{
495 DeviceClass *dc = DEVICE_CLASS(klass);
496 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
497
498 hc->root_bus_path = i440fx_pcihost_root_bus_path;
499 dc->realize = i440fx_pcihost_realize;
500 dc->fw_name = "pci";
501 dc->props = i440fx_props;
502
503 dc->user_creatable = false;
504}
505
506static const TypeInfo i440fx_pcihost_info = {
507 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
508 .parent = TYPE_PCI_HOST_BRIDGE,
509 .instance_size = sizeof(I440FXState),
510 .instance_init = i440fx_pcihost_initfn,
511 .class_init = i440fx_pcihost_class_init,
512};
513
514static void i440fx_register_types(void)
515{
516 type_register_static(&i440fx_info);
517 type_register_static(&igd_passthrough_i440fx_info);
518 type_register_static(&i440fx_pcihost_info);
519}
520
521type_init(i440fx_register_types)
522
