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20#include "qemu/osdep.h"
21#include "hw/irq.h"
22#include "target/ppc/cpu.h"
23#include "qemu/log.h"
24#include "qemu/module.h"
25#include "sysemu/reset.h"
26#include "qapi/error.h"
27#include "monitor/monitor.h"
28
29#include "exec/address-spaces.h"
30
31#include "hw/ppc/fdt.h"
32#include "hw/ppc/pnv.h"
33#include "hw/ppc/pnv_xscom.h"
34#include "hw/qdev-properties.h"
35#include "hw/ppc/pnv_psi.h"
36
37#include <libfdt.h>
38
39#define PSIHB_XSCOM_FIR_RW 0x00
40#define PSIHB_XSCOM_FIR_AND 0x01
41#define PSIHB_XSCOM_FIR_OR 0x02
42#define PSIHB_XSCOM_FIRMASK_RW 0x03
43#define PSIHB_XSCOM_FIRMASK_AND 0x04
44#define PSIHB_XSCOM_FIRMASK_OR 0x05
45#define PSIHB_XSCOM_FIRACT0 0x06
46#define PSIHB_XSCOM_FIRACT1 0x07
47
48
49#define PSIHB_XSCOM_BAR 0x0a
50#define PSIHB_BAR_EN 0x0000000000000001ull
51
52
53#define PSIHB_XSCOM_FSPBAR 0x0b
54
55
56#define PSIHB_XSCOM_CR 0x0e
57#define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull
58#define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull
59#define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull
60#define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull
61#define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull
62#define PSIHB_CR_FSP_RESET 0x0200000000000000ull
63#define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull
64#define PSIHB_CR_PSI_IRQ 0x0000800000000000ull
65#define PSIHB_CR_FSP_IRQ 0x0000400000000000ull
66#define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull
67#define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull
68
69
70
71#define PSIHB_XSCOM_SEMR 0x0f
72
73
74#define PSIHB_XSCOM_XIVR_FSP 0x10
75#define PSIHB_XIVR_SERVER_SH 40
76#define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH)
77#define PSIHB_XIVR_PRIO_SH 32
78#define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH)
79#define PSIHB_XIVR_SRC_SH 29
80#define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH)
81#define PSIHB_XIVR_PENDING 0x01000000ull
82
83
84#define PSIHB_XSCOM_SCR 0x12
85
86
87#define PSIHB_XSCOM_CCR 0x13
88
89
90#define PSIHB_XSCOM_DMA_UPADD 0x14
91
92
93#define PSIHB_XSCOM_IRQ_STAT 0x15
94#define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull
95#define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull
96#define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull
97#define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull
98#define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull
99
100
101#define PSIHB_XSCOM_XIVR_OCC 0x16
102#define PSIHB_XSCOM_XIVR_FSI 0x17
103#define PSIHB_XSCOM_XIVR_LPCI2C 0x18
104#define PSIHB_XSCOM_XIVR_LOCERR 0x19
105#define PSIHB_XSCOM_XIVR_EXT 0x1a
106
107
108#define PSIHB_XSCOM_IRSN 0x1b
109#define PSIHB_IRSN_COMP_SH 45
110#define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH)
111#define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull
112#define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull
113#define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull
114#define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull
115#define PSIHB_IRSN_COMPMASK_SH 13
116#define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
117
118#define PSIHB_BAR_MASK 0x0003fffffff00000ull
119#define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
120
121#define PSIHB9_BAR_MASK 0x00fffffffff00000ull
122#define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull
123
124#define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
125
126static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
127{
128 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
129 MemoryRegion *sysmem = get_system_memory();
130 uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
131
132 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
133
134
135 if (old & PSIHB_BAR_EN) {
136 memory_region_del_subregion(sysmem, &psi->regs_mr);
137 }
138
139
140 if (bar & PSIHB_BAR_EN) {
141 uint64_t addr = bar & ppc->bar_mask;
142 memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
143 }
144}
145
146static void pnv_psi_update_fsp_mr(PnvPsi *psi)
147{
148
149}
150
151static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
152{
153 uint64_t old = psi->regs[PSIHB_XSCOM_CR];
154
155 psi->regs[PSIHB_XSCOM_CR] = cr;
156
157
158 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
159 pnv_psi_update_fsp_mr(psi);
160 }
161}
162
163static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
164{
165 ICSState *ics = &PNV8_PSI(psi)->ics;
166
167
168
169
170
171
172 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
173 PSIHB_IRSN_IRQ_MUX |
174 PSIHB_IRSN_IRQ_RESET |
175 PSIHB_IRSN_DOWNSTREAM_EN |
176 PSIHB_IRSN_UPSTREAM_EN);
177
178
179
180
181
182 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
183}
184
185
186
187
188static const uint32_t xivr_regs[] = {
189 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
190 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
191 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
192 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
193 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C,
194 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
195 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
196};
197
198static const uint32_t stat_regs[] = {
199 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
200 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
201 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
202 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
203 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT,
204 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
205 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
206};
207
208static const uint64_t stat_bits[] = {
209 [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
210 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
211 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
212 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
213 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C,
214 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
215 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
216};
217
218void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
219{
220 PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
221}
222
223static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
224{
225 uint32_t xivr_reg;
226 uint32_t stat_reg;
227 uint32_t src;
228 bool masked;
229
230 if (irq > PSIHB_IRQ_EXTERNAL) {
231 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
232 return;
233 }
234
235 xivr_reg = xivr_regs[irq];
236 stat_reg = stat_regs[irq];
237
238 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
239 if (state) {
240 psi->regs[stat_reg] |= stat_bits[irq];
241
242
243
244 qemu_irq_raise(psi->qirqs[src]);
245 } else {
246 psi->regs[stat_reg] &= ~stat_bits[irq];
247
248
249 if (stat_reg != PSIHB_XSCOM_CR ||
250 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
251 qemu_irq_lower(psi->qirqs[src]);
252 } else {
253 state = true;
254 }
255 }
256
257
258
259
260
261
262
263
264
265
266
267
268 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
269 if (state && !masked) {
270 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
271 } else {
272 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
273 }
274}
275
276static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
277{
278 ICSState *ics = &PNV8_PSI(psi)->ics;
279 uint16_t server;
280 uint8_t prio;
281 uint8_t src;
282
283 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
284 (val & (PSIHB_XIVR_SERVER_MSK |
285 PSIHB_XIVR_PRIO_MSK |
286 PSIHB_XIVR_SRC_MSK));
287 val = psi->regs[reg];
288 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
289 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
290 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
291
292 if (src >= PSI_NUM_INTERRUPTS) {
293 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
294 return;
295 }
296
297
298 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
299 psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
300 }
301
302
303
304
305 server >>= 2;
306
307
308
309
310
311
312
313
314 ics_write_xive(ics, src, server, prio, prio);
315}
316
317static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
318{
319 uint64_t val = 0xffffffffffffffffull;
320
321 switch (offset) {
322 case PSIHB_XSCOM_FIR_RW:
323 case PSIHB_XSCOM_FIRACT0:
324 case PSIHB_XSCOM_FIRACT1:
325 case PSIHB_XSCOM_BAR:
326 case PSIHB_XSCOM_FSPBAR:
327 case PSIHB_XSCOM_CR:
328 case PSIHB_XSCOM_XIVR_FSP:
329 case PSIHB_XSCOM_XIVR_OCC:
330 case PSIHB_XSCOM_XIVR_FSI:
331 case PSIHB_XSCOM_XIVR_LPCI2C:
332 case PSIHB_XSCOM_XIVR_LOCERR:
333 case PSIHB_XSCOM_XIVR_EXT:
334 case PSIHB_XSCOM_IRQ_STAT:
335 case PSIHB_XSCOM_SEMR:
336 case PSIHB_XSCOM_DMA_UPADD:
337 case PSIHB_XSCOM_IRSN:
338 val = psi->regs[offset];
339 break;
340 default:
341 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
342 }
343 return val;
344}
345
346static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
347 bool mmio)
348{
349 switch (offset) {
350 case PSIHB_XSCOM_FIR_RW:
351 case PSIHB_XSCOM_FIRACT0:
352 case PSIHB_XSCOM_FIRACT1:
353 case PSIHB_XSCOM_SEMR:
354 case PSIHB_XSCOM_DMA_UPADD:
355 psi->regs[offset] = val;
356 break;
357 case PSIHB_XSCOM_FIR_OR:
358 psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
359 break;
360 case PSIHB_XSCOM_FIR_AND:
361 psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
362 break;
363 case PSIHB_XSCOM_BAR:
364
365 if (!mmio) {
366 pnv_psi_set_bar(psi, val);
367 } else {
368 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
369 }
370 break;
371 case PSIHB_XSCOM_FSPBAR:
372 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
373 pnv_psi_update_fsp_mr(psi);
374 break;
375 case PSIHB_XSCOM_CR:
376 pnv_psi_set_cr(psi, val);
377 break;
378 case PSIHB_XSCOM_SCR:
379 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
380 break;
381 case PSIHB_XSCOM_CCR:
382 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
383 break;
384 case PSIHB_XSCOM_XIVR_FSP:
385 case PSIHB_XSCOM_XIVR_OCC:
386 case PSIHB_XSCOM_XIVR_FSI:
387 case PSIHB_XSCOM_XIVR_LPCI2C:
388 case PSIHB_XSCOM_XIVR_LOCERR:
389 case PSIHB_XSCOM_XIVR_EXT:
390 pnv_psi_set_xivr(psi, offset, val);
391 break;
392 case PSIHB_XSCOM_IRQ_STAT:
393
394 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
395 break;
396 case PSIHB_XSCOM_IRSN:
397 pnv_psi_set_irsn(psi, val);
398 break;
399 default:
400 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
401 }
402}
403
404
405
406
407
408static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
409{
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
411}
412
413static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
414 uint64_t val, unsigned size)
415{
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
417}
418
419static const MemoryRegionOps psi_mmio_ops = {
420 .read = pnv_psi_mmio_read,
421 .write = pnv_psi_mmio_write,
422 .endianness = DEVICE_BIG_ENDIAN,
423 .valid = {
424 .min_access_size = 8,
425 .max_access_size = 8,
426 },
427 .impl = {
428 .min_access_size = 8,
429 .max_access_size = 8,
430 },
431};
432
433static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
434{
435 return pnv_psi_reg_read(opaque, addr >> 3, false);
436}
437
438static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
439 uint64_t val, unsigned size)
440{
441 pnv_psi_reg_write(opaque, addr >> 3, val, false);
442}
443
444static const MemoryRegionOps pnv_psi_xscom_ops = {
445 .read = pnv_psi_xscom_read,
446 .write = pnv_psi_xscom_write,
447 .endianness = DEVICE_BIG_ENDIAN,
448 .valid = {
449 .min_access_size = 8,
450 .max_access_size = 8,
451 },
452 .impl = {
453 .min_access_size = 8,
454 .max_access_size = 8,
455 }
456};
457
458static void pnv_psi_reset(void *dev)
459{
460 PnvPsi *psi = PNV_PSI(dev);
461
462 memset(psi->regs, 0x0, sizeof(psi->regs));
463
464 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
465}
466
467static void pnv_psi_power8_instance_init(Object *obj)
468{
469 Pnv8Psi *psi8 = PNV8_PSI(obj);
470
471 object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics),
472 TYPE_ICS, &error_abort, NULL);
473}
474
475static const uint8_t irq_to_xivr[] = {
476 PSIHB_XSCOM_XIVR_FSP,
477 PSIHB_XSCOM_XIVR_OCC,
478 PSIHB_XSCOM_XIVR_FSI,
479 PSIHB_XSCOM_XIVR_LPCI2C,
480 PSIHB_XSCOM_XIVR_LOCERR,
481 PSIHB_XSCOM_XIVR_EXT,
482};
483
484static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
485{
486 PnvPsi *psi = PNV_PSI(dev);
487 ICSState *ics = &PNV8_PSI(psi)->ics;
488 Object *obj;
489 Error *err = NULL;
490 unsigned int i;
491
492 obj = object_property_get_link(OBJECT(dev), "xics", &err);
493 if (!obj) {
494 error_setg(errp, "%s: required link 'xics' not found: %s",
495 __func__, error_get_pretty(err));
496 return;
497 }
498
499
500 object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
501 &error_abort);
502 object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
503 if (err) {
504 error_propagate(errp, err);
505 return;
506 }
507 object_property_set_bool(OBJECT(ics), true, "realized", &err);
508 if (err) {
509 error_propagate(errp, err);
510 return;
511 }
512
513 for (i = 0; i < ics->nr_irqs; i++) {
514 ics_set_irq_type(ics, i, true);
515 }
516
517 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
518
519
520 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
521 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
522
523
524 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
525 "psihb", PNV_PSIHB_SIZE);
526
527
528 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
529
530
531 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
532 uint8_t xivr = irq_to_xivr[i];
533 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
534 ((uint64_t) i << PSIHB_XIVR_SRC_SH);
535 }
536
537 qemu_register_reset(pnv_psi_reset, dev);
538}
539
540static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
541static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
542
543static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
544{
545 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
546 char *name;
547 int offset;
548 uint32_t reg[] = {
549 cpu_to_be32(ppc->xscom_pcba),
550 cpu_to_be32(ppc->xscom_size)
551 };
552
553 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
554 offset = fdt_add_subnode(fdt, xscom_offset, name);
555 _FDT(offset);
556 g_free(name);
557
558 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
559 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
560 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
561 if (ppc->chip_type == PNV_CHIP_POWER9) {
562 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
563 sizeof(compat_p9)));
564 } else {
565 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
566 sizeof(compat_p8)));
567 }
568 return 0;
569}
570
571static Property pnv_psi_properties[] = {
572 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
573 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
574 DEFINE_PROP_END_OF_LIST(),
575};
576
577static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
578{
579 DeviceClass *dc = DEVICE_CLASS(klass);
580 PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
581
582 dc->desc = "PowerNV PSI Controller POWER8";
583 dc->realize = pnv_psi_power8_realize;
584
585 ppc->chip_type = PNV_CHIP_POWER8;
586 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
587 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
588 ppc->bar_mask = PSIHB_BAR_MASK;
589 ppc->irq_set = pnv_psi_power8_irq_set;
590}
591
592static const TypeInfo pnv_psi_power8_info = {
593 .name = TYPE_PNV8_PSI,
594 .parent = TYPE_PNV_PSI,
595 .instance_size = sizeof(Pnv8Psi),
596 .instance_init = pnv_psi_power8_instance_init,
597 .class_init = pnv_psi_power8_class_init,
598};
599
600
601
602
603#define PSIHB9_CR 0x20
604#define PSIHB9_SEMR 0x28
605
606
607
608#define PSIHB9_INTERRUPT_CONTROL 0x58
609#define PSIHB9_IRQ_METHOD PPC_BIT(0)
610#define PSIHB9_IRQ_RESET PPC_BIT(1)
611#define PSIHB9_ESB_CI_BASE 0x60
612#define PSIHB9_ESB_CI_VALID 1
613#define PSIHB9_ESB_NOTIF_ADDR 0x68
614#define PSIHB9_ESB_NOTIF_VALID 1
615#define PSIHB9_IVT_OFFSET 0x70
616#define PSIHB9_IVT_OFF_SHIFT 32
617
618#define PSIHB9_IRQ_LEVEL 0x78
619#define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0)
620#define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1)
621#define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2)
622#define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3)
623#define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4)
624#define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5)
625#define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6)
626#define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7)
627#define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8)
628#define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9)
629#define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10)
630#define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11)
631#define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12)
632#define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13)
633#define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14)
634#define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15)
635#define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16)
636#define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19)
637
638#define PSIHB9_IRQ_STAT 0x80
639#define PSIHB9_IRQ_STAT_PSI PPC_BIT(0)
640#define PSIHB9_IRQ_STAT_OCC PPC_BIT(1)
641#define PSIHB9_IRQ_STAT_FSI PPC_BIT(2)
642#define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3)
643#define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4)
644#define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5)
645#define PSIHB9_IRQ_STAT_TPM PPC_BIT(6)
646#define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7)
647#define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8)
648#define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9)
649#define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10)
650#define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11)
651#define PSIHB9_IRQ_STAT_DIO PPC_BIT(12)
652#define PSIHB9_IRQ_STAT_PSU PPC_BIT(13)
653
654static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
655{
656 PnvPsi *psi = PNV_PSI(xf);
657 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
658 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
659 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
660
661 uint32_t offset =
662 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
663 uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
664 MemTxResult result;
665
666 if (!valid) {
667 return;
668 }
669
670 address_space_stq_be(&address_space_memory, notify_addr, data,
671 MEMTXATTRS_UNSPECIFIED, &result);
672 if (result != MEMTX_OK) {
673 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
674 HWADDR_PRIx "\n", __func__, notif_port);
675 return;
676 }
677}
678
679static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
680{
681 PnvPsi *psi = PNV_PSI(opaque);
682 uint32_t reg = PSIHB_REG(addr);
683 uint64_t val = -1;
684
685 switch (addr) {
686 case PSIHB9_CR:
687 case PSIHB9_SEMR:
688
689 case PSIHB9_INTERRUPT_CONTROL:
690 case PSIHB9_ESB_CI_BASE:
691 case PSIHB9_ESB_NOTIF_ADDR:
692 case PSIHB9_IVT_OFFSET:
693 val = psi->regs[reg];
694 break;
695 default:
696 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
697 }
698
699 return val;
700}
701
702static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
703 uint64_t val, unsigned size)
704{
705 PnvPsi *psi = PNV_PSI(opaque);
706 Pnv9Psi *psi9 = PNV9_PSI(psi);
707 uint32_t reg = PSIHB_REG(addr);
708 MemoryRegion *sysmem = get_system_memory();
709
710 switch (addr) {
711 case PSIHB9_CR:
712 case PSIHB9_SEMR:
713
714 break;
715 case PSIHB9_INTERRUPT_CONTROL:
716 if (val & PSIHB9_IRQ_RESET) {
717 device_reset(DEVICE(&psi9->source));
718 }
719 psi->regs[reg] = val;
720 break;
721
722 case PSIHB9_ESB_CI_BASE:
723 if (!(val & PSIHB9_ESB_CI_VALID)) {
724 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
725 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
726 }
727 } else {
728 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
729 memory_region_add_subregion(sysmem,
730 val & ~PSIHB9_ESB_CI_VALID,
731 &psi9->source.esb_mmio);
732 }
733 }
734 psi->regs[reg] = val;
735 break;
736
737 case PSIHB9_ESB_NOTIF_ADDR:
738 psi->regs[reg] = val;
739 break;
740 case PSIHB9_IVT_OFFSET:
741 psi->regs[reg] = val;
742 break;
743 default:
744 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
745 }
746}
747
748static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
749 .read = pnv_psi_p9_mmio_read,
750 .write = pnv_psi_p9_mmio_write,
751 .endianness = DEVICE_BIG_ENDIAN,
752 .valid = {
753 .min_access_size = 8,
754 .max_access_size = 8,
755 },
756 .impl = {
757 .min_access_size = 8,
758 .max_access_size = 8,
759 },
760};
761
762static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
763{
764
765 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
766 return -1;
767}
768
769static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
770 uint64_t val, unsigned size)
771{
772 PnvPsi *psi = PNV_PSI(opaque);
773
774
775 switch (addr >> 3) {
776 case PSIHB_XSCOM_BAR:
777 pnv_psi_set_bar(psi, val);
778 break;
779 default:
780 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
781 addr);
782 }
783}
784
785static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
786 .read = pnv_psi_p9_xscom_read,
787 .write = pnv_psi_p9_xscom_write,
788 .endianness = DEVICE_BIG_ENDIAN,
789 .valid = {
790 .min_access_size = 8,
791 .max_access_size = 8,
792 },
793 .impl = {
794 .min_access_size = 8,
795 .max_access_size = 8,
796 }
797};
798
799static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
800{
801 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
802
803 if (irq > PSIHB9_NUM_IRQS) {
804 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
805 return;
806 }
807
808 if (irq_method & PSIHB9_IRQ_METHOD) {
809 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
810 return;
811 }
812
813
814 if (state) {
815 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
816 } else {
817 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
818 }
819
820 qemu_set_irq(psi->qirqs[irq], state);
821}
822
823static void pnv_psi_power9_reset(void *dev)
824{
825 Pnv9Psi *psi = PNV9_PSI(dev);
826
827 pnv_psi_reset(dev);
828
829 if (memory_region_is_mapped(&psi->source.esb_mmio)) {
830 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
831 }
832}
833
834static void pnv_psi_power9_instance_init(Object *obj)
835{
836 Pnv9Psi *psi = PNV9_PSI(obj);
837
838 object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
839 TYPE_XIVE_SOURCE, &error_abort, NULL);
840}
841
842static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
843{
844 PnvPsi *psi = PNV_PSI(dev);
845 XiveSource *xsrc = &PNV9_PSI(psi)->source;
846 Error *local_err = NULL;
847 int i;
848
849
850 object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
851 &error_fatal);
852 object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
853 &error_fatal);
854 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi),
855 &error_fatal);
856 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
857 if (local_err) {
858 error_propagate(errp, local_err);
859 return;
860 }
861
862 for (i = 0; i < xsrc->nr_irqs; i++) {
863 xive_source_irq_set_lsi(xsrc, i);
864 }
865
866 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
867
868
869 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
870 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
871
872
873 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
874 "psihb", PNV9_PSIHB_SIZE);
875
876 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
877
878 qemu_register_reset(pnv_psi_power9_reset, dev);
879}
880
881static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
882{
883 DeviceClass *dc = DEVICE_CLASS(klass);
884 PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
885 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
886
887 dc->desc = "PowerNV PSI Controller POWER9";
888 dc->realize = pnv_psi_power9_realize;
889
890 ppc->chip_type = PNV_CHIP_POWER9;
891 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
892 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
893 ppc->bar_mask = PSIHB9_BAR_MASK;
894 ppc->irq_set = pnv_psi_power9_irq_set;
895
896 xfc->notify = pnv_psi_notify;
897}
898
899static const TypeInfo pnv_psi_power9_info = {
900 .name = TYPE_PNV9_PSI,
901 .parent = TYPE_PNV_PSI,
902 .instance_size = sizeof(Pnv9Psi),
903 .instance_init = pnv_psi_power9_instance_init,
904 .class_init = pnv_psi_power9_class_init,
905 .interfaces = (InterfaceInfo[]) {
906 { TYPE_XIVE_NOTIFIER },
907 { },
908 },
909};
910
911static void pnv_psi_class_init(ObjectClass *klass, void *data)
912{
913 DeviceClass *dc = DEVICE_CLASS(klass);
914 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
915
916 xdc->dt_xscom = pnv_psi_dt_xscom;
917
918 dc->desc = "PowerNV PSI Controller";
919 dc->props = pnv_psi_properties;
920}
921
922static const TypeInfo pnv_psi_info = {
923 .name = TYPE_PNV_PSI,
924 .parent = TYPE_SYS_BUS_DEVICE,
925 .instance_size = sizeof(PnvPsi),
926 .class_init = pnv_psi_class_init,
927 .class_size = sizeof(PnvPsiClass),
928 .abstract = true,
929 .interfaces = (InterfaceInfo[]) {
930 { TYPE_PNV_XSCOM_INTERFACE },
931 { }
932 }
933};
934
935static void pnv_psi_register_types(void)
936{
937 type_register_static(&pnv_psi_info);
938 type_register_static(&pnv_psi_power8_info);
939 type_register_static(&pnv_psi_power9_info);
940}
941
942type_init(pnv_psi_register_types);
943
944void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
945{
946 PnvPsi *psi = PNV_PSI(psi9);
947
948 uint32_t offset =
949 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
950
951 monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
952 offset, offset + psi9->source.nr_irqs - 1);
953 xive_source_pic_print_info(&psi9->source, offset, mon);
954}
955
