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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/module.h"
24#include "sysemu/reset.h"
25#include "hw/sysbus.h"
26#include "target/riscv/cpu.h"
27#include "hw/qdev-properties.h"
28#include "hw/riscv/riscv_hart.h"
29
30static Property riscv_harts_props[] = {
31 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
32 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
33 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
34 DEFINE_PROP_END_OF_LIST(),
35};
36
37static void riscv_harts_cpu_reset(void *opaque)
38{
39 RISCVCPU *cpu = opaque;
40 cpu_reset(CPU(cpu));
41}
42
43static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
44 char *cpu_type, Error **errp)
45{
46 Error *err = NULL;
47
48 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
49 sizeof(RISCVCPU), cpu_type,
50 &error_abort, NULL);
51 s->harts[idx].env.mhartid = s->hartid_base + idx;
52 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
53 object_property_set_bool(OBJECT(&s->harts[idx]), true,
54 "realized", &err);
55 if (err) {
56 error_propagate(errp, err);
57 return;
58 }
59}
60
61static void riscv_harts_realize(DeviceState *dev, Error **errp)
62{
63 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
64 int n;
65
66 s->harts = g_new0(RISCVCPU, s->num_harts);
67
68 for (n = 0; n < s->num_harts; n++) {
69 riscv_hart_realize(s, n, s->cpu_type, errp);
70 }
71}
72
73static void riscv_harts_class_init(ObjectClass *klass, void *data)
74{
75 DeviceClass *dc = DEVICE_CLASS(klass);
76
77 dc->props = riscv_harts_props;
78 dc->realize = riscv_harts_realize;
79}
80
81static const TypeInfo riscv_harts_info = {
82 .name = TYPE_RISCV_HART_ARRAY,
83 .parent = TYPE_SYS_BUS_DEVICE,
84 .instance_size = sizeof(RISCVHartArrayState),
85 .class_init = riscv_harts_class_init,
86};
87
88static void riscv_harts_register_types(void)
89{
90 type_register_static(&riscv_harts_info);
91}
92
93type_init(riscv_harts_register_types)
94