1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#include "qemu/osdep.h"
34#include "qemu/log.h"
35#include "qemu/error-report.h"
36#include "qapi/error.h"
37#include "hw/boards.h"
38#include "hw/loader.h"
39#include "hw/sysbus.h"
40#include "hw/char/serial.h"
41#include "hw/cpu/cluster.h"
42#include "hw/misc/unimp.h"
43#include "target/riscv/cpu.h"
44#include "hw/riscv/riscv_hart.h"
45#include "hw/riscv/sifive_plic.h"
46#include "hw/riscv/sifive_clint.h"
47#include "hw/riscv/sifive_uart.h"
48#include "hw/riscv/sifive_u.h"
49#include "hw/riscv/boot.h"
50#include "chardev/char.h"
51#include "net/eth.h"
52#include "sysemu/arch_init.h"
53#include "sysemu/device_tree.h"
54#include "sysemu/sysemu.h"
55#include "exec/address-spaces.h"
56
57#include <libfdt.h>
58
59#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
60
61static const struct MemmapEntry {
62 hwaddr base;
63 hwaddr size;
64} sifive_u_memmap[] = {
65 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
66 [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
67 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
68 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
69 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
70 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
71 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
72 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
73 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
74 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
75 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
76 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
77 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
78};
79
80#define OTP_SERIAL 1
81#define GEM_REVISION 0x10070109
82
83static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
84 uint64_t mem_size, const char *cmdline)
85{
86 MachineState *ms = MACHINE(qdev_get_machine());
87 void *fdt;
88 int cpu;
89 uint32_t *cells;
90 char *nodename;
91 char ethclk_names[] = "pclk\0hclk";
92 uint32_t plic_phandle, prci_phandle, phandle = 1;
93 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
94
95 fdt = s->fdt = create_device_tree(&s->fdt_size);
96 if (!fdt) {
97 error_report("create_device_tree() failed");
98 exit(1);
99 }
100
101 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
102 qemu_fdt_setprop_string(fdt, "/", "compatible",
103 "sifive,hifive-unleashed-a00");
104 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
105 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
106
107 qemu_fdt_add_subnode(fdt, "/soc");
108 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
109 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
110 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
111 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
112
113 hfclk_phandle = phandle++;
114 nodename = g_strdup_printf("/hfclk");
115 qemu_fdt_add_subnode(fdt, nodename);
116 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
117 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
118 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
119 SIFIVE_U_HFCLK_FREQ);
120 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
121 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
122 g_free(nodename);
123
124 rtcclk_phandle = phandle++;
125 nodename = g_strdup_printf("/rtcclk");
126 qemu_fdt_add_subnode(fdt, nodename);
127 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
128 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
129 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
130 SIFIVE_U_RTCCLK_FREQ);
131 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
132 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
133 g_free(nodename);
134
135 nodename = g_strdup_printf("/memory@%lx",
136 (long)memmap[SIFIVE_U_DRAM].base);
137 qemu_fdt_add_subnode(fdt, nodename);
138 qemu_fdt_setprop_cells(fdt, nodename, "reg",
139 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
140 mem_size >> 32, mem_size);
141 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
142 g_free(nodename);
143
144 qemu_fdt_add_subnode(fdt, "/cpus");
145 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
146 SIFIVE_CLINT_TIMEBASE_FREQ);
147 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
148 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
149
150 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
151 int cpu_phandle = phandle++;
152 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
153 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
154 char *isa;
155 qemu_fdt_add_subnode(fdt, nodename);
156
157 if (cpu != 0) {
158 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
159 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
160 } else {
161 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
162 }
163 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
164 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
165 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
166 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
167 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
168 qemu_fdt_add_subnode(fdt, intc);
169 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
170 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
171 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
172 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
173 g_free(isa);
174 g_free(intc);
175 g_free(nodename);
176 }
177
178 cells = g_new0(uint32_t, ms->smp.cpus * 4);
179 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
180 nodename =
181 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
182 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
183 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
184 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
185 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
186 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
187 g_free(nodename);
188 }
189 nodename = g_strdup_printf("/soc/clint@%lx",
190 (long)memmap[SIFIVE_U_CLINT].base);
191 qemu_fdt_add_subnode(fdt, nodename);
192 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
193 qemu_fdt_setprop_cells(fdt, nodename, "reg",
194 0x0, memmap[SIFIVE_U_CLINT].base,
195 0x0, memmap[SIFIVE_U_CLINT].size);
196 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
197 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
198 g_free(cells);
199 g_free(nodename);
200
201 prci_phandle = phandle++;
202 nodename = g_strdup_printf("/soc/clock-controller@%lx",
203 (long)memmap[SIFIVE_U_PRCI].base);
204 qemu_fdt_add_subnode(fdt, nodename);
205 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
206 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
207 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
208 hfclk_phandle, rtcclk_phandle);
209 qemu_fdt_setprop_cells(fdt, nodename, "reg",
210 0x0, memmap[SIFIVE_U_PRCI].base,
211 0x0, memmap[SIFIVE_U_PRCI].size);
212 qemu_fdt_setprop_string(fdt, nodename, "compatible",
213 "sifive,fu540-c000-prci");
214 g_free(nodename);
215
216 plic_phandle = phandle++;
217 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
218 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
219 nodename =
220 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
221 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
222
223 if (cpu == 0) {
224 cells[0] = cpu_to_be32(intc_phandle);
225 cells[1] = cpu_to_be32(IRQ_M_EXT);
226 } else {
227 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
228 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
229 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
230 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
231 }
232 g_free(nodename);
233 }
234 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
235 (long)memmap[SIFIVE_U_PLIC].base);
236 qemu_fdt_add_subnode(fdt, nodename);
237 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
238 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
239 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
240 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
241 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
242 qemu_fdt_setprop_cells(fdt, nodename, "reg",
243 0x0, memmap[SIFIVE_U_PLIC].base,
244 0x0, memmap[SIFIVE_U_PLIC].size);
245 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
246 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
247 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
248 g_free(cells);
249 g_free(nodename);
250
251 phy_phandle = phandle++;
252 nodename = g_strdup_printf("/soc/ethernet@%lx",
253 (long)memmap[SIFIVE_U_GEM].base);
254 qemu_fdt_add_subnode(fdt, nodename);
255 qemu_fdt_setprop_string(fdt, nodename, "compatible",
256 "sifive,fu540-c000-gem");
257 qemu_fdt_setprop_cells(fdt, nodename, "reg",
258 0x0, memmap[SIFIVE_U_GEM].base,
259 0x0, memmap[SIFIVE_U_GEM].size,
260 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
261 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
262 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
263 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
264 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
265 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
266 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
267 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
268 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
269 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
270 sizeof(ethclk_names));
271 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
272 s->soc.gem.conf.macaddr.a, ETH_ALEN);
273 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
274 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
275
276 qemu_fdt_add_subnode(fdt, "/aliases");
277 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
278
279 g_free(nodename);
280
281 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
282 (long)memmap[SIFIVE_U_GEM].base);
283 qemu_fdt_add_subnode(fdt, nodename);
284 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
285 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
286 g_free(nodename);
287
288 nodename = g_strdup_printf("/soc/serial@%lx",
289 (long)memmap[SIFIVE_U_UART0].base);
290 qemu_fdt_add_subnode(fdt, nodename);
291 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
292 qemu_fdt_setprop_cells(fdt, nodename, "reg",
293 0x0, memmap[SIFIVE_U_UART0].base,
294 0x0, memmap[SIFIVE_U_UART0].size);
295 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
296 prci_phandle, PRCI_CLK_TLCLK);
297 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
298 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
299
300 qemu_fdt_add_subnode(fdt, "/chosen");
301 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
302 if (cmdline) {
303 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
304 }
305
306 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
307
308 g_free(nodename);
309}
310
311static void riscv_sifive_u_init(MachineState *machine)
312{
313 const struct MemmapEntry *memmap = sifive_u_memmap;
314 SiFiveUState *s = RISCV_U_MACHINE(machine);
315 MemoryRegion *system_memory = get_system_memory();
316 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
317 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
318 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
319 int i;
320
321
322 object_initialize_child(OBJECT(machine), "soc", &s->soc,
323 sizeof(s->soc), TYPE_RISCV_U_SOC,
324 &error_abort, NULL);
325 object_property_set_bool(OBJECT(&s->soc), true, "realized",
326 &error_abort);
327
328
329 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
330 machine->ram_size, &error_fatal);
331 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
332 main_mem);
333
334
335 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
336 memmap[SIFIVE_U_FLASH0].size, &error_fatal);
337 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
338 flash0);
339
340
341 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
342
343 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
344 memmap[SIFIVE_U_DRAM].base);
345
346 if (machine->kernel_filename) {
347 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
348 NULL);
349
350 if (machine->initrd_filename) {
351 hwaddr start;
352 hwaddr end = riscv_load_initrd(machine->initrd_filename,
353 machine->ram_size, kernel_entry,
354 &start);
355 qemu_fdt_setprop_cell(s->fdt, "/chosen",
356 "linux,initrd-start", start);
357 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
358 end);
359 }
360 }
361
362 if (s->start_in_flash) {
363 start_addr = memmap[SIFIVE_U_FLASH0].base;
364 }
365
366
367 uint32_t reset_vec[8] = {
368 0x00000297,
369 0x02028593,
370 0xf1402573,
371#if defined(TARGET_RISCV32)
372 0x0182a283,
373#elif defined(TARGET_RISCV64)
374 0x0182b283,
375#endif
376 0x00028067,
377 0x00000000,
378 start_addr,
379 0x00000000,
380
381 };
382
383
384 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
385 reset_vec[i] = cpu_to_le32(reset_vec[i]);
386 }
387 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
388 memmap[SIFIVE_U_MROM].base, &address_space_memory);
389
390
391 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
392 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
393 error_report("not enough space to store device-tree");
394 exit(1);
395 }
396 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
397 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
398 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
399 &address_space_memory);
400}
401
402static void riscv_sifive_u_soc_init(Object *obj)
403{
404 MachineState *ms = MACHINE(qdev_get_machine());
405 SiFiveUSoCState *s = RISCV_U_SOC(obj);
406
407 object_initialize_child(obj, "e-cluster", &s->e_cluster,
408 sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
409 &error_abort, NULL);
410 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
411
412 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
413 &s->e_cpus, sizeof(s->e_cpus),
414 TYPE_RISCV_HART_ARRAY, &error_abort,
415 NULL);
416 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
417 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
418 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
419
420 object_initialize_child(obj, "u-cluster", &s->u_cluster,
421 sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
422 &error_abort, NULL);
423 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
424
425 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
426 &s->u_cpus, sizeof(s->u_cpus),
427 TYPE_RISCV_HART_ARRAY, &error_abort,
428 NULL);
429 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
430 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
431 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
432
433 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
434 TYPE_SIFIVE_U_PRCI);
435 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
436 TYPE_SIFIVE_U_OTP);
437 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
438 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
439 TYPE_CADENCE_GEM);
440}
441
442static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
443{
444 SiFiveUState *s = RISCV_U_MACHINE(obj);
445
446 return s->start_in_flash;
447}
448
449static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
450{
451 SiFiveUState *s = RISCV_U_MACHINE(obj);
452
453 s->start_in_flash = value;
454}
455
456static void riscv_sifive_u_machine_instance_init(Object *obj)
457{
458 SiFiveUState *s = RISCV_U_MACHINE(obj);
459
460 s->start_in_flash = false;
461 object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
462 sifive_u_set_start_in_flash, NULL);
463 object_property_set_description(obj, "start-in-flash",
464 "Set on to tell QEMU's ROM to jump to " \
465 "flash. Otherwise QEMU will jump to DRAM",
466 NULL);
467}
468
469static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
470{
471 MachineState *ms = MACHINE(qdev_get_machine());
472 SiFiveUSoCState *s = RISCV_U_SOC(dev);
473 const struct MemmapEntry *memmap = sifive_u_memmap;
474 MemoryRegion *system_memory = get_system_memory();
475 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
476 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
477 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
478 char *plic_hart_config;
479 size_t plic_hart_config_len;
480 int i;
481 Error *err = NULL;
482 NICInfo *nd = &nd_table[0];
483
484 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
485 &error_abort);
486 object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
487 &error_abort);
488
489
490
491
492
493
494 object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
495 &error_abort);
496 object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
497 &error_abort);
498
499
500 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
501 memmap[SIFIVE_U_MROM].size, &error_fatal);
502 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
503 mask_rom);
504
505
506
507
508
509
510
511
512
513
514 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
515 memmap[SIFIVE_U_L2LIM].size, &error_fatal);
516 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
517 l2lim_mem);
518
519
520 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
521 ms->smp.cpus;
522 plic_hart_config = g_malloc0(plic_hart_config_len);
523 for (i = 0; i < ms->smp.cpus; i++) {
524 if (i != 0) {
525 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
526 plic_hart_config_len);
527 } else {
528 strncat(plic_hart_config, "M", plic_hart_config_len);
529 }
530 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
531 }
532
533
534 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
535 plic_hart_config,
536 SIFIVE_U_PLIC_NUM_SOURCES,
537 SIFIVE_U_PLIC_NUM_PRIORITIES,
538 SIFIVE_U_PLIC_PRIORITY_BASE,
539 SIFIVE_U_PLIC_PENDING_BASE,
540 SIFIVE_U_PLIC_ENABLE_BASE,
541 SIFIVE_U_PLIC_ENABLE_STRIDE,
542 SIFIVE_U_PLIC_CONTEXT_BASE,
543 SIFIVE_U_PLIC_CONTEXT_STRIDE,
544 memmap[SIFIVE_U_PLIC].size);
545 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
546 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
547 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
548 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
549 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
550 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
551 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
552
553 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
554 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
555
556 object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
557 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
558
559 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
560 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
561 }
562
563 if (nd->used) {
564 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
565 qdev_set_nic_properties(DEVICE(&s->gem), nd);
566 }
567 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
568 &error_abort);
569 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
570 if (err) {
571 error_propagate(errp, err);
572 return;
573 }
574 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
575 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
576 plic_gpios[SIFIVE_U_GEM_IRQ]);
577
578 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
579 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
580}
581
582static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
583{
584 DeviceClass *dc = DEVICE_CLASS(oc);
585
586 dc->realize = riscv_sifive_u_soc_realize;
587
588 dc->user_creatable = false;
589}
590
591static const TypeInfo riscv_sifive_u_soc_type_info = {
592 .name = TYPE_RISCV_U_SOC,
593 .parent = TYPE_DEVICE,
594 .instance_size = sizeof(SiFiveUSoCState),
595 .instance_init = riscv_sifive_u_soc_init,
596 .class_init = riscv_sifive_u_soc_class_init,
597};
598
599static void riscv_sifive_u_soc_register_types(void)
600{
601 type_register_static(&riscv_sifive_u_soc_type_info);
602}
603
604type_init(riscv_sifive_u_soc_register_types)
605
606static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
607{
608 MachineClass *mc = MACHINE_CLASS(oc);
609
610 mc->desc = "RISC-V Board compatible with SiFive U SDK";
611 mc->init = riscv_sifive_u_init;
612 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
613 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
614 mc->default_cpus = mc->min_cpus;
615}
616
617static const TypeInfo riscv_sifive_u_machine_typeinfo = {
618 .name = MACHINE_TYPE_NAME("sifive_u"),
619 .parent = TYPE_MACHINE,
620 .class_init = riscv_sifive_u_machine_class_init,
621 .instance_init = riscv_sifive_u_machine_instance_init,
622 .instance_size = sizeof(SiFiveUState),
623};
624
625static void riscv_sifive_u_machine_init_register_types(void)
626{
627 type_register_static(&riscv_sifive_u_machine_typeinfo);
628}
629
630type_init(riscv_sifive_u_machine_init_register_types)
631
