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24#include "qemu/osdep.h"
25#include "qemu/log.h"
26#include "qemu/module.h"
27#include "hw/sysbus.h"
28#include "migration/vmstate.h"
29#include "trace.h"
30#include "qapi/error.h"
31#include "sysemu/block-backend.h"
32#include "sysemu/blockdev.h"
33#include "hw/qdev-properties.h"
34#include "hw/sd/sd.h"
35
36enum {
37 ENABLE_CMD_TX = (1<<0),
38 ENABLE_CMD_RX = (1<<1),
39 ENABLE_DAT_TX = (1<<2),
40 ENABLE_DAT_RX = (1<<3),
41};
42
43enum {
44 PENDING_CMD_TX = (1<<0),
45 PENDING_CMD_RX = (1<<1),
46 PENDING_DAT_TX = (1<<2),
47 PENDING_DAT_RX = (1<<3),
48};
49
50enum {
51 START_CMD_TX = (1<<0),
52 START_DAT_RX = (1<<1),
53};
54
55enum {
56 R_CLK2XDIV = 0,
57 R_ENABLE,
58 R_PENDING,
59 R_START,
60 R_CMD,
61 R_DAT,
62 R_MAX
63};
64
65#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
66#define MILKYMIST_MEMCARD(obj) \
67 OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
68
69struct MilkymistMemcardState {
70 SysBusDevice parent_obj;
71
72 MemoryRegion regs_region;
73 SDBus sdbus;
74
75 int command_write_ptr;
76 int response_read_ptr;
77 int response_len;
78 int ignore_next_cmd;
79 int enabled;
80 uint8_t command[6];
81 uint8_t response[17];
82 uint32_t regs[R_MAX];
83};
84typedef struct MilkymistMemcardState MilkymistMemcardState;
85
86static void update_pending_bits(MilkymistMemcardState *s)
87{
88
89 s->regs[R_PENDING] = 0;
90
91 if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
92 s->regs[R_PENDING] |= PENDING_CMD_RX;
93 }
94 if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
95 s->regs[R_PENDING] |= PENDING_DAT_RX;
96 }
97}
98
99static void memcard_sd_command(MilkymistMemcardState *s)
100{
101 SDRequest req;
102
103 req.cmd = s->command[0] & 0x3f;
104 req.arg = ldl_be_p(s->command + 1);
105 req.crc = s->command[5];
106
107 s->response[0] = req.cmd;
108 s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
109 s->response_read_ptr = 0;
110
111 if (s->response_len == 16) {
112
113 s->response[0] = 0x3f;
114 s->response_len += 1;
115 } else if (s->response_len == 4) {
116
117 s->response[5] = 0;
118 s->response_len += 2;
119 }
120
121 if (req.cmd == 0) {
122
123
124 s->ignore_next_cmd = 1;
125 }
126}
127
128static uint64_t memcard_read(void *opaque, hwaddr addr,
129 unsigned size)
130{
131 MilkymistMemcardState *s = opaque;
132 uint32_t r = 0;
133
134 addr >>= 2;
135 switch (addr) {
136 case R_CMD:
137 if (!s->enabled) {
138 r = 0xff;
139 } else {
140 r = s->response[s->response_read_ptr++];
141 if (s->response_read_ptr > s->response_len) {
142 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
143 "read more cmd bytes than available: clipping\n");
144 s->response_read_ptr = 0;
145 }
146 }
147 break;
148 case R_DAT:
149 if (!s->enabled) {
150 r = 0xffffffff;
151 } else {
152 r = 0;
153 r |= sdbus_read_data(&s->sdbus) << 24;
154 r |= sdbus_read_data(&s->sdbus) << 16;
155 r |= sdbus_read_data(&s->sdbus) << 8;
156 r |= sdbus_read_data(&s->sdbus);
157 }
158 break;
159 case R_CLK2XDIV:
160 case R_ENABLE:
161 case R_PENDING:
162 case R_START:
163 r = s->regs[addr];
164 break;
165
166 default:
167 qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
168 "read access to unknown register 0x%" HWADDR_PRIx "\n",
169 addr << 2);
170 break;
171 }
172
173 trace_milkymist_memcard_memory_read(addr << 2, r);
174
175 return r;
176}
177
178static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
179 unsigned size)
180{
181 MilkymistMemcardState *s = opaque;
182
183 trace_milkymist_memcard_memory_write(addr, value);
184
185 addr >>= 2;
186 switch (addr) {
187 case R_PENDING:
188
189 s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
190 update_pending_bits(s);
191 break;
192 case R_CMD:
193 if (!s->enabled) {
194 break;
195 }
196 if (s->ignore_next_cmd) {
197 s->ignore_next_cmd = 0;
198 break;
199 }
200 s->command[s->command_write_ptr] = value & 0xff;
201 s->command_write_ptr = (s->command_write_ptr + 1) % 6;
202 if (s->command_write_ptr == 0) {
203 memcard_sd_command(s);
204 }
205 break;
206 case R_DAT:
207 if (!s->enabled) {
208 break;
209 }
210 sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
211 sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
212 sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
213 sdbus_write_data(&s->sdbus, value & 0xff);
214 break;
215 case R_ENABLE:
216 s->regs[addr] = value;
217 update_pending_bits(s);
218 break;
219 case R_CLK2XDIV:
220 case R_START:
221 s->regs[addr] = value;
222 break;
223
224 default:
225 qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
226 "write access to unknown register 0x%" HWADDR_PRIx " "
227 "(value 0x%" PRIx64 ")\n", addr << 2, value);
228 break;
229 }
230}
231
232static const MemoryRegionOps memcard_mmio_ops = {
233 .read = memcard_read,
234 .write = memcard_write,
235 .valid = {
236 .min_access_size = 4,
237 .max_access_size = 4,
238 },
239 .endianness = DEVICE_NATIVE_ENDIAN,
240};
241
242static void milkymist_memcard_reset(DeviceState *d)
243{
244 MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
245 int i;
246
247 s->command_write_ptr = 0;
248 s->response_read_ptr = 0;
249 s->response_len = 0;
250
251 for (i = 0; i < R_MAX; i++) {
252 s->regs[i] = 0;
253 }
254}
255
256static void milkymist_memcard_init(Object *obj)
257{
258 MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
259 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
260
261 memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
262 "milkymist-memcard", R_MAX * 4);
263 sysbus_init_mmio(dev, &s->regs_region);
264}
265
266static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
267{
268 MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
269 DeviceState *carddev;
270 BlockBackend *blk;
271 DriveInfo *dinfo;
272 Error *err = NULL;
273
274 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
275 dev, "sd-bus");
276
277
278
279 dinfo = drive_get_next(IF_SD);
280 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
281 carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD);
282 qdev_prop_set_drive(carddev, "drive", blk, &err);
283 object_property_set_bool(OBJECT(carddev), true, "realized", &err);
284 if (err) {
285 error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
286 return;
287 }
288 s->enabled = blk && blk_is_inserted(blk);
289}
290
291static const VMStateDescription vmstate_milkymist_memcard = {
292 .name = "milkymist-memcard",
293 .version_id = 1,
294 .minimum_version_id = 1,
295 .fields = (VMStateField[]) {
296 VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
297 VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
298 VMSTATE_INT32(response_len, MilkymistMemcardState),
299 VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
300 VMSTATE_INT32(enabled, MilkymistMemcardState),
301 VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
302 VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
303 VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
304 VMSTATE_END_OF_LIST()
305 }
306};
307
308static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
309{
310 DeviceClass *dc = DEVICE_CLASS(klass);
311
312 dc->realize = milkymist_memcard_realize;
313 dc->reset = milkymist_memcard_reset;
314 dc->vmsd = &vmstate_milkymist_memcard;
315
316 dc->user_creatable = false;
317}
318
319static const TypeInfo milkymist_memcard_info = {
320 .name = TYPE_MILKYMIST_MEMCARD,
321 .parent = TYPE_SYS_BUS_DEVICE,
322 .instance_size = sizeof(MilkymistMemcardState),
323 .instance_init = milkymist_memcard_init,
324 .class_init = milkymist_memcard_class_init,
325};
326
327static void milkymist_memcard_register_types(void)
328{
329 type_register_static(&milkymist_memcard_info);
330}
331
332type_init(milkymist_memcard_register_types)
333
