qemu/hw/sh4/r2d.c
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   1/*
   2 * Renesas SH7751R R2D-PLUS emulation
   3 *
   4 * Copyright (c) 2007 Magnus Damm
   5 * Copyright (c) 2008 Paul Mundt
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "qemu/units.h"
  28#include "qapi/error.h"
  29#include "cpu.h"
  30#include "hw/sysbus.h"
  31#include "hw/sh4/sh.h"
  32#include "sysemu/reset.h"
  33#include "sysemu/runstate.h"
  34#include "sysemu/sysemu.h"
  35#include "hw/boards.h"
  36#include "hw/pci/pci.h"
  37#include "hw/qdev-properties.h"
  38#include "net/net.h"
  39#include "sh7750_regs.h"
  40#include "hw/ide.h"
  41#include "hw/irq.h"
  42#include "hw/loader.h"
  43#include "hw/usb.h"
  44#include "hw/block/flash.h"
  45#include "exec/address-spaces.h"
  46
  47#define FLASH_BASE 0x00000000
  48#define FLASH_SIZE (16 * MiB)
  49
  50#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  51#define SDRAM_SIZE 0x04000000
  52
  53#define SM501_VRAM_SIZE 0x800000
  54
  55#define BOOT_PARAMS_OFFSET 0x0010000
  56/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  57#define LINUX_LOAD_OFFSET  0x0800000
  58#define INITRD_LOAD_OFFSET 0x1800000
  59
  60#define PA_IRLMSK       0x00
  61#define PA_POWOFF       0x30
  62#define PA_VERREG       0x32
  63#define PA_OUTPORT      0x36
  64
  65typedef struct {
  66    uint16_t bcr;
  67    uint16_t irlmsk;
  68    uint16_t irlmon;
  69    uint16_t cfctl;
  70    uint16_t cfpow;
  71    uint16_t dispctl;
  72    uint16_t sdmpow;
  73    uint16_t rtcce;
  74    uint16_t pcicd;
  75    uint16_t voyagerrts;
  76    uint16_t cfrst;
  77    uint16_t admrts;
  78    uint16_t extrst;
  79    uint16_t cfcdintclr;
  80    uint16_t keyctlclr;
  81    uint16_t pad0;
  82    uint16_t pad1;
  83    uint16_t verreg;
  84    uint16_t inport;
  85    uint16_t outport;
  86    uint16_t bverreg;
  87
  88/* output pin */
  89    qemu_irq irl;
  90    MemoryRegion iomem;
  91} r2d_fpga_t;
  92
  93enum r2d_fpga_irq {
  94    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  95    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  96    NR_IRQS
  97};
  98
  99static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
 100    [CF_IDE]    = {  1, 1<<9 },
 101    [CF_CD]     = {  2, 1<<8 },
 102    [PCI_INTA]  = {  9, 1<<14 },
 103    [PCI_INTB]  = { 10, 1<<13 },
 104    [PCI_INTC]  = {  3, 1<<12 },
 105    [PCI_INTD]  = {  0, 1<<11 },
 106    [SM501]     = {  4, 1<<10 },
 107    [KEY]       = {  5, 1<<6 },
 108    [RTC_A]     = {  6, 1<<5 },
 109    [RTC_T]     = {  7, 1<<4 },
 110    [SDCARD]    = {  8, 1<<7 },
 111    [EXT]       = { 11, 1<<0 },
 112    [TP]        = { 12, 1<<15 },
 113};
 114
 115static void update_irl(r2d_fpga_t *fpga)
 116{
 117    int i, irl = 15;
 118    for (i = 0; i < NR_IRQS; i++)
 119        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 120            if (irqtab[i].irl < irl)
 121                irl = irqtab[i].irl;
 122    qemu_set_irq(fpga->irl, irl ^ 15);
 123}
 124
 125static void r2d_fpga_irq_set(void *opaque, int n, int level)
 126{
 127    r2d_fpga_t *fpga = opaque;
 128    if (level)
 129        fpga->irlmon |= irqtab[n].msk;
 130    else
 131        fpga->irlmon &= ~irqtab[n].msk;
 132    update_irl(fpga);
 133}
 134
 135static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
 136{
 137    r2d_fpga_t *s = opaque;
 138
 139    switch (addr) {
 140    case PA_IRLMSK:
 141        return s->irlmsk;
 142    case PA_OUTPORT:
 143        return s->outport;
 144    case PA_POWOFF:
 145        return 0x00;
 146    case PA_VERREG:
 147        return 0x10;
 148    }
 149
 150    return 0;
 151}
 152
 153static void
 154r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
 155{
 156    r2d_fpga_t *s = opaque;
 157
 158    switch (addr) {
 159    case PA_IRLMSK:
 160        s->irlmsk = value;
 161        update_irl(s);
 162        break;
 163    case PA_OUTPORT:
 164        s->outport = value;
 165        break;
 166    case PA_POWOFF:
 167        if (value & 1) {
 168            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 169        }
 170        break;
 171    case PA_VERREG:
 172        /* Discard writes */
 173        break;
 174    }
 175}
 176
 177static const MemoryRegionOps r2d_fpga_ops = {
 178    .read = r2d_fpga_read,
 179    .write = r2d_fpga_write,
 180    .impl.min_access_size = 2,
 181    .impl.max_access_size = 2,
 182    .endianness = DEVICE_NATIVE_ENDIAN,
 183};
 184
 185static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
 186                               hwaddr base, qemu_irq irl)
 187{
 188    r2d_fpga_t *s;
 189
 190    s = g_malloc0(sizeof(r2d_fpga_t));
 191
 192    s->irl = irl;
 193
 194    memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
 195    memory_region_add_subregion(sysmem, base, &s->iomem);
 196    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 197}
 198
 199typedef struct ResetData {
 200    SuperHCPU *cpu;
 201    uint32_t vector;
 202} ResetData;
 203
 204static void main_cpu_reset(void *opaque)
 205{
 206    ResetData *s = (ResetData *)opaque;
 207    CPUSH4State *env = &s->cpu->env;
 208
 209    cpu_reset(CPU(s->cpu));
 210    env->pc = s->vector;
 211}
 212
 213static struct QEMU_PACKED
 214{
 215    int mount_root_rdonly;
 216    int ramdisk_flags;
 217    int orig_root_dev;
 218    int loader_type;
 219    int initrd_start;
 220    int initrd_size;
 221
 222    char pad[232];
 223
 224    char kernel_cmdline[256] QEMU_NONSTRING;
 225} boot_params;
 226
 227static void r2d_init(MachineState *machine)
 228{
 229    const char *kernel_filename = machine->kernel_filename;
 230    const char *kernel_cmdline = machine->kernel_cmdline;
 231    const char *initrd_filename = machine->initrd_filename;
 232    SuperHCPU *cpu;
 233    CPUSH4State *env;
 234    ResetData *reset_info;
 235    struct SH7750State *s;
 236    MemoryRegion *sdram = g_new(MemoryRegion, 1);
 237    qemu_irq *irq;
 238    DriveInfo *dinfo;
 239    int i;
 240    DeviceState *dev;
 241    SysBusDevice *busdev;
 242    MemoryRegion *address_space_mem = get_system_memory();
 243    PCIBus *pci_bus;
 244
 245    cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
 246    env = &cpu->env;
 247
 248    reset_info = g_malloc0(sizeof(ResetData));
 249    reset_info->cpu = cpu;
 250    reset_info->vector = env->pc;
 251    qemu_register_reset(main_cpu_reset, reset_info);
 252
 253    /* Allocate memory space */
 254    memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
 255    memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
 256    /* Register peripherals */
 257    s = sh7750_init(cpu, address_space_mem);
 258    irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
 259
 260    dev = qdev_create(NULL, "sh_pci");
 261    busdev = SYS_BUS_DEVICE(dev);
 262    qdev_init_nofail(dev);
 263    pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
 264    sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
 265    sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
 266    sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
 267    sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
 268    sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
 269    sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
 270
 271    dev = qdev_create(NULL, "sysbus-sm501");
 272    busdev = SYS_BUS_DEVICE(dev);
 273    qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
 274    qdev_prop_set_uint32(dev, "base", 0x10000000);
 275    qdev_prop_set_ptr(dev, "chr-state", serial_hd(2));
 276    qdev_init_nofail(dev);
 277    sysbus_mmio_map(busdev, 0, 0x10000000);
 278    sysbus_mmio_map(busdev, 1, 0x13e00000);
 279    sysbus_connect_irq(busdev, 0, irq[SM501]);
 280
 281    /* onboard CF (True IDE mode, Master only). */
 282    dinfo = drive_get(IF_IDE, 0, 0);
 283    dev = qdev_create(NULL, "mmio-ide");
 284    busdev = SYS_BUS_DEVICE(dev);
 285    sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
 286    qdev_prop_set_uint32(dev, "shift", 1);
 287    qdev_init_nofail(dev);
 288    sysbus_mmio_map(busdev, 0, 0x14001000);
 289    sysbus_mmio_map(busdev, 1, 0x1400080c);
 290    mmio_ide_init_drives(dev, dinfo, NULL);
 291
 292    /*
 293     * Onboard flash memory
 294     * According to the old board user document in Japanese (under
 295     * NDA) what is referred to as FROM (Area0) is connected via a
 296     * 32-bit bus and CS0 to CN8. The docs mention a Cypress
 297     * S29PL127J60TFI130 chipsset.  Per the 'S29PL-J 002-00615
 298     * Rev. *E' datasheet, it is a 128Mbit NOR parallel flash
 299     * addressable in words of 16bit.
 300     */
 301    dinfo = drive_get(IF_PFLASH, 0, 0);
 302    pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
 303                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 304                          64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
 305                          0x555, 0x2aa, 0);
 306
 307    /* NIC: rtl8139 on-board, and 2 slots. */
 308    for (i = 0; i < nb_nics; i++)
 309        pci_nic_init_nofail(&nd_table[i], pci_bus,
 310                            "rtl8139", i==0 ? "2" : NULL);
 311
 312    /* USB keyboard */
 313    usb_create_simple(usb_bus_find(-1), "usb-kbd");
 314
 315    /* Todo: register on board registers */
 316    memset(&boot_params, 0, sizeof(boot_params));
 317
 318    if (kernel_filename) {
 319        int kernel_size;
 320
 321        kernel_size = load_image_targphys(kernel_filename,
 322                                          SDRAM_BASE + LINUX_LOAD_OFFSET,
 323                                          INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 324        if (kernel_size < 0) {
 325          fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 326          exit(1);
 327        }
 328
 329        /* initialization which should be done by firmware */
 330        address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
 331                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
 332        address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
 333                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
 334        reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 335    }
 336
 337    if (initrd_filename) {
 338        int initrd_size;
 339
 340        initrd_size = load_image_targphys(initrd_filename,
 341                                          SDRAM_BASE + INITRD_LOAD_OFFSET,
 342                                          SDRAM_SIZE - INITRD_LOAD_OFFSET);
 343
 344        if (initrd_size < 0) {
 345          fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 346          exit(1);
 347        }
 348
 349        /* initialization which should be done by firmware */
 350        boot_params.loader_type = tswap32(1);
 351        boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
 352        boot_params.initrd_size = tswap32(initrd_size);
 353    }
 354
 355    if (kernel_cmdline) {
 356        /* I see no evidence that this .kernel_cmdline buffer requires
 357           NUL-termination, so using strncpy should be ok. */
 358        strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 359                sizeof(boot_params.kernel_cmdline));
 360    }
 361
 362    rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 363                       SDRAM_BASE + BOOT_PARAMS_OFFSET);
 364}
 365
 366static void r2d_machine_init(MachineClass *mc)
 367{
 368    mc->desc = "r2d-plus board";
 369    mc->init = r2d_init;
 370    mc->block_default_type = IF_IDE;
 371    mc->default_cpu_type = TYPE_SH7751R_CPU;
 372}
 373
 374DEFINE_MACHINE("r2d", r2d_machine_init)
 375