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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "sysemu/reset.h"
28#include "sysemu/runstate.h"
29#include "qemu/module.h"
30#include "qemu/timer.h"
31#include "hw/irq.h"
32#include "hw/ptimer.h"
33
34#define D(x)
35
36#define RW_TMR0_DIV 0x00
37#define R_TMR0_DATA 0x04
38#define RW_TMR0_CTRL 0x08
39#define RW_TMR1_DIV 0x10
40#define R_TMR1_DATA 0x14
41#define RW_TMR1_CTRL 0x18
42#define R_TIME 0x38
43#define RW_WD_CTRL 0x40
44#define R_WD_STAT 0x44
45#define RW_INTR_MASK 0x48
46#define RW_ACK_INTR 0x4c
47#define R_INTR 0x50
48#define R_MASKED_INTR 0x54
49
50#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
51#define ETRAX_TIMER(obj) \
52 OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
53
54typedef struct ETRAXTimerState {
55 SysBusDevice parent_obj;
56
57 MemoryRegion mmio;
58 qemu_irq irq;
59 qemu_irq nmi;
60
61 ptimer_state *ptimer_t0;
62 ptimer_state *ptimer_t1;
63 ptimer_state *ptimer_wd;
64
65 int wd_hits;
66
67
68 uint32_t rw_tmr0_div;
69 uint32_t r_tmr0_data;
70 uint32_t rw_tmr0_ctrl;
71
72 uint32_t rw_tmr1_div;
73 uint32_t r_tmr1_data;
74 uint32_t rw_tmr1_ctrl;
75
76 uint32_t rw_wd_ctrl;
77
78 uint32_t rw_intr_mask;
79 uint32_t rw_ack_intr;
80 uint32_t r_intr;
81 uint32_t r_masked_intr;
82} ETRAXTimerState;
83
84static uint64_t
85timer_read(void *opaque, hwaddr addr, unsigned int size)
86{
87 ETRAXTimerState *t = opaque;
88 uint32_t r = 0;
89
90 switch (addr) {
91 case R_TMR0_DATA:
92 r = ptimer_get_count(t->ptimer_t0);
93 break;
94 case R_TMR1_DATA:
95 r = ptimer_get_count(t->ptimer_t1);
96 break;
97 case R_TIME:
98 r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
99 break;
100 case RW_INTR_MASK:
101 r = t->rw_intr_mask;
102 break;
103 case R_MASKED_INTR:
104 r = t->r_intr & t->rw_intr_mask;
105 break;
106 default:
107 D(printf ("%s %x\n", __func__, addr));
108 break;
109 }
110 return r;
111}
112
113static void update_ctrl(ETRAXTimerState *t, int tnum)
114{
115 unsigned int op;
116 unsigned int freq;
117 unsigned int freq_hz;
118 unsigned int div;
119 uint32_t ctrl;
120
121 ptimer_state *timer;
122
123 if (tnum == 0) {
124 ctrl = t->rw_tmr0_ctrl;
125 div = t->rw_tmr0_div;
126 timer = t->ptimer_t0;
127 } else {
128 ctrl = t->rw_tmr1_ctrl;
129 div = t->rw_tmr1_div;
130 timer = t->ptimer_t1;
131 }
132
133
134 op = ctrl & 3;
135 freq = ctrl >> 2;
136 freq_hz = 32000000;
137
138 switch (freq)
139 {
140 case 0:
141 case 1:
142 D(printf ("extern or disabled timer clock?\n"));
143 break;
144 case 4: freq_hz = 29493000; break;
145 case 5: freq_hz = 32000000; break;
146 case 6: freq_hz = 32768000; break;
147 case 7: freq_hz = 100000000; break;
148 default:
149 abort();
150 break;
151 }
152
153 D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
154 ptimer_transaction_begin(timer);
155 ptimer_set_freq(timer, freq_hz);
156 ptimer_set_limit(timer, div, 0);
157
158 switch (op)
159 {
160 case 0:
161
162 ptimer_set_limit(timer, div, 1);
163 break;
164 case 1:
165
166 ptimer_stop(timer);
167 break;
168 case 2:
169
170 ptimer_run(timer, 0);
171 break;
172 default:
173 abort();
174 break;
175 }
176 ptimer_transaction_commit(timer);
177}
178
179static void timer_update_irq(ETRAXTimerState *t)
180{
181 t->r_intr &= ~(t->rw_ack_intr);
182 t->r_masked_intr = t->r_intr & t->rw_intr_mask;
183
184 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
185 qemu_set_irq(t->irq, !!t->r_masked_intr);
186}
187
188static void timer0_hit(void *opaque)
189{
190 ETRAXTimerState *t = opaque;
191 t->r_intr |= 1;
192 timer_update_irq(t);
193}
194
195static void timer1_hit(void *opaque)
196{
197 ETRAXTimerState *t = opaque;
198 t->r_intr |= 2;
199 timer_update_irq(t);
200}
201
202static void watchdog_hit(void *opaque)
203{
204 ETRAXTimerState *t = opaque;
205 if (t->wd_hits == 0) {
206
207
208 ptimer_set_count(t->ptimer_wd, 10);
209 ptimer_run(t->ptimer_wd, 1);
210 qemu_irq_raise(t->nmi);
211 }
212 else
213 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
214
215 t->wd_hits++;
216}
217
218static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
219{
220 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
221 unsigned int wd_key = t->rw_wd_ctrl >> 9;
222 unsigned int wd_cnt = t->rw_wd_ctrl & 511;
223 unsigned int new_key = value >> 9 & ((1 << 7) - 1);
224 unsigned int new_cmd = (value >> 8) & 1;
225
226
227
228 wd_key = ~wd_key & ((1 << 7) - 1);
229
230 if (wd_en && wd_key != new_key)
231 return;
232
233 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
234 wd_en, new_key, wd_key, new_cmd, wd_cnt));
235
236 if (t->wd_hits)
237 qemu_irq_lower(t->nmi);
238
239 t->wd_hits = 0;
240
241 ptimer_transaction_begin(t->ptimer_wd);
242 ptimer_set_freq(t->ptimer_wd, 760);
243 if (wd_cnt == 0)
244 wd_cnt = 256;
245 ptimer_set_count(t->ptimer_wd, wd_cnt);
246 if (new_cmd)
247 ptimer_run(t->ptimer_wd, 1);
248 else
249 ptimer_stop(t->ptimer_wd);
250
251 t->rw_wd_ctrl = value;
252 ptimer_transaction_commit(t->ptimer_wd);
253}
254
255static void
256timer_write(void *opaque, hwaddr addr,
257 uint64_t val64, unsigned int size)
258{
259 ETRAXTimerState *t = opaque;
260 uint32_t value = val64;
261
262 switch (addr)
263 {
264 case RW_TMR0_DIV:
265 t->rw_tmr0_div = value;
266 break;
267 case RW_TMR0_CTRL:
268 D(printf ("RW_TMR0_CTRL=%x\n", value));
269 t->rw_tmr0_ctrl = value;
270 update_ctrl(t, 0);
271 break;
272 case RW_TMR1_DIV:
273 t->rw_tmr1_div = value;
274 break;
275 case RW_TMR1_CTRL:
276 D(printf ("RW_TMR1_CTRL=%x\n", value));
277 t->rw_tmr1_ctrl = value;
278 update_ctrl(t, 1);
279 break;
280 case RW_INTR_MASK:
281 D(printf ("RW_INTR_MASK=%x\n", value));
282 t->rw_intr_mask = value;
283 timer_update_irq(t);
284 break;
285 case RW_WD_CTRL:
286 timer_watchdog_update(t, value);
287 break;
288 case RW_ACK_INTR:
289 t->rw_ack_intr = value;
290 timer_update_irq(t);
291 t->rw_ack_intr = 0;
292 break;
293 default:
294 printf ("%s " TARGET_FMT_plx " %x\n",
295 __func__, addr, value);
296 break;
297 }
298}
299
300static const MemoryRegionOps timer_ops = {
301 .read = timer_read,
302 .write = timer_write,
303 .endianness = DEVICE_LITTLE_ENDIAN,
304 .valid = {
305 .min_access_size = 4,
306 .max_access_size = 4
307 }
308};
309
310static void etraxfs_timer_reset(void *opaque)
311{
312 ETRAXTimerState *t = opaque;
313
314 ptimer_transaction_begin(t->ptimer_t0);
315 ptimer_stop(t->ptimer_t0);
316 ptimer_transaction_commit(t->ptimer_t0);
317 ptimer_transaction_begin(t->ptimer_t1);
318 ptimer_stop(t->ptimer_t1);
319 ptimer_transaction_commit(t->ptimer_t1);
320 ptimer_transaction_begin(t->ptimer_wd);
321 ptimer_stop(t->ptimer_wd);
322 ptimer_transaction_commit(t->ptimer_wd);
323 t->rw_wd_ctrl = 0;
324 t->r_intr = 0;
325 t->rw_intr_mask = 0;
326 qemu_irq_lower(t->irq);
327}
328
329static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
330{
331 ETRAXTimerState *t = ETRAX_TIMER(dev);
332 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
333
334 t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
335 t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
336 t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
337
338 sysbus_init_irq(sbd, &t->irq);
339 sysbus_init_irq(sbd, &t->nmi);
340
341 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
342 "etraxfs-timer", 0x5c);
343 sysbus_init_mmio(sbd, &t->mmio);
344 qemu_register_reset(etraxfs_timer_reset, t);
345}
346
347static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
348{
349 DeviceClass *dc = DEVICE_CLASS(klass);
350
351 dc->realize = etraxfs_timer_realize;
352}
353
354static const TypeInfo etraxfs_timer_info = {
355 .name = TYPE_ETRAX_FS_TIMER,
356 .parent = TYPE_SYS_BUS_DEVICE,
357 .instance_size = sizeof(ETRAXTimerState),
358 .class_init = etraxfs_timer_class_init,
359};
360
361static void etraxfs_timer_register_types(void)
362{
363 type_register_static(&etraxfs_timer_info);
364}
365
366type_init(etraxfs_timer_register_types)
367
