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22#include "qemu/osdep.h"
23#include "qemu/module.h"
24#include "qemu/timer.h"
25#include "hw/usb.h"
26#include "hw/arm/omap.h"
27#include "hw/hw.h"
28#include "hw/irq.h"
29#include "hw/sysbus.h"
30
31#define TYPE_TUSB6010 "tusb6010"
32#define TUSB(obj) OBJECT_CHECK(TUSBState, (obj), TYPE_TUSB6010)
33
34typedef struct TUSBState {
35 SysBusDevice parent_obj;
36
37 MemoryRegion iomem[2];
38 qemu_irq irq;
39 MUSBState *musb;
40 QEMUTimer *otg_timer;
41 QEMUTimer *pwr_timer;
42
43 int power;
44 uint32_t scratch;
45 uint16_t test_reset;
46 uint32_t prcm_config;
47 uint32_t prcm_mngmt;
48 uint16_t otg_status;
49 uint32_t dev_config;
50 int host_mode;
51 uint32_t intr;
52 uint32_t intr_ok;
53 uint32_t mask;
54 uint32_t usbip_intr;
55 uint32_t usbip_mask;
56 uint32_t gpio_intr;
57 uint32_t gpio_mask;
58 uint32_t gpio_config;
59 uint32_t dma_intr;
60 uint32_t dma_mask;
61 uint32_t dma_map;
62 uint32_t dma_config;
63 uint32_t ep0_config;
64 uint32_t rx_config[15];
65 uint32_t tx_config[15];
66 uint32_t wkup_mask;
67 uint32_t pullup[2];
68 uint32_t control_config;
69 uint32_t otg_timer_val;
70} TUSBState;
71
72#define TUSB_DEVCLOCK 60000000
73
74#define TUSB_VLYNQ_CTRL 0x004
75
76
77#define TUSB_BASE_OFFSET 0x400
78
79
80#define TUSB_FIFO_BASE 0x600
81
82
83#define TUSB_SYS_REG_BASE 0x800
84
85#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
86#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
87#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
88#define TUSB_DEV_CONF_SOFT_ID (1 << 1)
89#define TUSB_DEV_CONF_ID_SEL (1 << 0)
90
91#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
92#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
93#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
94#define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23)
95#define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
96#define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
97#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
98#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
99#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
100#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
101#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
102#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
103#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
104#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
105#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
106#define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
107#define TUSB_PHY_OTG_CTRL_PD (1 << 6)
108#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
109#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
110#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
111#define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
112#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
113#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
114
115
116#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
117#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
118#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
119#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
120#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
121#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
122#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
123#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
124#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
125#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
126#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
127
128#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
129#define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
130#define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
131#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
132
133
134#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
135#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
136#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
137
138
139#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
140#define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25)
141#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
142#define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
143#define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
144#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
145#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
146#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
147#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
148#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
149#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
150#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
151#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
152#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
153#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
154
155
156#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
157#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
158#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
159#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
160#define TUSB_PRCM_WGPIO_7 (1 << 12)
161#define TUSB_PRCM_WGPIO_6 (1 << 11)
162#define TUSB_PRCM_WGPIO_5 (1 << 10)
163#define TUSB_PRCM_WGPIO_4 (1 << 9)
164#define TUSB_PRCM_WGPIO_3 (1 << 8)
165#define TUSB_PRCM_WGPIO_2 (1 << 7)
166#define TUSB_PRCM_WGPIO_1 (1 << 6)
167#define TUSB_PRCM_WGPIO_0 (1 << 5)
168#define TUSB_PRCM_WHOSTDISCON (1 << 4)
169#define TUSB_PRCM_WBUS (1 << 3)
170#define TUSB_PRCM_WNORCS (1 << 2)
171#define TUSB_PRCM_WVBUS (1 << 1)
172#define TUSB_PRCM_WID (1 << 0)
173
174#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
175#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
176#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
177#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
178#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
179#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
180#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
181#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
182#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
183#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
184#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
185#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
186#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
187#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
188#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
189#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
190
191
192#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
193#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
194#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
195#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
196#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
197#define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
198#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
199#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
200#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
201#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
202#define TUSB_INT_SRC_DEV_READY (1 << 12)
203#define TUSB_INT_SRC_USB_IP_TX (1 << 9)
204#define TUSB_INT_SRC_USB_IP_RX (1 << 8)
205#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
206#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
207#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
208#define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
209#define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
210#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
211#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
212#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
213
214#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
215#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
216#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
217#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
218#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
219#define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c)
220#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
221#define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c)
222#define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188)
223#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
224#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
225#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
226
227#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
228#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
229
230
231#define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
232#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
233#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
234#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
235#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
236#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20)
237#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
238#define TUSB_EP0_CONFIG_SW_EN (1 << 8)
239#define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
240#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
241#define TUSB_EP_CONFIG_SW_EN (1 << 31)
242#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
243#define TUSB_PROD_TEST_RESET_VAL 0xa596
244
245static void tusb_intr_update(TUSBState *s)
246{
247 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
248 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
249 else
250 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
251}
252
253static void tusb_usbip_intr_update(TUSBState *s)
254{
255
256 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
257 s->intr |= TUSB_INT_SRC_USB_IP_TX;
258 else
259 s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
260
261
262 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
263 s->intr |= TUSB_INT_SRC_USB_IP_RX;
264 else
265 s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
266
267
268
269 tusb_intr_update(s);
270}
271
272static void tusb_dma_intr_update(TUSBState *s)
273{
274 if (s->dma_intr & ~s->dma_mask)
275 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
276 else
277 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
278
279 tusb_intr_update(s);
280}
281
282static void tusb_gpio_intr_update(TUSBState *s)
283{
284
285}
286
287static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
288{
289 TUSBState *s = (TUSBState *) opaque;
290
291 switch (addr & 0xfff) {
292 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
293 return musb_read[0](s->musb, addr & 0x1ff);
294
295 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
296 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
297 }
298
299 printf("%s: unknown register at %03x\n",
300 __func__, (int) (addr & 0xfff));
301 return 0;
302}
303
304static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
305{
306 TUSBState *s = (TUSBState *) opaque;
307
308 switch (addr & 0xfff) {
309 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
310 return musb_read[1](s->musb, addr & 0x1ff);
311
312 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
313 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
314 }
315
316 printf("%s: unknown register at %03x\n",
317 __func__, (int) (addr & 0xfff));
318 return 0;
319}
320
321static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
322{
323 TUSBState *s = (TUSBState *) opaque;
324 int offset = addr & 0xfff;
325 int epnum;
326 uint32_t ret;
327
328 switch (offset) {
329 case TUSB_DEV_CONF:
330 return s->dev_config;
331
332 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
333 return musb_read[2](s->musb, offset & 0x1ff);
334
335 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
336 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
337
338 case TUSB_PHY_OTG_CTRL_ENABLE:
339 case TUSB_PHY_OTG_CTRL:
340 return 0x00;
341
342 case TUSB_DEV_OTG_STAT:
343 ret = s->otg_status;
344#if 0
345 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
346 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
347#endif
348 return ret;
349 case TUSB_DEV_OTG_TIMER:
350 return s->otg_timer_val;
351
352 case TUSB_PRCM_REV:
353 return 0x20;
354 case TUSB_PRCM_CONF:
355 return s->prcm_config;
356 case TUSB_PRCM_MNGMT:
357 return s->prcm_mngmt;
358 case TUSB_PRCM_WAKEUP_SOURCE:
359 case TUSB_PRCM_WAKEUP_CLEAR:
360 return 0x00000000;
361 case TUSB_PRCM_WAKEUP_MASK:
362 return s->wkup_mask;
363
364 case TUSB_PULLUP_1_CTRL:
365 return s->pullup[0];
366 case TUSB_PULLUP_2_CTRL:
367 return s->pullup[1];
368
369 case TUSB_INT_CTRL_REV:
370 return 0x20;
371 case TUSB_INT_CTRL_CONF:
372 return s->control_config;
373
374 case TUSB_USBIP_INT_SRC:
375 case TUSB_USBIP_INT_SET:
376 case TUSB_USBIP_INT_CLEAR:
377 return s->usbip_intr;
378 case TUSB_USBIP_INT_MASK:
379 return s->usbip_mask;
380
381 case TUSB_DMA_INT_SRC:
382 case TUSB_DMA_INT_SET:
383 case TUSB_DMA_INT_CLEAR:
384 return s->dma_intr;
385 case TUSB_DMA_INT_MASK:
386 return s->dma_mask;
387
388 case TUSB_GPIO_INT_SRC:
389 case TUSB_GPIO_INT_SET:
390 case TUSB_GPIO_INT_CLEAR:
391 return s->gpio_intr;
392 case TUSB_GPIO_INT_MASK:
393 return s->gpio_mask;
394
395 case TUSB_INT_SRC:
396 case TUSB_INT_SRC_SET:
397 case TUSB_INT_SRC_CLEAR:
398 return s->intr;
399 case TUSB_INT_MASK:
400 return s->mask;
401
402 case TUSB_GPIO_REV:
403 return 0x30;
404 case TUSB_GPIO_CONF:
405 return s->gpio_config;
406
407 case TUSB_DMA_CTRL_REV:
408 return 0x30;
409 case TUSB_DMA_REQ_CONF:
410 return s->dma_config;
411 case TUSB_EP0_CONF:
412 return s->ep0_config;
413 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
414 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
415 return s->tx_config[epnum];
416 case TUSB_DMA_EP_MAP:
417 return s->dma_map;
418 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
419 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
420 return s->rx_config[epnum];
421 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
422 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
423 return 0x00000000;
424 case TUSB_WAIT_COUNT:
425 return 0x00;
426
427 case TUSB_SCRATCH_PAD:
428 return s->scratch;
429
430 case TUSB_PROD_TEST_RESET:
431 return s->test_reset;
432
433
434 case TUSB_DIDR1_LO:
435 return 0xa9453c59;
436 case TUSB_DIDR1_HI:
437 return 0x54059adf;
438 }
439
440 printf("%s: unknown register at %03x\n", __func__, offset);
441 return 0;
442}
443
444static void tusb_async_writeb(void *opaque, hwaddr addr,
445 uint32_t value)
446{
447 TUSBState *s = (TUSBState *) opaque;
448
449 switch (addr & 0xfff) {
450 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
451 musb_write[0](s->musb, addr & 0x1ff, value);
452 break;
453
454 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
455 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
456 break;
457
458 default:
459 printf("%s: unknown register at %03x\n",
460 __func__, (int) (addr & 0xfff));
461 return;
462 }
463}
464
465static void tusb_async_writeh(void *opaque, hwaddr addr,
466 uint32_t value)
467{
468 TUSBState *s = (TUSBState *) opaque;
469
470 switch (addr & 0xfff) {
471 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
472 musb_write[1](s->musb, addr & 0x1ff, value);
473 break;
474
475 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
476 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
477 break;
478
479 default:
480 printf("%s: unknown register at %03x\n",
481 __func__, (int) (addr & 0xfff));
482 return;
483 }
484}
485
486static void tusb_async_writew(void *opaque, hwaddr addr,
487 uint32_t value)
488{
489 TUSBState *s = (TUSBState *) opaque;
490 int offset = addr & 0xfff;
491 int epnum;
492
493 switch (offset) {
494 case TUSB_VLYNQ_CTRL:
495 break;
496
497 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
498 musb_write[2](s->musb, offset & 0x1ff, value);
499 break;
500
501 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
502 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
503 break;
504
505 case TUSB_DEV_CONF:
506 s->dev_config = value;
507 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
508 if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
509 hw_error("%s: Product Test mode not allowed\n", __func__);
510 break;
511
512 case TUSB_PHY_OTG_CTRL_ENABLE:
513 case TUSB_PHY_OTG_CTRL:
514 return;
515 case TUSB_DEV_OTG_TIMER:
516 s->otg_timer_val = value;
517 if (value & TUSB_DEV_OTG_TIMER_ENABLE)
518 timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
519 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
520 NANOSECONDS_PER_SECOND, TUSB_DEVCLOCK));
521 else
522 timer_del(s->otg_timer);
523 break;
524
525 case TUSB_PRCM_CONF:
526 s->prcm_config = value;
527 break;
528 case TUSB_PRCM_MNGMT:
529 s->prcm_mngmt = value;
530 break;
531 case TUSB_PRCM_WAKEUP_CLEAR:
532 break;
533 case TUSB_PRCM_WAKEUP_MASK:
534 s->wkup_mask = value;
535 break;
536
537 case TUSB_PULLUP_1_CTRL:
538 s->pullup[0] = value;
539 break;
540 case TUSB_PULLUP_2_CTRL:
541 s->pullup[1] = value;
542 break;
543 case TUSB_INT_CTRL_CONF:
544 s->control_config = value;
545 tusb_intr_update(s);
546 break;
547
548 case TUSB_USBIP_INT_SET:
549 s->usbip_intr |= value;
550 tusb_usbip_intr_update(s);
551 break;
552 case TUSB_USBIP_INT_CLEAR:
553 s->usbip_intr &= ~value;
554 tusb_usbip_intr_update(s);
555 musb_core_intr_clear(s->musb, ~value);
556 break;
557 case TUSB_USBIP_INT_MASK:
558 s->usbip_mask = value;
559 tusb_usbip_intr_update(s);
560 break;
561
562 case TUSB_DMA_INT_SET:
563 s->dma_intr |= value;
564 tusb_dma_intr_update(s);
565 break;
566 case TUSB_DMA_INT_CLEAR:
567 s->dma_intr &= ~value;
568 tusb_dma_intr_update(s);
569 break;
570 case TUSB_DMA_INT_MASK:
571 s->dma_mask = value;
572 tusb_dma_intr_update(s);
573 break;
574
575 case TUSB_GPIO_INT_SET:
576 s->gpio_intr |= value;
577 tusb_gpio_intr_update(s);
578 break;
579 case TUSB_GPIO_INT_CLEAR:
580 s->gpio_intr &= ~value;
581 tusb_gpio_intr_update(s);
582 break;
583 case TUSB_GPIO_INT_MASK:
584 s->gpio_mask = value;
585 tusb_gpio_intr_update(s);
586 break;
587
588 case TUSB_INT_SRC_SET:
589 s->intr |= value;
590 tusb_intr_update(s);
591 break;
592 case TUSB_INT_SRC_CLEAR:
593 s->intr &= ~value;
594 tusb_intr_update(s);
595 break;
596 case TUSB_INT_MASK:
597 s->mask = value;
598 tusb_intr_update(s);
599 break;
600
601 case TUSB_GPIO_CONF:
602 s->gpio_config = value;
603 break;
604 case TUSB_DMA_REQ_CONF:
605 s->dma_config = value;
606 break;
607 case TUSB_EP0_CONF:
608 s->ep0_config = value & 0x1ff;
609 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
610 value & TUSB_EP0_CONFIG_DIR_TX);
611 break;
612 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
613 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
614 s->tx_config[epnum] = value;
615 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
616 break;
617 case TUSB_DMA_EP_MAP:
618 s->dma_map = value;
619 break;
620 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
621 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
622 s->rx_config[epnum] = value;
623 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
624 break;
625 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
626 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
627 return;
628 case TUSB_WAIT_COUNT:
629 return;
630
631 case TUSB_SCRATCH_PAD:
632 s->scratch = value;
633 break;
634
635 case TUSB_PROD_TEST_RESET:
636 s->test_reset = value;
637 break;
638
639 default:
640 printf("%s: unknown register at %03x\n", __func__, offset);
641 return;
642 }
643}
644
645static uint64_t tusb_async_readfn(void *opaque, hwaddr addr, unsigned size)
646{
647 switch (size) {
648 case 1:
649 return tusb_async_readb(opaque, addr);
650 case 2:
651 return tusb_async_readh(opaque, addr);
652 case 4:
653 return tusb_async_readw(opaque, addr);
654 default:
655 g_assert_not_reached();
656 }
657}
658
659static void tusb_async_writefn(void *opaque, hwaddr addr,
660 uint64_t value, unsigned size)
661{
662 switch (size) {
663 case 1:
664 tusb_async_writeb(opaque, addr, value);
665 break;
666 case 2:
667 tusb_async_writeh(opaque, addr, value);
668 break;
669 case 4:
670 tusb_async_writew(opaque, addr, value);
671 break;
672 default:
673 g_assert_not_reached();
674 }
675}
676
677static const MemoryRegionOps tusb_async_ops = {
678 .read = tusb_async_readfn,
679 .write = tusb_async_writefn,
680 .valid.min_access_size = 1,
681 .valid.max_access_size = 4,
682 .endianness = DEVICE_NATIVE_ENDIAN,
683};
684
685static void tusb_otg_tick(void *opaque)
686{
687 TUSBState *s = (TUSBState *) opaque;
688
689 s->otg_timer_val = 0;
690 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
691 tusb_intr_update(s);
692}
693
694static void tusb_power_tick(void *opaque)
695{
696 TUSBState *s = (TUSBState *) opaque;
697
698 if (s->power) {
699 s->intr_ok = ~0;
700 tusb_intr_update(s);
701 }
702}
703
704static void tusb_musb_core_intr(void *opaque, int source, int level)
705{
706 TUSBState *s = (TUSBState *) opaque;
707 uint16_t otg_status = s->otg_status;
708
709 switch (source) {
710 case musb_set_vbus:
711 if (level)
712 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
713 else
714 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
715
716
717
718 if (s->otg_status != otg_status) {
719 s->otg_status = otg_status;
720 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
721 tusb_intr_update(s);
722 }
723 break;
724
725 case musb_set_session:
726
727
728 if (level) {
729 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
730 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
731 } else {
732 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
733 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
734 }
735
736
737 break;
738
739 case musb_irq_tx:
740 case musb_irq_rx:
741 s->usbip_intr = musb_core_intr_get(s->musb);
742
743 default:
744 if (level)
745 s->intr |= 1 << source;
746 else
747 s->intr &= ~(1 << source);
748 tusb_intr_update(s);
749 break;
750 }
751}
752
753static void tusb6010_power(TUSBState *s, int on)
754{
755 if (!on) {
756 s->power = 0;
757 } else if (!s->power && on) {
758 s->power = 1;
759
760 s->intr_ok = 0;
761 tusb_intr_update(s);
762 timer_mod(s->pwr_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
763 NANOSECONDS_PER_SECOND / 2);
764 }
765}
766
767static void tusb6010_irq(void *opaque, int source, int level)
768{
769 if (source) {
770 tusb_musb_core_intr(opaque, source - 1, level);
771 } else {
772 tusb6010_power(opaque, level);
773 }
774}
775
776static void tusb6010_reset(DeviceState *dev)
777{
778 TUSBState *s = TUSB(dev);
779 int i;
780
781 s->test_reset = TUSB_PROD_TEST_RESET_VAL;
782 s->host_mode = 0;
783 s->dev_config = 0;
784 s->otg_status = 0;
785 s->power = 0;
786 s->mask = 0xffffffff;
787 s->intr = 0x00000000;
788 s->otg_timer_val = 0;
789 s->scratch = 0;
790 s->prcm_config = 0;
791 s->prcm_mngmt = 0;
792 s->intr_ok = 0;
793 s->usbip_intr = 0;
794 s->usbip_mask = 0;
795 s->gpio_intr = 0;
796 s->gpio_mask = 0;
797 s->gpio_config = 0;
798 s->dma_intr = 0;
799 s->dma_mask = 0;
800 s->dma_map = 0;
801 s->dma_config = 0;
802 s->ep0_config = 0;
803 s->wkup_mask = 0;
804 s->pullup[0] = s->pullup[1] = 0;
805 s->control_config = 0;
806 for (i = 0; i < 15; i++) {
807 s->rx_config[i] = s->tx_config[i] = 0;
808 }
809 musb_reset(s->musb);
810}
811
812static void tusb6010_realize(DeviceState *dev, Error **errp)
813{
814 TUSBState *s = TUSB(dev);
815 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
816
817 s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
818 s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
819 memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
820 "tusb-async", UINT32_MAX);
821 sysbus_init_mmio(sbd, &s->iomem[0]);
822 sysbus_init_mmio(sbd, &s->iomem[1]);
823 sysbus_init_irq(sbd, &s->irq);
824 qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
825 s->musb = musb_init(dev, 1);
826}
827
828static void tusb6010_class_init(ObjectClass *klass, void *data)
829{
830 DeviceClass *dc = DEVICE_CLASS(klass);
831
832 dc->realize = tusb6010_realize;
833 dc->reset = tusb6010_reset;
834}
835
836static const TypeInfo tusb6010_info = {
837 .name = TYPE_TUSB6010,
838 .parent = TYPE_SYS_BUS_DEVICE,
839 .instance_size = sizeof(TUSBState),
840 .class_init = tusb6010_class_init,
841};
842
843static void tusb6010_register_types(void)
844{
845 type_register_static(&tusb6010_info);
846}
847
848type_init(tusb6010_register_types)
849
