LXR qemu/include/hw/i386/x86.h

   1/*
   2 * Copyright (c) 2019 Red Hat, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2 or later, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License along with
  14 * this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17#ifndef HW_I386_X86_H
  18#define HW_I386_X86_H
  19
  20#include "qemu-common.h"
  21#include "exec/hwaddr.h"
  22#include "qemu/notify.h"
  23
  24#include "hw/boards.h"
  25#include "hw/nmi.h"
  26
  27typedef struct {
  28    /*< private >*/
  29    MachineClass parent;
  30
  31    /*< public >*/
  32
  33    /* TSC rate migration: */
  34    bool save_tsc_khz;
  35    /* Enables contiguous-apic-ID mode */
  36    bool compat_apic_id_mode;
  37} X86MachineClass;
  38
  39typedef struct {
  40    /*< private >*/
  41    MachineState parent;
  42
  43    /*< public >*/
  44
  45    /* Pointers to devices and objects: */
  46    ISADevice *rtc;
  47    FWCfgState *fw_cfg;
  48    qemu_irq *gsi;
  49    GMappedFile *initrd_mapped_file;
  50
  51    /* Configuration options: */
  52    uint64_t max_ram_below_4g;
  53
  54    /* RAM information (sizes, addresses, configuration): */
  55    ram_addr_t below_4g_mem_size, above_4g_mem_size;
  56
  57    /* CPU and apic information: */
  58    bool apic_xrupt_override;
  59    unsigned apic_id_limit;
  60    uint16_t boot_cpus;
  61    unsigned smp_dies;
  62
  63    /*
  64     * Address space used by IOAPIC device. All IOAPIC interrupts
  65     * will be translated to MSI messages in the address space.
  66     */
  67    AddressSpace *ioapic_as;
  68} X86MachineState;
  69
  70#define X86_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  71
  72#define TYPE_X86_MACHINE   MACHINE_TYPE_NAME("x86")
  73#define X86_MACHINE(obj) \
  74    OBJECT_CHECK(X86MachineState, (obj), TYPE_X86_MACHINE)
  75#define X86_MACHINE_GET_CLASS(obj) \
  76    OBJECT_GET_CLASS(X86MachineClass, obj, TYPE_X86_MACHINE)
  77#define X86_MACHINE_CLASS(class) \
  78    OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
  79
  80uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
  81                                    unsigned int cpu_index);
  82
  83void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
  84void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
  85CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
  86                                             unsigned cpu_index);
  87int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
  88const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
  89
  90void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
  91
  92void x86_load_linux(X86MachineState *x86ms,
  93                    FWCfgState *fw_cfg,
  94                    int acpi_data_size,
  95                    bool pvh_enabled,
  96                    bool linuxboot_dma_enabled);
  97
  98#endif
  99