1#ifndef HW_PPC_H
2#define HW_PPC_H
3
4#include "target/ppc/cpu-qom.h"
5
6void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
7PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
8
9
10typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
11typedef struct clk_setup_t clk_setup_t;
12struct clk_setup_t {
13 clk_setup_cb cb;
14 void *opaque;
15};
16static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
17{
18 if (clk->cb != NULL)
19 (*clk->cb)(clk->opaque, freq);
20}
21
22struct ppc_tb_t {
23
24 int64_t tb_offset;
25 int64_t atb_offset;
26 uint32_t tb_freq;
27
28 uint64_t decr_next;
29 uint32_t decr_freq;
30 QEMUTimer *decr_timer;
31
32 uint64_t hdecr_next;
33 QEMUTimer *hdecr_timer;
34 uint64_t purr_load;
35 uint64_t purr_start;
36 void *opaque;
37 uint32_t flags;
38};
39
40
41#define PPC_TIMER_BOOKE (1 << 0)
42#define PPC_TIMER_E500 (1 << 1)
43#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2)
44
45
46
47#define PPC_DECR_ZERO_TRIGGERED (1 << 3)
48
49
50#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4)
51
52
53
54uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
55clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
56
57typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
58typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
59int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
60 int (*dcr_write_error)(int dcrn));
61int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
62 dcr_read_cb drc_read, dcr_write_cb dcr_write);
63clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
64 unsigned int decr_excp);
65
66
67void ppc40x_core_reset(PowerPCCPU *cpu);
68void ppc40x_chip_reset(PowerPCCPU *cpu);
69void ppc40x_system_reset(PowerPCCPU *cpu);
70void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
71
72#if defined(CONFIG_USER_ONLY)
73static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
74static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
75static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
76static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
77static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
78static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
79#else
80void ppc40x_irq_init(PowerPCCPU *cpu);
81void ppce500_irq_init(PowerPCCPU *cpu);
82void ppc6xx_irq_init(PowerPCCPU *cpu);
83void ppc970_irq_init(PowerPCCPU *cpu);
84void ppcPOWER7_irq_init(PowerPCCPU *cpu);
85void ppcPOWER9_irq_init(PowerPCCPU *cpu);
86#endif
87
88
89enum {
90 ARCH_PREP = 0,
91 ARCH_MAC99,
92 ARCH_HEATHROW,
93 ARCH_MAC99_U3,
94};
95
96#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
97#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
98#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
99#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
100#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
101#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
102#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
103#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
104#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
105#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
106#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
107#define FW_CFG_PPC_VIACONFIG (FW_CFG_ARCH_LOCAL + 0x0b)
108
109#define PPC_SERIAL_MM_BAUDBASE 399193
110
111
112void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
113#endif
114