LXR qemu/include/hw/ssi/aspeed

   1/*
   2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
   3 *
   4 * Copyright (C) 2016 IBM Corp.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef ASPEED_SMC_H
  26#define ASPEED_SMC_H
  27
  28#include "hw/ssi/ssi.h"
  29#include "hw/sysbus.h"
  30
  31typedef struct AspeedSegments {
  32    hwaddr addr;
  33    uint32_t size;
  34} AspeedSegments;
  35
  36struct AspeedSMCState;
  37typedef struct AspeedSMCController {
  38    const char *name;
  39    uint8_t r_conf;
  40    uint8_t r_ce_ctrl;
  41    uint8_t r_ctrl0;
  42    uint8_t r_timings;
  43    uint8_t conf_enable_w0;
  44    uint8_t max_slaves;
  45    const AspeedSegments *segments;
  46    hwaddr flash_window_base;
  47    uint32_t flash_window_size;
  48    bool has_dma;
  49    hwaddr dma_flash_mask;
  50    hwaddr dma_dram_mask;
  51    uint32_t nregs;
  52    uint32_t (*segment_to_reg)(const struct AspeedSMCState *s,
  53                               const AspeedSegments *seg);
  54    void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg,
  55                           AspeedSegments *seg);
  56} AspeedSMCController;
  57
  58typedef struct AspeedSMCFlash {
  59    struct AspeedSMCState *controller;
  60
  61    uint8_t id;
  62    uint32_t size;
  63
  64    MemoryRegion mmio;
  65    DeviceState *flash;
  66} AspeedSMCFlash;
  67
  68#define TYPE_ASPEED_SMC "aspeed.smc"
  69#define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC)
  70#define ASPEED_SMC_CLASS(klass) \
  71     OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC)
  72#define ASPEED_SMC_GET_CLASS(obj) \
  73     OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC)
  74
  75typedef struct  AspeedSMCClass {
  76    SysBusDevice parent_obj;
  77    const AspeedSMCController *ctrl;
  78}  AspeedSMCClass;
  79
  80#define ASPEED_SMC_R_MAX        (0x100 / 4)
  81
  82typedef struct AspeedSMCState {
  83    SysBusDevice parent_obj;
  84
  85    const AspeedSMCController *ctrl;
  86
  87    MemoryRegion mmio;
  88    MemoryRegion mmio_flash;
  89
  90    qemu_irq irq;
  91    int irqline;
  92
  93    uint32_t num_cs;
  94    qemu_irq *cs_lines;
  95    bool inject_failure;
  96
  97    SSIBus *spi;
  98
  99    uint32_t regs[ASPEED_SMC_R_MAX];
 100
 101    /* depends on the controller type */
 102    uint8_t r_conf;
 103    uint8_t r_ce_ctrl;
 104    uint8_t r_ctrl0;
 105    uint8_t r_timings;
 106    uint8_t conf_enable_w0;
 107
 108    /* for DMA support */
 109    uint64_t sdram_base;
 110
 111    AddressSpace flash_as;
 112    MemoryRegion *dram_mr;
 113    AddressSpace dram_as;
 114
 115    AspeedSMCFlash *flashes;
 116
 117    uint8_t snoop_index;
 118    uint8_t snoop_dummies;
 119} AspeedSMCState;
 120
 121#endif /* ASPEED_SMC_H */
 122