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19#include "qemu/osdep.h"
20#include "qemu/main-loop.h"
21#include "cpu.h"
22#include "exec/helper-proto.h"
23#include "exec/exec-all.h"
24#include "exec/cpu_ldst.h"
25#include "internal.h"
26#include "helper_regs.h"
27
28
29
30
31
32#ifdef DEBUG_EXCEPTIONS
33# define LOG_EXCP(...) qemu_log(__VA_ARGS__)
34#else
35# define LOG_EXCP(...) do { } while (0)
36#endif
37
38
39
40#if defined(CONFIG_USER_ONLY)
41void ppc_cpu_do_interrupt(CPUState *cs)
42{
43 PowerPCCPU *cpu = POWERPC_CPU(cs);
44 CPUPPCState *env = &cpu->env;
45
46 cs->exception_index = POWERPC_EXCP_NONE;
47 env->error_code = 0;
48}
49
50static void ppc_hw_interrupt(CPUPPCState *env)
51{
52 CPUState *cs = env_cpu(env);
53
54 cs->exception_index = POWERPC_EXCP_NONE;
55 env->error_code = 0;
56}
57#else
58static inline void dump_syscall(CPUPPCState *env)
59{
60 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
61 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
62 " nip=" TARGET_FMT_lx "\n",
63 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
64 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
65 ppc_dump_gpr(env, 6), env->nip);
66}
67
68static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
69 target_ulong *msr)
70{
71
72 env->resume_as_sreset = false;
73
74
75 *msr |= (0x1ull << (63 - 47));
76
77
78 if (excp == POWERPC_EXCP_MCHECK) {
79 return excp;
80 }
81 switch (excp) {
82 case POWERPC_EXCP_RESET:
83 *msr |= 0x4ull << (63 - 45);
84 break;
85 case POWERPC_EXCP_EXTERNAL:
86 *msr |= 0x8ull << (63 - 45);
87 break;
88 case POWERPC_EXCP_DECR:
89 *msr |= 0x6ull << (63 - 45);
90 break;
91 case POWERPC_EXCP_SDOOR:
92 *msr |= 0x5ull << (63 - 45);
93 break;
94 case POWERPC_EXCP_SDOOR_HV:
95 *msr |= 0x3ull << (63 - 45);
96 break;
97 case POWERPC_EXCP_HV_MAINT:
98 *msr |= 0xaull << (63 - 45);
99 break;
100 case POWERPC_EXCP_HVIRT:
101 *msr |= 0x9ull << (63 - 45);
102 break;
103 default:
104 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
105 excp);
106 }
107 return POWERPC_EXCP_RESET;
108}
109
110static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail)
111{
112 uint64_t offset = 0;
113
114 switch (ail) {
115 case AIL_0001_8000:
116 offset = 0x18000;
117 break;
118 case AIL_C000_0000_0000_4000:
119 offset = 0xc000000000004000ull;
120 break;
121 default:
122 cpu_abort(cs, "Invalid AIL combination %d\n", ail);
123 break;
124 }
125
126 return offset;
127}
128
129
130
131
132
133static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
134{
135 CPUState *cs = CPU(cpu);
136 CPUPPCState *env = &cpu->env;
137 target_ulong msr, new_msr, vector;
138 int srr0, srr1, asrr0, asrr1, lev, ail;
139 bool lpes0;
140
141 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
142 " => %08x (%02x)\n", env->nip, excp, env->error_code);
143
144
145 if (excp_model == POWERPC_EXCP_BOOKE) {
146 msr = env->msr;
147 } else {
148 msr = env->msr & ~0x783f0000ULL;
149 }
150
151
152
153
154
155 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
156
157
158 srr0 = SPR_SRR0;
159 srr1 = SPR_SRR1;
160 asrr0 = -1;
161 asrr1 = -1;
162
163
164
165
166
167 if (env->resume_as_sreset) {
168 excp = powerpc_reset_wakeup(cs, env, excp, &msr);
169 }
170
171
172
173
174
175
176
177
178
179
180
181
182
183#if defined(TARGET_PPC64)
184 if (excp_model == POWERPC_EXCP_POWER7 ||
185 excp_model == POWERPC_EXCP_POWER8 ||
186 excp_model == POWERPC_EXCP_POWER9) {
187 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
188 if (excp_model != POWERPC_EXCP_POWER7) {
189 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
190 } else {
191 ail = 0;
192 }
193 } else
194#endif
195 {
196 lpes0 = true;
197 ail = 0;
198 }
199
200
201
202
203
204
205 if (excp == POWERPC_EXCP_HV_EMU
206#if defined(TARGET_PPC64)
207 && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
208#endif
209
210 ) {
211 excp = POWERPC_EXCP_PROGRAM;
212 }
213
214 switch (excp) {
215 case POWERPC_EXCP_NONE:
216
217 return;
218 case POWERPC_EXCP_CRITICAL:
219 switch (excp_model) {
220 case POWERPC_EXCP_40x:
221 srr0 = SPR_40x_SRR2;
222 srr1 = SPR_40x_SRR3;
223 break;
224 case POWERPC_EXCP_BOOKE:
225 srr0 = SPR_BOOKE_CSRR0;
226 srr1 = SPR_BOOKE_CSRR1;
227 break;
228 case POWERPC_EXCP_G2:
229 break;
230 default:
231 goto excp_invalid;
232 }
233 break;
234 case POWERPC_EXCP_MCHECK:
235 if (msr_me == 0) {
236
237
238
239
240 fprintf(stderr, "Machine check while not allowed. "
241 "Entering checkstop state\n");
242 if (qemu_log_separate()) {
243 qemu_log("Machine check while not allowed. "
244 "Entering checkstop state\n");
245 }
246 cs->halted = 1;
247 cpu_interrupt_exittb(cs);
248 }
249 if (env->msr_mask & MSR_HVB) {
250
251
252
253
254 new_msr |= (target_ulong)MSR_HVB;
255 }
256 ail = 0;
257
258
259 new_msr &= ~((target_ulong)1 << MSR_ME);
260
261
262 switch (excp_model) {
263 case POWERPC_EXCP_40x:
264 srr0 = SPR_40x_SRR2;
265 srr1 = SPR_40x_SRR3;
266 break;
267 case POWERPC_EXCP_BOOKE:
268
269 srr0 = SPR_BOOKE_MCSRR0;
270 srr1 = SPR_BOOKE_MCSRR1;
271 asrr0 = SPR_BOOKE_CSRR0;
272 asrr1 = SPR_BOOKE_CSRR1;
273 break;
274 default:
275 break;
276 }
277 break;
278 case POWERPC_EXCP_DSI:
279 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
280 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
281 break;
282 case POWERPC_EXCP_ISI:
283 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
284 "\n", msr, env->nip);
285 msr |= env->error_code;
286 break;
287 case POWERPC_EXCP_EXTERNAL:
288 cs = CPU(cpu);
289
290 if (!lpes0) {
291 new_msr |= (target_ulong)MSR_HVB;
292 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
293 srr0 = SPR_HSRR0;
294 srr1 = SPR_HSRR1;
295 }
296 if (env->mpic_proxy) {
297
298 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
299 }
300 break;
301 case POWERPC_EXCP_ALIGN:
302
303
304
305
306
307
308 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
309 break;
310 case POWERPC_EXCP_PROGRAM:
311 switch (env->error_code & ~0xF) {
312 case POWERPC_EXCP_FP:
313 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
314 LOG_EXCP("Ignore floating point exception\n");
315 cs->exception_index = POWERPC_EXCP_NONE;
316 env->error_code = 0;
317 return;
318 }
319
320
321
322
323
324
325 msr |= 0x00100000;
326 env->spr[SPR_BOOKE_ESR] = ESR_FP;
327 break;
328 case POWERPC_EXCP_INVAL:
329 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
330 msr |= 0x00080000;
331 env->spr[SPR_BOOKE_ESR] = ESR_PIL;
332 break;
333 case POWERPC_EXCP_PRIV:
334 msr |= 0x00040000;
335 env->spr[SPR_BOOKE_ESR] = ESR_PPR;
336 break;
337 case POWERPC_EXCP_TRAP:
338 msr |= 0x00020000;
339 env->spr[SPR_BOOKE_ESR] = ESR_PTR;
340 break;
341 default:
342
343 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
344 env->error_code);
345 break;
346 }
347 break;
348 case POWERPC_EXCP_SYSCALL:
349 dump_syscall(env);
350 lev = env->error_code;
351
352
353
354
355
356 env->nip += 4;
357
358
359 if ((lev == 1) && cpu->vhyp) {
360 PPCVirtualHypervisorClass *vhc =
361 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
362 vhc->hypercall(cpu->vhyp, cpu);
363 return;
364 }
365 if (lev == 1) {
366 new_msr |= (target_ulong)MSR_HVB;
367 }
368 break;
369 case POWERPC_EXCP_FPU:
370 case POWERPC_EXCP_APU:
371 case POWERPC_EXCP_DECR:
372 break;
373 case POWERPC_EXCP_FIT:
374
375 LOG_EXCP("FIT exception\n");
376 break;
377 case POWERPC_EXCP_WDT:
378 LOG_EXCP("WDT exception\n");
379 switch (excp_model) {
380 case POWERPC_EXCP_BOOKE:
381 srr0 = SPR_BOOKE_CSRR0;
382 srr1 = SPR_BOOKE_CSRR1;
383 break;
384 default:
385 break;
386 }
387 break;
388 case POWERPC_EXCP_DTLB:
389 case POWERPC_EXCP_ITLB:
390 break;
391 case POWERPC_EXCP_DEBUG:
392 if (env->flags & POWERPC_FLAG_DE) {
393
394 srr0 = SPR_BOOKE_DSRR0;
395 srr1 = SPR_BOOKE_DSRR1;
396 asrr0 = SPR_BOOKE_CSRR0;
397 asrr1 = SPR_BOOKE_CSRR1;
398
399 } else {
400 cpu_abort(cs, "Debug exception triggered on unsupported model\n");
401 }
402 break;
403 case POWERPC_EXCP_SPEU:
404 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
405 break;
406 case POWERPC_EXCP_EFPDI:
407
408 cpu_abort(cs, "Embedded floating point data exception "
409 "is not implemented yet !\n");
410 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
411 break;
412 case POWERPC_EXCP_EFPRI:
413
414 cpu_abort(cs, "Embedded floating point round exception "
415 "is not implemented yet !\n");
416 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
417 break;
418 case POWERPC_EXCP_EPERFM:
419
420 cpu_abort(cs,
421 "Performance counter exception is not implemented yet !\n");
422 break;
423 case POWERPC_EXCP_DOORI:
424 break;
425 case POWERPC_EXCP_DOORCI:
426 srr0 = SPR_BOOKE_CSRR0;
427 srr1 = SPR_BOOKE_CSRR1;
428 break;
429 case POWERPC_EXCP_RESET:
430
431 if (msr_pow) {
432
433 msr |= 0x10000;
434 new_msr |= ((target_ulong)1 << MSR_ME);
435 }
436 if (env->msr_mask & MSR_HVB) {
437
438
439
440
441 new_msr |= (target_ulong)MSR_HVB;
442 } else {
443 if (msr_pow) {
444 cpu_abort(cs, "Trying to deliver power-saving system reset "
445 "exception %d with no HV support\n", excp);
446 }
447 }
448 ail = 0;
449 break;
450 case POWERPC_EXCP_DSEG:
451 case POWERPC_EXCP_ISEG:
452 case POWERPC_EXCP_TRACE:
453 break;
454 case POWERPC_EXCP_HDECR:
455 case POWERPC_EXCP_HDSI:
456 case POWERPC_EXCP_HISI:
457 case POWERPC_EXCP_HDSEG:
458 case POWERPC_EXCP_HISEG:
459 case POWERPC_EXCP_SDOOR_HV:
460 case POWERPC_EXCP_HV_EMU:
461 case POWERPC_EXCP_HVIRT:
462 srr0 = SPR_HSRR0;
463 srr1 = SPR_HSRR1;
464 new_msr |= (target_ulong)MSR_HVB;
465 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
466 break;
467 case POWERPC_EXCP_VPU:
468 case POWERPC_EXCP_VSXU:
469 case POWERPC_EXCP_FU:
470#ifdef TARGET_PPC64
471 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
472#endif
473 break;
474 case POWERPC_EXCP_PIT:
475 LOG_EXCP("PIT exception\n");
476 break;
477 case POWERPC_EXCP_IO:
478
479 cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
480 break;
481 case POWERPC_EXCP_RUNM:
482
483 cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
484 break;
485 case POWERPC_EXCP_EMUL:
486
487 cpu_abort(cs, "602 emulation trap exception "
488 "is not implemented yet !\n");
489 break;
490 case POWERPC_EXCP_IFTLB:
491 switch (excp_model) {
492 case POWERPC_EXCP_602:
493 case POWERPC_EXCP_603:
494 case POWERPC_EXCP_603E:
495 case POWERPC_EXCP_G2:
496 goto tlb_miss_tgpr;
497 case POWERPC_EXCP_7x5:
498 goto tlb_miss;
499 case POWERPC_EXCP_74xx:
500 goto tlb_miss_74xx;
501 default:
502 cpu_abort(cs, "Invalid instruction TLB miss exception\n");
503 break;
504 }
505 break;
506 case POWERPC_EXCP_DLTLB:
507 switch (excp_model) {
508 case POWERPC_EXCP_602:
509 case POWERPC_EXCP_603:
510 case POWERPC_EXCP_603E:
511 case POWERPC_EXCP_G2:
512 goto tlb_miss_tgpr;
513 case POWERPC_EXCP_7x5:
514 goto tlb_miss;
515 case POWERPC_EXCP_74xx:
516 goto tlb_miss_74xx;
517 default:
518 cpu_abort(cs, "Invalid data load TLB miss exception\n");
519 break;
520 }
521 break;
522 case POWERPC_EXCP_DSTLB:
523 switch (excp_model) {
524 case POWERPC_EXCP_602:
525 case POWERPC_EXCP_603:
526 case POWERPC_EXCP_603E:
527 case POWERPC_EXCP_G2:
528 tlb_miss_tgpr:
529
530 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
531 new_msr |= (target_ulong)1 << MSR_TGPR;
532 hreg_swap_gpr_tgpr(env);
533 }
534 goto tlb_miss;
535 case POWERPC_EXCP_7x5:
536 tlb_miss:
537#if defined(DEBUG_SOFTWARE_TLB)
538 if (qemu_log_enabled()) {
539 const char *es;
540 target_ulong *miss, *cmp;
541 int en;
542
543 if (excp == POWERPC_EXCP_IFTLB) {
544 es = "I";
545 en = 'I';
546 miss = &env->spr[SPR_IMISS];
547 cmp = &env->spr[SPR_ICMP];
548 } else {
549 if (excp == POWERPC_EXCP_DLTLB) {
550 es = "DL";
551 } else {
552 es = "DS";
553 }
554 en = 'D';
555 miss = &env->spr[SPR_DMISS];
556 cmp = &env->spr[SPR_DCMP];
557 }
558 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
559 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
560 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
561 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
562 env->error_code);
563 }
564#endif
565 msr |= env->crf[0] << 28;
566 msr |= env->error_code;
567
568 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
569 break;
570 case POWERPC_EXCP_74xx:
571 tlb_miss_74xx:
572#if defined(DEBUG_SOFTWARE_TLB)
573 if (qemu_log_enabled()) {
574 const char *es;
575 target_ulong *miss, *cmp;
576 int en;
577
578 if (excp == POWERPC_EXCP_IFTLB) {
579 es = "I";
580 en = 'I';
581 miss = &env->spr[SPR_TLBMISS];
582 cmp = &env->spr[SPR_PTEHI];
583 } else {
584 if (excp == POWERPC_EXCP_DLTLB) {
585 es = "DL";
586 } else {
587 es = "DS";
588 }
589 en = 'D';
590 miss = &env->spr[SPR_TLBMISS];
591 cmp = &env->spr[SPR_PTEHI];
592 }
593 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
594 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
595 env->error_code);
596 }
597#endif
598 msr |= env->error_code;
599 break;
600 default:
601 cpu_abort(cs, "Invalid data store TLB miss exception\n");
602 break;
603 }
604 break;
605 case POWERPC_EXCP_FPA:
606
607 cpu_abort(cs, "Floating point assist exception "
608 "is not implemented yet !\n");
609 break;
610 case POWERPC_EXCP_DABR:
611
612 cpu_abort(cs, "DABR exception is not implemented yet !\n");
613 break;
614 case POWERPC_EXCP_IABR:
615
616 cpu_abort(cs, "IABR exception is not implemented yet !\n");
617 break;
618 case POWERPC_EXCP_SMI:
619
620 cpu_abort(cs, "SMI exception is not implemented yet !\n");
621 break;
622 case POWERPC_EXCP_THERM:
623
624 cpu_abort(cs, "Thermal management exception "
625 "is not implemented yet !\n");
626 break;
627 case POWERPC_EXCP_PERFM:
628
629 cpu_abort(cs,
630 "Performance counter exception is not implemented yet !\n");
631 break;
632 case POWERPC_EXCP_VPUA:
633
634 cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
635 break;
636 case POWERPC_EXCP_SOFTP:
637
638 cpu_abort(cs,
639 "970 soft-patch exception is not implemented yet !\n");
640 break;
641 case POWERPC_EXCP_MAINT:
642
643 cpu_abort(cs,
644 "970 maintenance exception is not implemented yet !\n");
645 break;
646 case POWERPC_EXCP_MEXTBR:
647
648 cpu_abort(cs, "Maskable external exception "
649 "is not implemented yet !\n");
650 break;
651 case POWERPC_EXCP_NMEXTBR:
652
653 cpu_abort(cs, "Non maskable external exception "
654 "is not implemented yet !\n");
655 break;
656 default:
657 excp_invalid:
658 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
659 break;
660 }
661
662
663 env->spr[srr0] = env->nip;
664
665
666 env->spr[srr1] = msr;
667
668
669 if (!(env->msr_mask & MSR_HVB)) {
670 if (new_msr & MSR_HVB) {
671 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
672 "no HV support\n", excp);
673 }
674 if (srr0 == SPR_HSRR0) {
675 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
676 "no HV support\n", excp);
677 }
678 }
679
680
681 if (asrr0 != -1) {
682 env->spr[asrr0] = env->spr[srr0];
683 }
684 if (asrr1 != -1) {
685 env->spr[asrr1] = env->spr[srr1];
686 }
687
688
689
690
691
692#ifdef TARGET_PPC64
693 if (excp_model == POWERPC_EXCP_POWER7) {
694 if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
695 new_msr |= (target_ulong)1 << MSR_LE;
696 }
697 } else if (excp_model == POWERPC_EXCP_POWER8) {
698 if (new_msr & MSR_HVB) {
699 if (env->spr[SPR_HID0] & HID0_HILE) {
700 new_msr |= (target_ulong)1 << MSR_LE;
701 }
702 } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
703 new_msr |= (target_ulong)1 << MSR_LE;
704 }
705 } else if (excp_model == POWERPC_EXCP_POWER9) {
706 if (new_msr & MSR_HVB) {
707 if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
708 new_msr |= (target_ulong)1 << MSR_LE;
709 }
710 } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
711 new_msr |= (target_ulong)1 << MSR_LE;
712 }
713 } else if (msr_ile) {
714 new_msr |= (target_ulong)1 << MSR_LE;
715 }
716#else
717 if (msr_ile) {
718 new_msr |= (target_ulong)1 << MSR_LE;
719 }
720#endif
721
722
723 vector = env->excp_vectors[excp];
724 if (vector == (target_ulong)-1ULL) {
725 cpu_abort(cs, "Raised an exception without defined vector %d\n",
726 excp);
727 }
728 vector |= env->excp_prefix;
729
730
731
732
733
734 if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
735 ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
736 ail = 0;
737 }
738
739 if (ail) {
740 new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
741 vector |= ppc_excp_vector_offset(cs, ail);
742 }
743
744#if defined(TARGET_PPC64)
745 if (excp_model == POWERPC_EXCP_BOOKE) {
746 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
747
748 new_msr |= (target_ulong)1 << MSR_CM;
749 } else {
750 vector = (uint32_t)vector;
751 }
752 } else {
753 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
754 vector = (uint32_t)vector;
755 } else {
756 new_msr |= (target_ulong)1 << MSR_SF;
757 }
758 }
759#endif
760
761
762
763
764
765
766
767
768 env->msr = new_msr & env->msr_mask;
769 hreg_compute_hflags(env);
770 env->nip = vector;
771
772 cs->exception_index = POWERPC_EXCP_NONE;
773 env->error_code = 0;
774
775
776 env->reserve_addr = -1;
777
778
779
780
781
782 check_tlb_flush(env, false);
783}
784
785void ppc_cpu_do_interrupt(CPUState *cs)
786{
787 PowerPCCPU *cpu = POWERPC_CPU(cs);
788 CPUPPCState *env = &cpu->env;
789
790 powerpc_excp(cpu, env->excp_model, cs->exception_index);
791}
792
793static void ppc_hw_interrupt(CPUPPCState *env)
794{
795 PowerPCCPU *cpu = env_archcpu(env);
796 bool async_deliver;
797
798
799 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
800 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
801 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
802 return;
803 }
804
805 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
806 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
807 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
808 return;
809 }
810#if 0
811
812 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
813 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
814 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
815 return;
816 }
817#endif
818
819
820
821
822
823
824
825 async_deliver = (msr_ee != 0) || env->resume_as_sreset;
826
827
828 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
829
830 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
831 if ((async_deliver || msr_hv == 0) && hdice) {
832
833 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
834 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
835 return;
836 }
837 }
838
839
840 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
841
842 bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
843 if ((async_deliver || msr_hv == 0) && hvice) {
844 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HVIRT);
845 return;
846 }
847 }
848
849
850 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
851 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
852 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
853
854 if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
855 (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
856 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
857 return;
858 }
859 }
860 if (msr_ce != 0) {
861
862 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
863 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
864 return;
865 }
866 }
867 if (async_deliver != 0) {
868
869 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
870 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
871 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
872 return;
873 }
874 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
875 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
876 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
877 return;
878 }
879
880 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
881 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
882 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
883 return;
884 }
885
886 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
887 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
888 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
889 return;
890 }
891
892 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
893 if (ppc_decr_clear_on_delivery(env)) {
894 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
895 }
896 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
897 return;
898 }
899 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
900 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
901 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
902 return;
903 }
904 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) {
905 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
906 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV);
907 return;
908 }
909 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
910 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
911 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
912 return;
913 }
914
915 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
916 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
917 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
918 return;
919 }
920 }
921
922 if (env->resume_as_sreset) {
923
924
925
926
927
928
929
930
931
932
933
934 cpu_abort(env_cpu(env),
935 "Wakeup from PM state but interrupt Undelivered");
936 }
937}
938
939void ppc_cpu_do_system_reset(CPUState *cs)
940{
941 PowerPCCPU *cpu = POWERPC_CPU(cs);
942 CPUPPCState *env = &cpu->env;
943
944 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
945}
946#endif
947
948bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
949{
950 PowerPCCPU *cpu = POWERPC_CPU(cs);
951 CPUPPCState *env = &cpu->env;
952
953 if (interrupt_request & CPU_INTERRUPT_HARD) {
954 ppc_hw_interrupt(env);
955 if (env->pending_interrupts == 0) {
956 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
957 }
958 return true;
959 }
960 return false;
961}
962
963#if defined(DEBUG_OP)
964static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
965{
966 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
967 TARGET_FMT_lx "\n", RA, msr);
968}
969#endif
970
971
972
973
974void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
975 uint32_t error_code, uintptr_t raddr)
976{
977 CPUState *cs = env_cpu(env);
978
979 cs->exception_index = exception;
980 env->error_code = error_code;
981 cpu_loop_exit_restore(cs, raddr);
982}
983
984void raise_exception_err(CPUPPCState *env, uint32_t exception,
985 uint32_t error_code)
986{
987 raise_exception_err_ra(env, exception, error_code, 0);
988}
989
990void raise_exception(CPUPPCState *env, uint32_t exception)
991{
992 raise_exception_err_ra(env, exception, 0, 0);
993}
994
995void raise_exception_ra(CPUPPCState *env, uint32_t exception,
996 uintptr_t raddr)
997{
998 raise_exception_err_ra(env, exception, 0, raddr);
999}
1000
1001void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
1002 uint32_t error_code)
1003{
1004 raise_exception_err_ra(env, exception, error_code, 0);
1005}
1006
1007void helper_raise_exception(CPUPPCState *env, uint32_t exception)
1008{
1009 raise_exception_err_ra(env, exception, 0, 0);
1010}
1011
1012#if !defined(CONFIG_USER_ONLY)
1013void helper_store_msr(CPUPPCState *env, target_ulong val)
1014{
1015 uint32_t excp = hreg_store_msr(env, val, 0);
1016
1017 if (excp != 0) {
1018 CPUState *cs = env_cpu(env);
1019 cpu_interrupt_exittb(cs);
1020 raise_exception(env, excp);
1021 }
1022}
1023
1024#if defined(TARGET_PPC64)
1025void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
1026{
1027 CPUState *cs;
1028
1029 cs = env_cpu(env);
1030 cs->halted = 1;
1031
1032
1033
1034
1035
1036 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
1037
1038
1039 env->resume_as_sreset = (insn != PPC_PM_STOP) ||
1040 (env->spr[SPR_PSSCR] & PSSCR_EC);
1041}
1042#endif
1043
1044static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
1045{
1046 CPUState *cs = env_cpu(env);
1047
1048
1049 msr &= ~(1ULL << MSR_POW);
1050
1051#if defined(TARGET_PPC64)
1052
1053 if (!msr_is_64bit(env, msr)) {
1054 nip = (uint32_t)nip;
1055 }
1056#else
1057 nip = (uint32_t)nip;
1058#endif
1059
1060 env->nip = nip & ~((target_ulong)0x00000003);
1061 hreg_store_msr(env, msr, 1);
1062#if defined(DEBUG_OP)
1063 cpu_dump_rfi(env->nip, env->msr);
1064#endif
1065
1066
1067
1068
1069 cpu_interrupt_exittb(cs);
1070
1071 env->reserve_addr = -1;
1072
1073
1074 check_tlb_flush(env, false);
1075}
1076
1077void helper_rfi(CPUPPCState *env)
1078{
1079 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
1080}
1081
1082#define MSR_BOOK3S_MASK
1083#if defined(TARGET_PPC64)
1084void helper_rfid(CPUPPCState *env)
1085{
1086
1087
1088
1089
1090
1091
1092 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
1093}
1094
1095void helper_hrfid(CPUPPCState *env)
1096{
1097 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
1098}
1099#endif
1100
1101
1102
1103void helper_40x_rfci(CPUPPCState *env)
1104{
1105 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1106}
1107
1108void helper_rfci(CPUPPCState *env)
1109{
1110 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1111}
1112
1113void helper_rfdi(CPUPPCState *env)
1114{
1115
1116 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1117}
1118
1119void helper_rfmci(CPUPPCState *env)
1120{
1121
1122 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1123}
1124#endif
1125
1126void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1127 uint32_t flags)
1128{
1129 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1130 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1131 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1132 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1133 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1134 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1135 POWERPC_EXCP_TRAP, GETPC());
1136 }
1137}
1138
1139#if defined(TARGET_PPC64)
1140void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1141 uint32_t flags)
1142{
1143 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1144 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1145 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1146 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1147 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1148 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1149 POWERPC_EXCP_TRAP, GETPC());
1150 }
1151}
1152#endif
1153
1154#if !defined(CONFIG_USER_ONLY)
1155
1156
1157
1158void helper_rfsvc(CPUPPCState *env)
1159{
1160 do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1161}
1162
1163
1164static int dbell2irq(target_ulong rb)
1165{
1166 int msg = rb & DBELL_TYPE_MASK;
1167 int irq = -1;
1168
1169 switch (msg) {
1170 case DBELL_TYPE_DBELL:
1171 irq = PPC_INTERRUPT_DOORBELL;
1172 break;
1173 case DBELL_TYPE_DBELL_CRIT:
1174 irq = PPC_INTERRUPT_CDOORBELL;
1175 break;
1176 case DBELL_TYPE_G_DBELL:
1177 case DBELL_TYPE_G_DBELL_CRIT:
1178 case DBELL_TYPE_G_DBELL_MC:
1179
1180 default:
1181 break;
1182 }
1183
1184 return irq;
1185}
1186
1187void helper_msgclr(CPUPPCState *env, target_ulong rb)
1188{
1189 int irq = dbell2irq(rb);
1190
1191 if (irq < 0) {
1192 return;
1193 }
1194
1195 env->pending_interrupts &= ~(1 << irq);
1196}
1197
1198void helper_msgsnd(target_ulong rb)
1199{
1200 int irq = dbell2irq(rb);
1201 int pir = rb & DBELL_PIRTAG_MASK;
1202 CPUState *cs;
1203
1204 if (irq < 0) {
1205 return;
1206 }
1207
1208 qemu_mutex_lock_iothread();
1209 CPU_FOREACH(cs) {
1210 PowerPCCPU *cpu = POWERPC_CPU(cs);
1211 CPUPPCState *cenv = &cpu->env;
1212
1213 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1214 cenv->pending_interrupts |= 1 << irq;
1215 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1216 }
1217 }
1218 qemu_mutex_unlock_iothread();
1219}
1220
1221
1222static int book3s_dbell2irq(target_ulong rb)
1223{
1224 int msg = rb & DBELL_TYPE_MASK;
1225
1226
1227
1228
1229
1230
1231 return msg == DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : -1;
1232}
1233
1234void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
1235{
1236 int irq = book3s_dbell2irq(rb);
1237
1238 if (irq < 0) {
1239 return;
1240 }
1241
1242 env->pending_interrupts &= ~(1 << irq);
1243}
1244
1245void helper_book3s_msgsnd(target_ulong rb)
1246{
1247 int irq = book3s_dbell2irq(rb);
1248 int pir = rb & DBELL_PROCIDTAG_MASK;
1249 CPUState *cs;
1250
1251 if (irq < 0) {
1252 return;
1253 }
1254
1255 qemu_mutex_lock_iothread();
1256 CPU_FOREACH(cs) {
1257 PowerPCCPU *cpu = POWERPC_CPU(cs);
1258 CPUPPCState *cenv = &cpu->env;
1259
1260
1261 if (cenv->spr_cb[SPR_PIR].default_value == pir) {
1262 cenv->pending_interrupts |= 1 << irq;
1263 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1264 }
1265 }
1266 qemu_mutex_unlock_iothread();
1267}
1268#endif
1269
1270void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
1271 MMUAccessType access_type,
1272 int mmu_idx, uintptr_t retaddr)
1273{
1274 CPUPPCState *env = cs->env_ptr;
1275 uint32_t insn;
1276
1277
1278 cpu_restore_state(cs, retaddr, true);
1279 insn = cpu_ldl_code(env, env->nip);
1280
1281 cs->exception_index = POWERPC_EXCP_ALIGN;
1282 env->error_code = insn & 0x03FF0000;
1283 cpu_loop_exit(cs);
1284}
1285