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20#include "qemu/osdep.h"
21#include "qemu/qemu-print.h"
22#include "qemu/ctype.h"
23#include "qemu/log.h"
24#include "cpu.h"
25#include "exec/exec-all.h"
26#include "qapi/error.h"
27#include "qemu/error-report.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30#include "fpu/softfloat-helpers.h"
31
32
33
34static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
35
36const char * const riscv_int_regnames[] = {
37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
41 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
42};
43
44const char * const riscv_fpr_regnames[] = {
45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
50 "f30/ft10", "f31/ft11"
51};
52
53const char * const riscv_excp_names[] = {
54 "misaligned_fetch",
55 "fault_fetch",
56 "illegal_instruction",
57 "breakpoint",
58 "misaligned_load",
59 "fault_load",
60 "misaligned_store",
61 "fault_store",
62 "user_ecall",
63 "supervisor_ecall",
64 "hypervisor_ecall",
65 "machine_ecall",
66 "exec_page_fault",
67 "load_page_fault",
68 "reserved",
69 "store_page_fault"
70};
71
72const char * const riscv_intr_names[] = {
73 "u_software",
74 "s_software",
75 "h_software",
76 "m_software",
77 "u_timer",
78 "s_timer",
79 "h_timer",
80 "m_timer",
81 "u_external",
82 "s_external",
83 "h_external",
84 "m_external",
85 "reserved",
86 "reserved",
87 "reserved",
88 "reserved"
89};
90
91static void set_misa(CPURISCVState *env, target_ulong misa)
92{
93 env->misa_mask = env->misa = misa;
94}
95
96static void set_priv_version(CPURISCVState *env, int priv_ver)
97{
98 env->priv_ver = priv_ver;
99}
100
101static void set_feature(CPURISCVState *env, int feature)
102{
103 env->features |= (1ULL << feature);
104}
105
106static void set_resetvec(CPURISCVState *env, int resetvec)
107{
108#ifndef CONFIG_USER_ONLY
109 env->resetvec = resetvec;
110#endif
111}
112
113static void riscv_any_cpu_init(Object *obj)
114{
115 CPURISCVState *env = &RISCV_CPU(obj)->env;
116 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
117 set_priv_version(env, PRIV_VERSION_1_11_0);
118 set_resetvec(env, DEFAULT_RSTVEC);
119}
120
121#if defined(TARGET_RISCV32)
122
123static void riscv_base32_cpu_init(Object *obj)
124{
125 CPURISCVState *env = &RISCV_CPU(obj)->env;
126
127 set_misa(env, 0);
128}
129
130static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
131{
132 CPURISCVState *env = &RISCV_CPU(obj)->env;
133 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
134 set_priv_version(env, PRIV_VERSION_1_09_1);
135 set_resetvec(env, DEFAULT_RSTVEC);
136 set_feature(env, RISCV_FEATURE_MMU);
137 set_feature(env, RISCV_FEATURE_PMP);
138}
139
140static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
141{
142 CPURISCVState *env = &RISCV_CPU(obj)->env;
143 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
144 set_priv_version(env, PRIV_VERSION_1_10_0);
145 set_resetvec(env, DEFAULT_RSTVEC);
146 set_feature(env, RISCV_FEATURE_MMU);
147 set_feature(env, RISCV_FEATURE_PMP);
148}
149
150static void rv32imacu_nommu_cpu_init(Object *obj)
151{
152 CPURISCVState *env = &RISCV_CPU(obj)->env;
153 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
154 set_priv_version(env, PRIV_VERSION_1_10_0);
155 set_resetvec(env, DEFAULT_RSTVEC);
156 set_feature(env, RISCV_FEATURE_PMP);
157}
158
159#elif defined(TARGET_RISCV64)
160
161static void riscv_base64_cpu_init(Object *obj)
162{
163 CPURISCVState *env = &RISCV_CPU(obj)->env;
164
165 set_misa(env, 0);
166}
167
168static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
169{
170 CPURISCVState *env = &RISCV_CPU(obj)->env;
171 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
172 set_priv_version(env, PRIV_VERSION_1_09_1);
173 set_resetvec(env, DEFAULT_RSTVEC);
174 set_feature(env, RISCV_FEATURE_MMU);
175 set_feature(env, RISCV_FEATURE_PMP);
176}
177
178static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
179{
180 CPURISCVState *env = &RISCV_CPU(obj)->env;
181 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
182 set_priv_version(env, PRIV_VERSION_1_10_0);
183 set_resetvec(env, DEFAULT_RSTVEC);
184 set_feature(env, RISCV_FEATURE_MMU);
185 set_feature(env, RISCV_FEATURE_PMP);
186}
187
188static void rv64imacu_nommu_cpu_init(Object *obj)
189{
190 CPURISCVState *env = &RISCV_CPU(obj)->env;
191 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
192 set_priv_version(env, PRIV_VERSION_1_10_0);
193 set_resetvec(env, DEFAULT_RSTVEC);
194 set_feature(env, RISCV_FEATURE_PMP);
195}
196
197#endif
198
199static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
200{
201 ObjectClass *oc;
202 char *typename;
203 char **cpuname;
204
205 cpuname = g_strsplit(cpu_model, ",", 1);
206 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
207 oc = object_class_by_name(typename);
208 g_strfreev(cpuname);
209 g_free(typename);
210 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
211 object_class_is_abstract(oc)) {
212 return NULL;
213 }
214 return oc;
215}
216
217static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
218{
219 RISCVCPU *cpu = RISCV_CPU(cs);
220 CPURISCVState *env = &cpu->env;
221 int i;
222
223 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
224#ifndef CONFIG_USER_ONLY
225 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
227 qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip);
228 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
229 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
230 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
231 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
232 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
233 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
234#endif
235
236 for (i = 0; i < 32; i++) {
237 qemu_fprintf(f, " %s " TARGET_FMT_lx,
238 riscv_int_regnames[i], env->gpr[i]);
239 if ((i & 3) == 3) {
240 qemu_fprintf(f, "\n");
241 }
242 }
243 if (flags & CPU_DUMP_FPU) {
244 for (i = 0; i < 32; i++) {
245 qemu_fprintf(f, " %s %016" PRIx64,
246 riscv_fpr_regnames[i], env->fpr[i]);
247 if ((i & 3) == 3) {
248 qemu_fprintf(f, "\n");
249 }
250 }
251 }
252}
253
254static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
255{
256 RISCVCPU *cpu = RISCV_CPU(cs);
257 CPURISCVState *env = &cpu->env;
258 env->pc = value;
259}
260
261static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
262{
263 RISCVCPU *cpu = RISCV_CPU(cs);
264 CPURISCVState *env = &cpu->env;
265 env->pc = tb->pc;
266}
267
268static bool riscv_cpu_has_work(CPUState *cs)
269{
270#ifndef CONFIG_USER_ONLY
271 RISCVCPU *cpu = RISCV_CPU(cs);
272 CPURISCVState *env = &cpu->env;
273
274
275
276
277 return (env->mip & env->mie) != 0;
278#else
279 return true;
280#endif
281}
282
283void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
284 target_ulong *data)
285{
286 env->pc = data[0];
287}
288
289static void riscv_cpu_reset(CPUState *cs)
290{
291 RISCVCPU *cpu = RISCV_CPU(cs);
292 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
293 CPURISCVState *env = &cpu->env;
294
295 mcc->parent_reset(cs);
296#ifndef CONFIG_USER_ONLY
297 env->priv = PRV_M;
298 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
299 env->mcause = 0;
300 env->pc = env->resetvec;
301#endif
302 cs->exception_index = EXCP_NONE;
303 env->load_res = -1;
304 set_default_nan_mode(1, &env->fp_status);
305}
306
307static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
308{
309#if defined(TARGET_RISCV32)
310 info->print_insn = print_insn_riscv32;
311#elif defined(TARGET_RISCV64)
312 info->print_insn = print_insn_riscv64;
313#endif
314}
315
316static void riscv_cpu_realize(DeviceState *dev, Error **errp)
317{
318 CPUState *cs = CPU(dev);
319 RISCVCPU *cpu = RISCV_CPU(dev);
320 CPURISCVState *env = &cpu->env;
321 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
322 int priv_version = PRIV_VERSION_1_11_0;
323 target_ulong target_misa = 0;
324 Error *local_err = NULL;
325
326 cpu_exec_realizefn(cs, &local_err);
327 if (local_err != NULL) {
328 error_propagate(errp, local_err);
329 return;
330 }
331
332 if (cpu->cfg.priv_spec) {
333 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
334 priv_version = PRIV_VERSION_1_11_0;
335 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
336 priv_version = PRIV_VERSION_1_10_0;
337 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
338 priv_version = PRIV_VERSION_1_09_1;
339 } else {
340 error_setg(errp,
341 "Unsupported privilege spec version '%s'",
342 cpu->cfg.priv_spec);
343 return;
344 }
345 }
346
347 set_priv_version(env, priv_version);
348 set_resetvec(env, DEFAULT_RSTVEC);
349
350 if (cpu->cfg.mmu) {
351 set_feature(env, RISCV_FEATURE_MMU);
352 }
353
354 if (cpu->cfg.pmp) {
355 set_feature(env, RISCV_FEATURE_PMP);
356 }
357
358
359 if (!env->misa) {
360
361 if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
362 error_setg(errp,
363 "I and E extensions are incompatible");
364 return;
365 }
366
367 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
368 error_setg(errp,
369 "Either I or E extension must be set");
370 return;
371 }
372
373 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
374 cpu->cfg.ext_a & cpu->cfg.ext_f &
375 cpu->cfg.ext_d)) {
376 warn_report("Setting G will also set IMAFD");
377 cpu->cfg.ext_i = true;
378 cpu->cfg.ext_m = true;
379 cpu->cfg.ext_a = true;
380 cpu->cfg.ext_f = true;
381 cpu->cfg.ext_d = true;
382 }
383
384
385 if (cpu->cfg.ext_i) {
386 target_misa |= RVI;
387 }
388 if (cpu->cfg.ext_e) {
389 target_misa |= RVE;
390 }
391 if (cpu->cfg.ext_m) {
392 target_misa |= RVM;
393 }
394 if (cpu->cfg.ext_a) {
395 target_misa |= RVA;
396 }
397 if (cpu->cfg.ext_f) {
398 target_misa |= RVF;
399 }
400 if (cpu->cfg.ext_d) {
401 target_misa |= RVD;
402 }
403 if (cpu->cfg.ext_c) {
404 target_misa |= RVC;
405 }
406 if (cpu->cfg.ext_s) {
407 target_misa |= RVS;
408 }
409 if (cpu->cfg.ext_u) {
410 target_misa |= RVU;
411 }
412
413 set_misa(env, RVXLEN | target_misa);
414 }
415
416 riscv_cpu_register_gdb_regs_for_features(cs);
417
418 qemu_init_vcpu(cs);
419 cpu_reset(cs);
420
421 mcc->parent_realize(dev, errp);
422}
423
424static void riscv_cpu_init(Object *obj)
425{
426 RISCVCPU *cpu = RISCV_CPU(obj);
427
428 cpu_set_cpustate_pointers(cpu);
429}
430
431static const VMStateDescription vmstate_riscv_cpu = {
432 .name = "cpu",
433 .unmigratable = 1,
434};
435
436static Property riscv_cpu_properties[] = {
437 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
438 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
439 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
440 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
441 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
442 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
443 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
444 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
445 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
446 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
447 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
448 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
449 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
450 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
451 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
452 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
453 DEFINE_PROP_END_OF_LIST(),
454};
455
456static void riscv_cpu_class_init(ObjectClass *c, void *data)
457{
458 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
459 CPUClass *cc = CPU_CLASS(c);
460 DeviceClass *dc = DEVICE_CLASS(c);
461
462 device_class_set_parent_realize(dc, riscv_cpu_realize,
463 &mcc->parent_realize);
464
465 mcc->parent_reset = cc->reset;
466 cc->reset = riscv_cpu_reset;
467
468 cc->class_by_name = riscv_cpu_class_by_name;
469 cc->has_work = riscv_cpu_has_work;
470 cc->do_interrupt = riscv_cpu_do_interrupt;
471 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
472 cc->dump_state = riscv_cpu_dump_state;
473 cc->set_pc = riscv_cpu_set_pc;
474 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
475 cc->gdb_read_register = riscv_cpu_gdb_read_register;
476 cc->gdb_write_register = riscv_cpu_gdb_write_register;
477 cc->gdb_num_core_regs = 33;
478#if defined(TARGET_RISCV32)
479 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
480#elif defined(TARGET_RISCV64)
481 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
482#endif
483 cc->gdb_stop_before_watchpoint = true;
484 cc->disas_set_info = riscv_cpu_disas_set_info;
485#ifndef CONFIG_USER_ONLY
486 cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
487 cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
488 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
489#endif
490#ifdef CONFIG_TCG
491 cc->tcg_initialize = riscv_translate_init;
492 cc->tlb_fill = riscv_cpu_tlb_fill;
493#endif
494
495 cc->vmsd = &vmstate_riscv_cpu;
496 dc->props = riscv_cpu_properties;
497}
498
499char *riscv_isa_string(RISCVCPU *cpu)
500{
501 int i;
502 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
503 char *isa_str = g_new(char, maxlen);
504 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
505 for (i = 0; i < sizeof(riscv_exts); i++) {
506 if (cpu->env.misa & RV(riscv_exts[i])) {
507 *p++ = qemu_tolower(riscv_exts[i]);
508 }
509 }
510 *p = '\0';
511 return isa_str;
512}
513
514static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
515{
516 ObjectClass *class_a = (ObjectClass *)a;
517 ObjectClass *class_b = (ObjectClass *)b;
518 const char *name_a, *name_b;
519
520 name_a = object_class_get_name(class_a);
521 name_b = object_class_get_name(class_b);
522 return strcmp(name_a, name_b);
523}
524
525static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
526{
527 const char *typename = object_class_get_name(OBJECT_CLASS(data));
528 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
529
530 qemu_printf("%.*s\n", len, typename);
531}
532
533void riscv_cpu_list(void)
534{
535 GSList *list;
536
537 list = object_class_get_list(TYPE_RISCV_CPU, false);
538 list = g_slist_sort(list, riscv_cpu_list_compare);
539 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
540 g_slist_free(list);
541}
542
543#define DEFINE_CPU(type_name, initfn) \
544 { \
545 .name = type_name, \
546 .parent = TYPE_RISCV_CPU, \
547 .instance_init = initfn \
548 }
549
550static const TypeInfo riscv_cpu_type_infos[] = {
551 {
552 .name = TYPE_RISCV_CPU,
553 .parent = TYPE_CPU,
554 .instance_size = sizeof(RISCVCPU),
555 .instance_init = riscv_cpu_init,
556 .abstract = true,
557 .class_size = sizeof(RISCVCPUClass),
558 .class_init = riscv_cpu_class_init,
559 },
560 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
561#if defined(TARGET_RISCV32)
562 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
563 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
564 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
565
566 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
567 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
568 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
569#elif defined(TARGET_RISCV64)
570 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
571 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
572 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
573
574 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
575 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
576 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
577#endif
578};
579
580DEFINE_TYPES(riscv_cpu_type_infos)
581
