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26#include "qemu/osdep.h"
27#include "qemu/log.h"
28#include "qapi/error.h"
29#include "cpu.h"
30#include "trace.h"
31
32static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
33 uint8_t val);
34static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
35static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
36
37
38
39
40static inline uint8_t pmp_get_a_field(uint8_t cfg)
41{
42 uint8_t a = cfg >> 3;
43 return a & 0x3;
44}
45
46
47
48
49static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
50{
51
52 if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
53 return 1;
54 }
55
56
57 if ((pmp_index + 1u) >= MAX_RISCV_PMPS) {
58 return 0;
59 }
60
61
62
63
64 const uint8_t a_field =
65 pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
66 if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
67 (PMP_AMATCH_TOR == a_field)) {
68 return 1;
69 }
70
71 return 0;
72}
73
74
75
76
77static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
78{
79 return env->pmp_state.num_rules;
80}
81
82
83
84
85static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
86{
87 if (pmp_index < MAX_RISCV_PMPS) {
88 return env->pmp_state.pmp[pmp_index].cfg_reg;
89 }
90
91 return 0;
92}
93
94
95
96
97
98
99static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
100{
101 if (pmp_index < MAX_RISCV_PMPS) {
102 if (!pmp_is_locked(env, pmp_index)) {
103 env->pmp_state.pmp[pmp_index].cfg_reg = val;
104 pmp_update_rule(env, pmp_index);
105 } else {
106 qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
107 }
108 } else {
109 qemu_log_mask(LOG_GUEST_ERROR,
110 "ignoring pmpcfg write - out of bounds\n");
111 }
112}
113
114static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
115{
116
117
118
119
120
121
122
123
124
125
126 if (a == -1) {
127 *sa = 0u;
128 *ea = -1;
129 return;
130 } else {
131 target_ulong t1 = ctz64(~a);
132 target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
133 target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
134 *sa = base;
135 *ea = base + range;
136 }
137}
138
139
140
141
142
143
144
145static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
146{
147 int i;
148
149 env->pmp_state.num_rules = 0;
150
151 uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
152 target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
153 target_ulong prev_addr = 0u;
154 target_ulong sa = 0u;
155 target_ulong ea = 0u;
156
157 if (pmp_index >= 1u) {
158 prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
159 }
160
161 switch (pmp_get_a_field(this_cfg)) {
162 case PMP_AMATCH_OFF:
163 sa = 0u;
164 ea = -1;
165 break;
166
167 case PMP_AMATCH_TOR:
168 sa = prev_addr << 2;
169 ea = (this_addr << 2) - 1u;
170 break;
171
172 case PMP_AMATCH_NA4:
173 sa = this_addr << 2;
174 ea = (this_addr + 4u) - 1u;
175 break;
176
177 case PMP_AMATCH_NAPOT:
178 pmp_decode_napot(this_addr, &sa, &ea);
179 break;
180
181 default:
182 sa = 0u;
183 ea = 0u;
184 break;
185 }
186
187 env->pmp_state.addr[pmp_index].sa = sa;
188 env->pmp_state.addr[pmp_index].ea = ea;
189
190 for (i = 0; i < MAX_RISCV_PMPS; i++) {
191 const uint8_t a_field =
192 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
193 if (PMP_AMATCH_OFF != a_field) {
194 env->pmp_state.num_rules++;
195 }
196 }
197}
198
199static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
200{
201 int result = 0;
202
203 if ((addr >= env->pmp_state.addr[pmp_index].sa)
204 && (addr <= env->pmp_state.addr[pmp_index].ea)) {
205 result = 1;
206 } else {
207 result = 0;
208 }
209
210 return result;
211}
212
213
214
215
216
217
218
219
220
221bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
222 target_ulong size, pmp_priv_t privs, target_ulong mode)
223{
224 int i = 0;
225 int ret = -1;
226 int pmp_size = 0;
227 target_ulong s = 0;
228 target_ulong e = 0;
229 pmp_priv_t allowed_privs = 0;
230
231
232 if (0 == pmp_get_num_rules(env)) {
233 return true;
234 }
235
236
237
238
239
240 if (size == 0) {
241 pmp_size = -(addr | TARGET_PAGE_MASK);
242 } else {
243 pmp_size = size;
244 }
245
246
247
248 for (i = 0; i < MAX_RISCV_PMPS; i++) {
249 s = pmp_is_in_range(env, i, addr);
250 e = pmp_is_in_range(env, i, addr + pmp_size - 1);
251
252
253 if ((s + e) == 1) {
254 qemu_log_mask(LOG_GUEST_ERROR,
255 "pmp violation - access is partially inside\n");
256 ret = 0;
257 break;
258 }
259
260
261 const uint8_t a_field =
262 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
263
264
265
266
267
268 if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
269 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
270 if ((mode != PRV_M) || pmp_is_locked(env, i)) {
271 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
272 }
273
274 if ((privs & allowed_privs) == privs) {
275 ret = 1;
276 break;
277 } else {
278 ret = 0;
279 break;
280 }
281 }
282 }
283
284
285 if (ret == -1) {
286 if (mode == PRV_M) {
287 ret = 1;
288
289 } else {
290 ret = 0;
291
292
293 }
294 }
295
296 return ret == 1 ? true : false;
297}
298
299
300
301
302
303void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
304 target_ulong val)
305{
306 int i;
307 uint8_t cfg_val;
308
309 trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
310
311 if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
312 qemu_log_mask(LOG_GUEST_ERROR,
313 "ignoring pmpcfg write - incorrect address\n");
314 return;
315 }
316
317 for (i = 0; i < sizeof(target_ulong); i++) {
318 cfg_val = (val >> 8 * i) & 0xff;
319 pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
320 cfg_val);
321 }
322}
323
324
325
326
327
328target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
329{
330 int i;
331 target_ulong cfg_val = 0;
332 target_ulong val = 0;
333
334 for (i = 0; i < sizeof(target_ulong); i++) {
335 val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
336 cfg_val |= (val << (i * 8));
337 }
338 trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
339
340 return cfg_val;
341}
342
343
344
345
346
347void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
348 target_ulong val)
349{
350 trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
351 if (addr_index < MAX_RISCV_PMPS) {
352 if (!pmp_is_locked(env, addr_index)) {
353 env->pmp_state.pmp[addr_index].addr_reg = val;
354 pmp_update_rule(env, addr_index);
355 } else {
356 qemu_log_mask(LOG_GUEST_ERROR,
357 "ignoring pmpaddr write - locked\n");
358 }
359 } else {
360 qemu_log_mask(LOG_GUEST_ERROR,
361 "ignoring pmpaddr write - out of bounds\n");
362 }
363}
364
365
366
367
368
369target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
370{
371 target_ulong val = 0;
372
373 if (addr_index < MAX_RISCV_PMPS) {
374 val = env->pmp_state.pmp[addr_index].addr_reg;
375 trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
376 } else {
377 qemu_log_mask(LOG_GUEST_ERROR,
378 "ignoring pmpaddr read - out of bounds\n");
379 }
380
381 return val;
382}
383