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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qapi/error.h"
23#include "hw/sysbus.h"
24#include "migration/vmstate.h"
25#include "hw/arm/boot.h"
26#include "hw/loader.h"
27#include "net/net.h"
28#include "sysemu/kvm.h"
29#include "sysemu/runstate.h"
30#include "sysemu/sysemu.h"
31#include "hw/boards.h"
32#include "exec/address-spaces.h"
33#include "qemu/error-report.h"
34#include "hw/char/pl011.h"
35#include "hw/ide/ahci.h"
36#include "hw/cpu/a9mpcore.h"
37#include "hw/cpu/a15mpcore.h"
38#include "qemu/log.h"
39
40#define SMP_BOOT_ADDR 0x100
41#define SMP_BOOT_REG 0x40
42#define MPCORE_PERIPHBASE 0xfff10000
43
44#define MVBAR_ADDR 0x200
45#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
46
47#define NIRQ_GIC 160
48
49
50
51static void hb_write_board_setup(ARMCPU *cpu,
52 const struct arm_boot_info *info)
53{
54 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
55}
56
57static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
58{
59 int n;
60 uint32_t smpboot[] = {
61 0xee100fb0,
62 0xe210000f,
63 0xe3a03040,
64 0xe0830200,
65 0xe59f2024,
66 0xe3a01001,
67 0xe5821100,
68 0xe3a010ff,
69 0xe5821104,
70 0xf57ff04f,
71 0xe320f003,
72 0xe5901000,
73 0xe1110001,
74 0x0afffffb,
75 0xe12fff11,
76 MPCORE_PERIPHBASE
77 };
78 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
79 smpboot[n] = tswap32(smpboot[n]);
80 }
81 rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
82 arm_boot_address_space(cpu, info));
83}
84
85static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
86{
87 CPUARMState *env = &cpu->env;
88
89 switch (info->nb_cpus) {
90 case 4:
91 address_space_stl_notdirty(&address_space_memory,
92 SMP_BOOT_REG + 0x30, 0,
93 MEMTXATTRS_UNSPECIFIED, NULL);
94 case 3:
95 address_space_stl_notdirty(&address_space_memory,
96 SMP_BOOT_REG + 0x20, 0,
97 MEMTXATTRS_UNSPECIFIED, NULL);
98 case 2:
99 address_space_stl_notdirty(&address_space_memory,
100 SMP_BOOT_REG + 0x10, 0,
101 MEMTXATTRS_UNSPECIFIED, NULL);
102 env->regs[15] = SMP_BOOT_ADDR;
103 break;
104 default:
105 break;
106 }
107}
108
109#define NUM_REGS 0x200
110static void hb_regs_write(void *opaque, hwaddr offset,
111 uint64_t value, unsigned size)
112{
113 uint32_t *regs = opaque;
114
115 if (offset == 0xf00) {
116 if (value == 1 || value == 2) {
117 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
118 } else if (value == 3) {
119 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
120 }
121 }
122
123 if (offset / 4 >= NUM_REGS) {
124 qemu_log_mask(LOG_GUEST_ERROR,
125 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
126 return;
127 }
128 regs[offset / 4] = value;
129}
130
131static uint64_t hb_regs_read(void *opaque, hwaddr offset,
132 unsigned size)
133{
134 uint32_t value;
135 uint32_t *regs = opaque;
136
137 if (offset / 4 >= NUM_REGS) {
138 qemu_log_mask(LOG_GUEST_ERROR,
139 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
140 return 0;
141 }
142 value = regs[offset / 4];
143
144 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
145 value |= 0x30000000;
146 }
147
148 return value;
149}
150
151static const MemoryRegionOps hb_mem_ops = {
152 .read = hb_regs_read,
153 .write = hb_regs_write,
154 .endianness = DEVICE_NATIVE_ENDIAN,
155};
156
157#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
158#define HIGHBANK_REGISTERS(obj) \
159 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
160
161typedef struct {
162
163 SysBusDevice parent_obj;
164
165
166 MemoryRegion iomem;
167 uint32_t regs[NUM_REGS];
168} HighbankRegsState;
169
170static VMStateDescription vmstate_highbank_regs = {
171 .name = "highbank-regs",
172 .version_id = 0,
173 .minimum_version_id = 0,
174 .fields = (VMStateField[]) {
175 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
176 VMSTATE_END_OF_LIST(),
177 },
178};
179
180static void highbank_regs_reset(DeviceState *dev)
181{
182 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
183
184 s->regs[0x40] = 0x05F20121;
185 s->regs[0x41] = 0x2;
186 s->regs[0x42] = 0x05F30121;
187 s->regs[0x43] = 0x05F40121;
188}
189
190static void highbank_regs_init(Object *obj)
191{
192 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
193 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
194
195 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
196 "highbank_regs", 0x1000);
197 sysbus_init_mmio(dev, &s->iomem);
198}
199
200static void highbank_regs_class_init(ObjectClass *klass, void *data)
201{
202 DeviceClass *dc = DEVICE_CLASS(klass);
203
204 dc->desc = "Calxeda Highbank registers";
205 dc->vmsd = &vmstate_highbank_regs;
206 dc->reset = highbank_regs_reset;
207}
208
209static const TypeInfo highbank_regs_info = {
210 .name = TYPE_HIGHBANK_REGISTERS,
211 .parent = TYPE_SYS_BUS_DEVICE,
212 .instance_size = sizeof(HighbankRegsState),
213 .instance_init = highbank_regs_init,
214 .class_init = highbank_regs_class_init,
215};
216
217static void highbank_regs_register_types(void)
218{
219 type_register_static(&highbank_regs_info);
220}
221
222type_init(highbank_regs_register_types)
223
224static struct arm_boot_info highbank_binfo;
225
226enum cxmachines {
227 CALXEDA_HIGHBANK,
228 CALXEDA_MIDWAY,
229};
230
231
232
233
234
235
236
237static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
238{
239 ram_addr_t ram_size = machine->ram_size;
240 DeviceState *dev = NULL;
241 SysBusDevice *busdev;
242 qemu_irq pic[128];
243 int n;
244 unsigned int smp_cpus = machine->smp.cpus;
245 qemu_irq cpu_irq[4];
246 qemu_irq cpu_fiq[4];
247 qemu_irq cpu_virq[4];
248 qemu_irq cpu_vfiq[4];
249 MemoryRegion *sysram;
250 MemoryRegion *dram;
251 MemoryRegion *sysmem;
252 char *sysboot_filename;
253
254 switch (machine_id) {
255 case CALXEDA_HIGHBANK:
256 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
257 break;
258 case CALXEDA_MIDWAY:
259 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
260 break;
261 default:
262 assert(0);
263 }
264
265 for (n = 0; n < smp_cpus; n++) {
266 Object *cpuobj;
267 ARMCPU *cpu;
268
269 cpuobj = object_new(machine->cpu_type);
270 cpu = ARM_CPU(cpuobj);
271
272 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
273 "psci-conduit", &error_abort);
274
275 if (n) {
276
277 object_property_set_bool(cpuobj, true,
278 "start-powered-off", &error_abort);
279 }
280
281 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
282 object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
283 "reset-cbar", &error_abort);
284 }
285 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
286 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
287 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
288 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
289 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
290 }
291
292 sysmem = get_system_memory();
293 dram = g_new(MemoryRegion, 1);
294 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
295
296 memory_region_add_subregion(sysmem, 0, dram);
297
298 sysram = g_new(MemoryRegion, 1);
299 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
300 &error_fatal);
301 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
302 if (bios_name != NULL) {
303 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
304 if (sysboot_filename != NULL) {
305 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
306 error_report("Unable to load %s", bios_name);
307 exit(1);
308 }
309 g_free(sysboot_filename);
310 } else {
311 error_report("Unable to find %s", bios_name);
312 exit(1);
313 }
314 }
315
316 switch (machine_id) {
317 case CALXEDA_HIGHBANK:
318 dev = qdev_create(NULL, "l2x0");
319 qdev_init_nofail(dev);
320 busdev = SYS_BUS_DEVICE(dev);
321 sysbus_mmio_map(busdev, 0, 0xfff12000);
322
323 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
324 break;
325 case CALXEDA_MIDWAY:
326 dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
327 break;
328 }
329 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
330 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
331 qdev_init_nofail(dev);
332 busdev = SYS_BUS_DEVICE(dev);
333 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
334 for (n = 0; n < smp_cpus; n++) {
335 sysbus_connect_irq(busdev, n, cpu_irq[n]);
336 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
337 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
338 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
339 }
340
341 for (n = 0; n < 128; n++) {
342 pic[n] = qdev_get_gpio_in(dev, n);
343 }
344
345 dev = qdev_create(NULL, "sp804");
346 qdev_prop_set_uint32(dev, "freq0", 150000000);
347 qdev_prop_set_uint32(dev, "freq1", 150000000);
348 qdev_init_nofail(dev);
349 busdev = SYS_BUS_DEVICE(dev);
350 sysbus_mmio_map(busdev, 0, 0xfff34000);
351 sysbus_connect_irq(busdev, 0, pic[18]);
352 pl011_create(0xfff36000, pic[20], serial_hd(0));
353
354 dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
355 qdev_init_nofail(dev);
356 busdev = SYS_BUS_DEVICE(dev);
357 sysbus_mmio_map(busdev, 0, 0xfff3c000);
358
359 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
360 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
361 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
362 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
363 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
364 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
365
366 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
367
368 if (nd_table[0].used) {
369 qemu_check_nic_model(&nd_table[0], "xgmac");
370 dev = qdev_create(NULL, "xgmac");
371 qdev_set_nic_properties(dev, &nd_table[0]);
372 qdev_init_nofail(dev);
373 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
374 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
376 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
377
378 qemu_check_nic_model(&nd_table[1], "xgmac");
379 dev = qdev_create(NULL, "xgmac");
380 qdev_set_nic_properties(dev, &nd_table[1]);
381 qdev_init_nofail(dev);
382 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
383 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
385 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
386 }
387
388
389
390 highbank_binfo.ram_size = ram_size;
391
392
393
394
395 highbank_binfo.board_id = -1;
396 highbank_binfo.nb_cpus = smp_cpus;
397 highbank_binfo.loader_start = 0;
398 highbank_binfo.write_secondary_boot = hb_write_secondary;
399 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
400 if (!kvm_enabled()) {
401 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
402 highbank_binfo.write_board_setup = hb_write_board_setup;
403 highbank_binfo.secure_board_setup = true;
404 } else {
405 warn_report("cannot load built-in Monitor support "
406 "if KVM is enabled. Some guests (such as Linux) "
407 "may not boot.");
408 }
409
410 arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
411}
412
413static void highbank_init(MachineState *machine)
414{
415 calxeda_init(machine, CALXEDA_HIGHBANK);
416}
417
418static void midway_init(MachineState *machine)
419{
420 calxeda_init(machine, CALXEDA_MIDWAY);
421}
422
423static void highbank_class_init(ObjectClass *oc, void *data)
424{
425 MachineClass *mc = MACHINE_CLASS(oc);
426
427 mc->desc = "Calxeda Highbank (ECX-1000)";
428 mc->init = highbank_init;
429 mc->block_default_type = IF_IDE;
430 mc->units_per_default_bus = 1;
431 mc->max_cpus = 4;
432 mc->ignore_memory_transaction_failures = true;
433}
434
435static const TypeInfo highbank_type = {
436 .name = MACHINE_TYPE_NAME("highbank"),
437 .parent = TYPE_MACHINE,
438 .class_init = highbank_class_init,
439};
440
441static void midway_class_init(ObjectClass *oc, void *data)
442{
443 MachineClass *mc = MACHINE_CLASS(oc);
444
445 mc->desc = "Calxeda Midway (ECX-2000)";
446 mc->init = midway_init;
447 mc->block_default_type = IF_IDE;
448 mc->units_per_default_bus = 1;
449 mc->max_cpus = 4;
450 mc->ignore_memory_transaction_failures = true;
451}
452
453static const TypeInfo midway_type = {
454 .name = MACHINE_TYPE_NAME("midway"),
455 .parent = TYPE_MACHINE,
456 .class_init = midway_class_init,
457};
458
459static void calxeda_machines_init(void)
460{
461 type_register_static(&highbank_type);
462 type_register_static(&midway_type);
463}
464
465type_init(calxeda_machines_init)
466