LXR qemu/hw/i386/amd

   1/*
   2 * QEMU emulation of an AMD IOMMU (AMD-Vi)
   3 *
   4 * Copyright (C) 2011 Eduard - Gabriel Munteanu
   5 * Copyright (C) 2015, 2016 David Kiarie Kahurani
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef AMD_IOMMU_H
  22#define AMD_IOMMU_H
  23
  24#include "hw/pci/pci.h"
  25#include "hw/i386/x86-iommu.h"
  26
  27/* Capability registers */
  28#define AMDVI_CAPAB_BAR_LOW           0x04
  29#define AMDVI_CAPAB_BAR_HIGH          0x08
  30#define AMDVI_CAPAB_RANGE             0x0C
  31#define AMDVI_CAPAB_MISC              0x10
  32
  33#define AMDVI_CAPAB_SIZE              0x18
  34#define AMDVI_CAPAB_REG_SIZE          0x04
  35
  36/* Capability header data */
  37#define AMDVI_CAPAB_ID_SEC            0xf
  38#define AMDVI_CAPAB_FLAT_EXT          (1 << 28)
  39#define AMDVI_CAPAB_EFR_SUP           (1 << 27)
  40#define AMDVI_CAPAB_FLAG_NPCACHE      (1 << 26)
  41#define AMDVI_CAPAB_FLAG_HTTUNNEL     (1 << 25)
  42#define AMDVI_CAPAB_FLAG_IOTLBSUP     (1 << 24)
  43#define AMDVI_CAPAB_INIT_TYPE         (3 << 16)
  44
  45/* No. of used MMIO registers */
  46#define AMDVI_MMIO_REGS_HIGH  7
  47#define AMDVI_MMIO_REGS_LOW   8
  48
  49/* MMIO registers */
  50#define AMDVI_MMIO_DEVICE_TABLE       0x0000
  51#define AMDVI_MMIO_COMMAND_BASE       0x0008
  52#define AMDVI_MMIO_EVENT_BASE         0x0010
  53#define AMDVI_MMIO_CONTROL            0x0018
  54#define AMDVI_MMIO_EXCL_BASE          0x0020
  55#define AMDVI_MMIO_EXCL_LIMIT         0x0028
  56#define AMDVI_MMIO_EXT_FEATURES       0x0030
  57#define AMDVI_MMIO_COMMAND_HEAD       0x2000
  58#define AMDVI_MMIO_COMMAND_TAIL       0x2008
  59#define AMDVI_MMIO_EVENT_HEAD         0x2010
  60#define AMDVI_MMIO_EVENT_TAIL         0x2018
  61#define AMDVI_MMIO_STATUS             0x2020
  62#define AMDVI_MMIO_PPR_BASE           0x0038
  63#define AMDVI_MMIO_PPR_HEAD           0x2030
  64#define AMDVI_MMIO_PPR_TAIL           0x2038
  65
  66#define AMDVI_MMIO_SIZE               0x4000
  67
  68#define AMDVI_MMIO_DEVTAB_SIZE_MASK   ((1ULL << 12) - 1)
  69#define AMDVI_MMIO_DEVTAB_BASE_MASK   (((1ULL << 52) - 1) & ~ \
  70                                       AMDVI_MMIO_DEVTAB_SIZE_MASK)
  71#define AMDVI_MMIO_DEVTAB_ENTRY_SIZE  32
  72#define AMDVI_MMIO_DEVTAB_SIZE_UNIT   4096
  73
  74/* some of this are similar but just for readability */
  75#define AMDVI_MMIO_CMDBUF_SIZE_BYTE       (AMDVI_MMIO_COMMAND_BASE + 7)
  76#define AMDVI_MMIO_CMDBUF_SIZE_MASK       0x0f
  77#define AMDVI_MMIO_CMDBUF_BASE_MASK       AMDVI_MMIO_DEVTAB_BASE_MASK
  78#define AMDVI_MMIO_CMDBUF_HEAD_MASK       (((1ULL << 19) - 1) & ~0x0f)
  79#define AMDVI_MMIO_CMDBUF_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  80
  81#define AMDVI_MMIO_EVTLOG_SIZE_BYTE       (AMDVI_MMIO_EVENT_BASE + 7)
  82#define AMDVI_MMIO_EVTLOG_SIZE_MASK       AMDVI_MMIO_CMDBUF_SIZE_MASK
  83#define AMDVI_MMIO_EVTLOG_BASE_MASK       AMDVI_MMIO_CMDBUF_BASE_MASK
  84#define AMDVI_MMIO_EVTLOG_HEAD_MASK       (((1ULL << 19) - 1) & ~0x0f)
  85#define AMDVI_MMIO_EVTLOG_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  86
  87#define AMDVI_MMIO_PPRLOG_SIZE_BYTE       (AMDVI_MMIO_EVENT_BASE + 7)
  88#define AMDVI_MMIO_PPRLOG_HEAD_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  89#define AMDVI_MMIO_PPRLOG_TAIL_MASK       AMDVI_MMIO_EVTLOG_HEAD_MASK
  90#define AMDVI_MMIO_PPRLOG_BASE_MASK       AMDVI_MMIO_EVTLOG_BASE_MASK
  91#define AMDVI_MMIO_PPRLOG_SIZE_MASK       AMDVI_MMIO_EVTLOG_SIZE_MASK
  92
  93#define AMDVI_MMIO_EXCL_ENABLED_MASK      (1ULL << 0)
  94#define AMDVI_MMIO_EXCL_ALLOW_MASK        (1ULL << 1)
  95#define AMDVI_MMIO_EXCL_LIMIT_MASK        AMDVI_MMIO_DEVTAB_BASE_MASK
  96#define AMDVI_MMIO_EXCL_LIMIT_LOW         0xfff
  97
  98/* mmio control register flags */
  99#define AMDVI_MMIO_CONTROL_AMDVIEN        (1ULL << 0)
 100#define AMDVI_MMIO_CONTROL_HTTUNEN        (1ULL << 1)
 101#define AMDVI_MMIO_CONTROL_EVENTLOGEN     (1ULL << 2)
 102#define AMDVI_MMIO_CONTROL_EVENTINTEN     (1ULL << 3)
 103#define AMDVI_MMIO_CONTROL_COMWAITINTEN   (1ULL << 4)
 104#define AMDVI_MMIO_CONTROL_CMDBUFLEN      (1ULL << 12)
 105#define AMDVI_MMIO_CONTROL_GAEN           (1ULL << 17)
 106
 107/* MMIO status register bits */
 108#define AMDVI_MMIO_STATUS_CMDBUF_RUN  (1 << 4)
 109#define AMDVI_MMIO_STATUS_EVT_RUN     (1 << 3)
 110#define AMDVI_MMIO_STATUS_COMP_INT    (1 << 2)
 111#define AMDVI_MMIO_STATUS_EVT_OVF     (1 << 0)
 112
 113#define AMDVI_CMDBUF_ID_BYTE              0x07
 114#define AMDVI_CMDBUF_ID_RSHIFT            4
 115
 116#define AMDVI_CMD_COMPLETION_WAIT         0x01
 117#define AMDVI_CMD_INVAL_DEVTAB_ENTRY      0x02
 118#define AMDVI_CMD_INVAL_AMDVI_PAGES       0x03
 119#define AMDVI_CMD_INVAL_IOTLB_PAGES       0x04
 120#define AMDVI_CMD_INVAL_INTR_TABLE        0x05
 121#define AMDVI_CMD_PREFETCH_AMDVI_PAGES    0x06
 122#define AMDVI_CMD_COMPLETE_PPR_REQUEST    0x07
 123#define AMDVI_CMD_INVAL_AMDVI_ALL         0x08
 124
 125#define AMDVI_DEVTAB_ENTRY_SIZE           32
 126
 127/* Device table entry bits 0:63 */
 128#define AMDVI_DEV_VALID                   (1ULL << 0)
 129#define AMDVI_DEV_TRANSLATION_VALID       (1ULL << 1)
 130#define AMDVI_DEV_MODE_MASK               0x7
 131#define AMDVI_DEV_MODE_RSHIFT             9
 132#define AMDVI_DEV_PT_ROOT_MASK            0xffffffffff000
 133#define AMDVI_DEV_PT_ROOT_RSHIFT          12
 134#define AMDVI_DEV_PERM_SHIFT              61
 135#define AMDVI_DEV_PERM_READ               (1ULL << 61)
 136#define AMDVI_DEV_PERM_WRITE              (1ULL << 62)
 137
 138/* Device table entry bits 64:127 */
 139#define AMDVI_DEV_DOMID_ID_MASK          ((1ULL << 16) - 1)
 140
 141/* Event codes and flags, as stored in the info field */
 142#define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY  (0x1U << 12)
 143#define AMDVI_EVENT_IOPF                  (0x2U << 12)
 144#define   AMDVI_EVENT_IOPF_I              (1U << 3)
 145#define AMDVI_EVENT_DEV_TAB_HW_ERROR      (0x3U << 12)
 146#define AMDVI_EVENT_PAGE_TAB_HW_ERROR     (0x4U << 12)
 147#define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12)
 148#define AMDVI_EVENT_COMMAND_HW_ERROR      (0x6U << 12)
 149
 150#define AMDVI_EVENT_LEN                  16
 151#define AMDVI_PERM_READ             (1 << 0)
 152#define AMDVI_PERM_WRITE            (1 << 1)
 153
 154#define AMDVI_FEATURE_PREFETCH            (1ULL << 0) /* page prefetch       */
 155#define AMDVI_FEATURE_PPR                 (1ULL << 1) /* PPR Support         */
 156#define AMDVI_FEATURE_GT                  (1ULL << 4) /* Guest Translation   */
 157#define AMDVI_FEATURE_IA                  (1ULL << 6) /* inval all support   */
 158#define AMDVI_FEATURE_GA                  (1ULL << 7) /* guest VAPIC support */
 159#define AMDVI_FEATURE_HE                  (1ULL << 8) /* hardware error regs */
 160#define AMDVI_FEATURE_PC                  (1ULL << 9) /* Perf counters       */
 161
 162/* reserved DTE bits */
 163#define AMDVI_DTE_LOWER_QUAD_RESERVED  0x80300000000000fc
 164#define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100
 165#define AMDVI_DTE_UPPER_QUAD_RESERVED  0x08f0000000000000
 166
 167/* AMDVI paging mode */
 168#define AMDVI_GATS_MODE                 (2ULL <<  12)
 169#define AMDVI_HATS_MODE                 (2ULL <<  10)
 170
 171/* IOTLB */
 172#define AMDVI_IOTLB_MAX_SIZE 1024
 173#define AMDVI_DEVID_SHIFT    36
 174
 175/* extended feature support */
 176#define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \
 177        AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \
 178        AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA)
 179
 180/* capabilities header */
 181#define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \
 182        AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \
 183        | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \
 184        AMDVI_CAPAB_FLAG_HTTUNNEL |  AMDVI_CAPAB_EFR_SUP)
 185
 186/* AMDVI default address */
 187#define AMDVI_BASE_ADDR 0xfed80000
 188
 189/* page management constants */
 190#define AMDVI_PAGE_SHIFT 12
 191#define AMDVI_PAGE_SIZE  (1ULL << AMDVI_PAGE_SHIFT)
 192
 193#define AMDVI_PAGE_SHIFT_4K 12
 194#define AMDVI_PAGE_MASK_4K  (~((1ULL << AMDVI_PAGE_SHIFT_4K) - 1))
 195
 196#define AMDVI_MAX_VA_ADDR          (48UL << 5)
 197#define AMDVI_MAX_PH_ADDR          (40UL << 8)
 198#define AMDVI_MAX_GVA_ADDR         (48UL << 15)
 199
 200/* Completion Wait data size */
 201#define AMDVI_COMPLETION_DATA_SIZE    8
 202
 203#define AMDVI_COMMAND_SIZE   16
 204/* Completion Wait data size */
 205#define AMDVI_COMPLETION_DATA_SIZE    8
 206
 207#define AMDVI_COMMAND_SIZE   16
 208
 209#define AMDVI_INT_ADDR_FIRST    0xfee00000
 210#define AMDVI_INT_ADDR_LAST     0xfeefffff
 211#define AMDVI_INT_ADDR_SIZE     (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1)
 212#define AMDVI_MSI_ADDR_HI_MASK  (0xffffffff00000000ULL)
 213#define AMDVI_MSI_ADDR_LO_MASK  (0x00000000ffffffffULL)
 214
 215/* SB IOAPIC is always on this device in AMD systems */
 216#define AMDVI_IOAPIC_SB_DEVID   PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
 217
 218/* Interrupt remapping errors */
 219#define AMDVI_IR_ERR            0x1
 220#define AMDVI_IR_GET_IRTE       0x2
 221#define AMDVI_IR_TARGET_ABORT   0x3
 222
 223/* Interrupt remapping */
 224#define AMDVI_IR_REMAP_ENABLE           1ULL
 225#define AMDVI_IR_INTCTL_SHIFT           60
 226#define AMDVI_IR_INTCTL_ABORT           0
 227#define AMDVI_IR_INTCTL_PASS            1
 228#define AMDVI_IR_INTCTL_REMAP           2
 229
 230#define AMDVI_IR_PHYS_ADDR_MASK         (((1ULL << 45) - 1) << 6)
 231
 232/* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */
 233#define AMDVI_IRTE_OFFSET               0x7ff
 234
 235/* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */
 236#define AMDVI_IOAPIC_INT_TYPE_FIXED          0x0
 237#define AMDVI_IOAPIC_INT_TYPE_ARBITRATED     0x1
 238#define AMDVI_IOAPIC_INT_TYPE_SMI            0x2
 239#define AMDVI_IOAPIC_INT_TYPE_NMI            0x4
 240#define AMDVI_IOAPIC_INT_TYPE_INIT           0x5
 241#define AMDVI_IOAPIC_INT_TYPE_EINT           0x7
 242
 243/* Pass through interrupt */
 244#define AMDVI_DEV_INT_PASS_MASK         (1ULL << 56)
 245#define AMDVI_DEV_EINT_PASS_MASK        (1ULL << 57)
 246#define AMDVI_DEV_NMI_PASS_MASK         (1ULL << 58)
 247#define AMDVI_DEV_LINT0_PASS_MASK       (1ULL << 62)
 248#define AMDVI_DEV_LINT1_PASS_MASK       (1ULL << 63)
 249
 250/* Interrupt remapping table fields (Guest VAPIC not enabled) */
 251union irte {
 252    uint32_t val;
 253    struct {
 254        uint32_t valid:1,
 255                 no_fault:1,
 256                 int_type:3,
 257                 rq_eoi:1,
 258                 dm:1,
 259                 guest_mode:1,
 260                 destination:8,
 261                 vector:8,
 262                 rsvd:8;
 263    } fields;
 264};
 265
 266/* Interrupt remapping table fields (Guest VAPIC is enabled) */
 267union irte_ga_lo {
 268  uint64_t val;
 269
 270  /* For int remapping */
 271  struct {
 272      uint64_t  valid:1,
 273                no_fault:1,
 274                /* ------ */
 275                int_type:3,
 276                rq_eoi:1,
 277                dm:1,
 278                /* ------ */
 279                guest_mode:1,
 280                destination:8,
 281                rsvd_1:48;
 282  } fields_remap;
 283};
 284
 285union irte_ga_hi {
 286  uint64_t val;
 287  struct {
 288      uint64_t  vector:8,
 289                rsvd_2:56;
 290  } fields;
 291};
 292
 293struct irte_ga {
 294  union irte_ga_lo lo;
 295  union irte_ga_hi hi;
 296};
 297
 298#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
 299#define AMD_IOMMU_DEVICE(obj)\
 300    OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE)
 301
 302#define TYPE_AMD_IOMMU_PCI "AMDVI-PCI"
 303
 304#define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region"
 305
 306typedef struct AMDVIAddressSpace AMDVIAddressSpace;
 307
 308/* functions to steal PCI config space */
 309typedef struct AMDVIPCIState {
 310    PCIDevice dev;               /* The PCI device itself        */
 311} AMDVIPCIState;
 312
 313typedef struct AMDVIState {
 314    X86IOMMUState iommu;        /* IOMMU bus device             */
 315    AMDVIPCIState pci;          /* IOMMU PCI device             */
 316
 317    uint32_t version;
 318    uint32_t capab_offset;       /* capability offset pointer    */
 319
 320    uint64_t mmio_addr;
 321
 322    uint32_t devid;              /* auto-assigned devid          */
 323
 324    bool enabled;                /* IOMMU enabled                */
 325    bool ats_enabled;            /* address translation enabled  */
 326    bool cmdbuf_enabled;         /* command buffer enabled       */
 327    bool evtlog_enabled;         /* event log enabled            */
 328    bool excl_enabled;
 329
 330    hwaddr devtab;               /* base address device table    */
 331    size_t devtab_len;           /* device table length          */
 332
 333    hwaddr cmdbuf;               /* command buffer base address  */
 334    uint64_t cmdbuf_len;         /* command buffer length        */
 335    uint32_t cmdbuf_head;        /* current IOMMU read position  */
 336    uint32_t cmdbuf_tail;        /* next Software write position */
 337    bool completion_wait_intr;
 338
 339    hwaddr evtlog;               /* base address event log       */
 340    bool evtlog_intr;
 341    uint32_t evtlog_len;         /* event log length             */
 342    uint32_t evtlog_head;        /* current IOMMU write position */
 343    uint32_t evtlog_tail;        /* current Software read position */
 344
 345    /* unused for now */
 346    hwaddr excl_base;            /* base DVA - IOMMU exclusion range */
 347    hwaddr excl_limit;           /* limit of IOMMU exclusion range   */
 348    bool excl_allow;             /* translate accesses to the exclusion range */
 349    bool excl_enable;            /* exclusion range enabled          */
 350
 351    hwaddr ppr_log;              /* base address ppr log */
 352    uint32_t pprlog_len;         /* ppr log len  */
 353    uint32_t pprlog_head;        /* ppr log head */
 354    uint32_t pprlog_tail;        /* ppr log tail */
 355
 356    MemoryRegion mmio;                 /* MMIO region                  */
 357    uint8_t mmior[AMDVI_MMIO_SIZE];    /* read/write MMIO              */
 358    uint8_t w1cmask[AMDVI_MMIO_SIZE];  /* read/write 1 clear mask      */
 359    uint8_t romask[AMDVI_MMIO_SIZE];   /* MMIO read/only mask          */
 360    bool mmio_enabled;
 361
 362    /* for each served device */
 363    AMDVIAddressSpace **address_spaces[PCI_BUS_MAX];
 364
 365    /* IOTLB */
 366    GHashTable *iotlb;
 367
 368    /* Interrupt remapping */
 369    bool ga_enabled;
 370} AMDVIState;
 371
 372#endif
 373