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22#include "qemu/osdep.h"
23#include "qemu/error-report.h"
24#include "qemu/main-loop.h"
25#include "qapi/error.h"
26#include "hw/sysbus.h"
27#include "exec/address-spaces.h"
28#include "intel_iommu_internal.h"
29#include "hw/pci/pci.h"
30#include "hw/pci/pci_bus.h"
31#include "hw/qdev-properties.h"
32#include "hw/i386/pc.h"
33#include "hw/i386/apic-msidef.h"
34#include "hw/boards.h"
35#include "hw/i386/x86-iommu.h"
36#include "hw/pci-host/q35.h"
37#include "sysemu/kvm.h"
38#include "sysemu/sysemu.h"
39#include "hw/i386/apic_internal.h"
40#include "kvm_i386.h"
41#include "migration/vmstate.h"
42#include "trace.h"
43
44
45#define VTD_CE_GET_RID2PASID(ce) \
46 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
47#define VTD_CE_GET_PASID_DIR_TABLE(ce) \
48 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
49
50
51#define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
52#define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
53#define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\
54 if (ret_fr) { \
55 ret_fr = -ret_fr; \
56 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \
57 trace_vtd_fault_disabled(); \
58 } else { \
59 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \
60 } \
61 goto error; \
62 } \
63}
64
65static void vtd_address_space_refresh_all(IntelIOMMUState *s);
66static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
67
68static void vtd_panic_require_caching_mode(void)
69{
70 error_report("We need to set caching-mode=on for intel-iommu to enable "
71 "device assignment with IOMMU protection.");
72 exit(1);
73}
74
75static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
76 uint64_t wmask, uint64_t w1cmask)
77{
78 stq_le_p(&s->csr[addr], val);
79 stq_le_p(&s->wmask[addr], wmask);
80 stq_le_p(&s->w1cmask[addr], w1cmask);
81}
82
83static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
84{
85 stq_le_p(&s->womask[addr], mask);
86}
87
88static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
89 uint32_t wmask, uint32_t w1cmask)
90{
91 stl_le_p(&s->csr[addr], val);
92 stl_le_p(&s->wmask[addr], wmask);
93 stl_le_p(&s->w1cmask[addr], w1cmask);
94}
95
96static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
97{
98 stl_le_p(&s->womask[addr], mask);
99}
100
101
102static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
103{
104 uint64_t oldval = ldq_le_p(&s->csr[addr]);
105 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
106 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
107 stq_le_p(&s->csr[addr],
108 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
109}
110
111static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
112{
113 uint32_t oldval = ldl_le_p(&s->csr[addr]);
114 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
115 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
116 stl_le_p(&s->csr[addr],
117 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
118}
119
120static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
121{
122 uint64_t val = ldq_le_p(&s->csr[addr]);
123 uint64_t womask = ldq_le_p(&s->womask[addr]);
124 return val & ~womask;
125}
126
127static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
128{
129 uint32_t val = ldl_le_p(&s->csr[addr]);
130 uint32_t womask = ldl_le_p(&s->womask[addr]);
131 return val & ~womask;
132}
133
134
135static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
136{
137 return ldq_le_p(&s->csr[addr]);
138}
139
140static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
141{
142 return ldl_le_p(&s->csr[addr]);
143}
144
145static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
146{
147 stq_le_p(&s->csr[addr], val);
148}
149
150static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
151 uint32_t clear, uint32_t mask)
152{
153 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
154 stl_le_p(&s->csr[addr], new_val);
155 return new_val;
156}
157
158static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
159 uint64_t clear, uint64_t mask)
160{
161 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
162 stq_le_p(&s->csr[addr], new_val);
163 return new_val;
164}
165
166static inline void vtd_iommu_lock(IntelIOMMUState *s)
167{
168 qemu_mutex_lock(&s->iommu_lock);
169}
170
171static inline void vtd_iommu_unlock(IntelIOMMUState *s)
172{
173 qemu_mutex_unlock(&s->iommu_lock);
174}
175
176static void vtd_update_scalable_state(IntelIOMMUState *s)
177{
178 uint64_t val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
179
180 if (s->scalable_mode) {
181 s->root_scalable = val & VTD_RTADDR_SMT;
182 }
183}
184
185
186static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as)
187{
188 return as->notifier_flags & IOMMU_NOTIFIER_MAP;
189}
190
191
192static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
193{
194 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
195}
196
197static guint vtd_uint64_hash(gconstpointer v)
198{
199 return (guint)*(const uint64_t *)v;
200}
201
202static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
203 gpointer user_data)
204{
205 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
206 uint16_t domain_id = *(uint16_t *)user_data;
207 return entry->domain_id == domain_id;
208}
209
210
211static inline uint32_t vtd_slpt_level_shift(uint32_t level)
212{
213 assert(level != 0);
214 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
215}
216
217static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
218{
219 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
220}
221
222static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
223 gpointer user_data)
224{
225 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
226 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
227 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
228 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
229 return (entry->domain_id == info->domain_id) &&
230 (((entry->gfn & info->mask) == gfn) ||
231 (entry->gfn == gfn_tlb));
232}
233
234
235
236
237static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
238{
239 VTDAddressSpace *vtd_as;
240 VTDBus *vtd_bus;
241 GHashTableIter bus_it;
242 uint32_t devfn_it;
243
244 trace_vtd_context_cache_reset();
245
246 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
247
248 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
249 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
250 vtd_as = vtd_bus->dev_as[devfn_it];
251 if (!vtd_as) {
252 continue;
253 }
254 vtd_as->context_cache_entry.context_cache_gen = 0;
255 }
256 }
257 s->context_cache_gen = 1;
258}
259
260
261static void vtd_reset_iotlb_locked(IntelIOMMUState *s)
262{
263 assert(s->iotlb);
264 g_hash_table_remove_all(s->iotlb);
265}
266
267static void vtd_reset_iotlb(IntelIOMMUState *s)
268{
269 vtd_iommu_lock(s);
270 vtd_reset_iotlb_locked(s);
271 vtd_iommu_unlock(s);
272}
273
274static void vtd_reset_caches(IntelIOMMUState *s)
275{
276 vtd_iommu_lock(s);
277 vtd_reset_iotlb_locked(s);
278 vtd_reset_context_cache_locked(s);
279 vtd_iommu_unlock(s);
280}
281
282static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
283 uint32_t level)
284{
285 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
286 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
287}
288
289static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
290{
291 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
292}
293
294
295static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
296 hwaddr addr)
297{
298 VTDIOTLBEntry *entry;
299 uint64_t key;
300 int level;
301
302 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
303 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
304 source_id, level);
305 entry = g_hash_table_lookup(s->iotlb, &key);
306 if (entry) {
307 goto out;
308 }
309 }
310
311out:
312 return entry;
313}
314
315
316static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
317 uint16_t domain_id, hwaddr addr, uint64_t slpte,
318 uint8_t access_flags, uint32_t level)
319{
320 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
321 uint64_t *key = g_malloc(sizeof(*key));
322 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
323
324 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
325 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
326 trace_vtd_iotlb_reset("iotlb exceeds size limit");
327 vtd_reset_iotlb_locked(s);
328 }
329
330 entry->gfn = gfn;
331 entry->domain_id = domain_id;
332 entry->slpte = slpte;
333 entry->access_flags = access_flags;
334 entry->mask = vtd_slpt_level_page_mask(level);
335 *key = vtd_get_iotlb_key(gfn, source_id, level);
336 g_hash_table_replace(s->iotlb, key, entry);
337}
338
339
340
341
342static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
343 hwaddr mesg_data_reg)
344{
345 MSIMessage msi;
346
347 assert(mesg_data_reg < DMAR_REG_SIZE);
348 assert(mesg_addr_reg < DMAR_REG_SIZE);
349
350 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
351 msi.data = vtd_get_long_raw(s, mesg_data_reg);
352
353 trace_vtd_irq_generate(msi.address, msi.data);
354
355 apic_get_class()->send_msi(&msi);
356}
357
358
359
360
361
362static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
363{
364 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
365 pre_fsts & VTD_FSTS_IQE) {
366 error_report_once("There are previous interrupt conditions "
367 "to be serviced by software, fault event "
368 "is not generated");
369 return;
370 }
371 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
372 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
373 error_report_once("Interrupt Mask set, irq is not generated");
374 } else {
375 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
376 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
377 }
378}
379
380
381
382
383static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
384{
385
386 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
387 addr += 8;
388
389 assert(index < DMAR_FRCD_REG_NR);
390
391 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
392}
393
394
395
396
397
398static void vtd_update_fsts_ppf(IntelIOMMUState *s)
399{
400 uint32_t i;
401 uint32_t ppf_mask = 0;
402
403 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
404 if (vtd_is_frcd_set(s, i)) {
405 ppf_mask = VTD_FSTS_PPF;
406 break;
407 }
408 }
409 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
410 trace_vtd_fsts_ppf(!!ppf_mask);
411}
412
413static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
414{
415
416 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
417 addr += 8;
418
419 assert(index < DMAR_FRCD_REG_NR);
420
421 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
422 vtd_update_fsts_ppf(s);
423}
424
425
426static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
427 uint16_t source_id, hwaddr addr,
428 VTDFaultReason fault, bool is_write)
429{
430 uint64_t hi = 0, lo;
431 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
432
433 assert(index < DMAR_FRCD_REG_NR);
434
435 lo = VTD_FRCD_FI(addr);
436 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
437 if (!is_write) {
438 hi |= VTD_FRCD_T;
439 }
440 vtd_set_quad_raw(s, frcd_reg_addr, lo);
441 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
442
443 trace_vtd_frr_new(index, hi, lo);
444}
445
446
447static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
448{
449 uint32_t i;
450 uint64_t frcd_reg;
451 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8;
452
453 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
454 frcd_reg = vtd_get_quad_raw(s, addr);
455 if ((frcd_reg & VTD_FRCD_F) &&
456 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
457 return true;
458 }
459 addr += 16;
460 }
461 return false;
462}
463
464
465static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
466 hwaddr addr, VTDFaultReason fault,
467 bool is_write)
468{
469 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
470
471 assert(fault < VTD_FR_MAX);
472
473 if (fault == VTD_FR_RESERVED_ERR) {
474
475 return;
476 }
477
478 trace_vtd_dmar_fault(source_id, fault, addr, is_write);
479
480 if (fsts_reg & VTD_FSTS_PFO) {
481 error_report_once("New fault is not recorded due to "
482 "Primary Fault Overflow");
483 return;
484 }
485
486 if (vtd_try_collapse_fault(s, source_id)) {
487 error_report_once("New fault is not recorded due to "
488 "compression of faults");
489 return;
490 }
491
492 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
493 error_report_once("Next Fault Recording Reg is used, "
494 "new fault is not recorded, set PFO field");
495 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
496 return;
497 }
498
499 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
500
501 if (fsts_reg & VTD_FSTS_PPF) {
502 error_report_once("There are pending faults already, "
503 "fault event is not generated");
504 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
505 s->next_frcd_reg++;
506 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
507 s->next_frcd_reg = 0;
508 }
509 } else {
510 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
511 VTD_FSTS_FRI(s->next_frcd_reg));
512 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
513 s->next_frcd_reg++;
514 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
515 s->next_frcd_reg = 0;
516 }
517
518
519
520 vtd_generate_fault_event(s, fsts_reg);
521 }
522}
523
524
525
526
527static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
528{
529 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
530
531 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
532 vtd_generate_fault_event(s, fsts_reg);
533}
534
535
536static void vtd_generate_completion_event(IntelIOMMUState *s)
537{
538 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
539 trace_vtd_inv_desc_wait_irq("One pending, skip current");
540 return;
541 }
542 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
543 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
544 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
545 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
546 "new event not generated");
547 return;
548 } else {
549
550 trace_vtd_inv_desc_wait_irq("Generating complete event");
551 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
552 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
553 }
554}
555
556static inline bool vtd_root_entry_present(IntelIOMMUState *s,
557 VTDRootEntry *re,
558 uint8_t devfn)
559{
560 if (s->root_scalable && devfn > UINT8_MAX / 2) {
561 return re->hi & VTD_ROOT_ENTRY_P;
562 }
563
564 return re->lo & VTD_ROOT_ENTRY_P;
565}
566
567static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
568 VTDRootEntry *re)
569{
570 dma_addr_t addr;
571
572 addr = s->root + index * sizeof(*re);
573 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
574 re->lo = 0;
575 return -VTD_FR_ROOT_TABLE_INV;
576 }
577 re->lo = le64_to_cpu(re->lo);
578 re->hi = le64_to_cpu(re->hi);
579 return 0;
580}
581
582static inline bool vtd_ce_present(VTDContextEntry *context)
583{
584 return context->lo & VTD_CONTEXT_ENTRY_P;
585}
586
587static int vtd_get_context_entry_from_root(IntelIOMMUState *s,
588 VTDRootEntry *re,
589 uint8_t index,
590 VTDContextEntry *ce)
591{
592 dma_addr_t addr, ce_size;
593
594
595 ce_size = s->root_scalable ? VTD_CTX_ENTRY_SCALABLE_SIZE :
596 VTD_CTX_ENTRY_LEGACY_SIZE;
597
598 if (s->root_scalable && index > UINT8_MAX / 2) {
599 index = index & (~VTD_DEVFN_CHECK_MASK);
600 addr = re->hi & VTD_ROOT_ENTRY_CTP;
601 } else {
602 addr = re->lo & VTD_ROOT_ENTRY_CTP;
603 }
604
605 addr = addr + index * ce_size;
606 if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) {
607 return -VTD_FR_CONTEXT_TABLE_INV;
608 }
609
610 ce->lo = le64_to_cpu(ce->lo);
611 ce->hi = le64_to_cpu(ce->hi);
612 if (ce_size == VTD_CTX_ENTRY_SCALABLE_SIZE) {
613 ce->val[2] = le64_to_cpu(ce->val[2]);
614 ce->val[3] = le64_to_cpu(ce->val[3]);
615 }
616 return 0;
617}
618
619static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
620{
621 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
622}
623
624static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
625{
626 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
627}
628
629
630static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
631{
632 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
633}
634
635
636static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
637{
638 uint64_t slpte;
639
640 assert(index < VTD_SL_PT_ENTRY_NR);
641
642 if (dma_memory_read(&address_space_memory,
643 base_addr + index * sizeof(slpte), &slpte,
644 sizeof(slpte))) {
645 slpte = (uint64_t)-1;
646 return slpte;
647 }
648 slpte = le64_to_cpu(slpte);
649 return slpte;
650}
651
652
653
654
655static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
656{
657 return (iova >> vtd_slpt_level_shift(level)) &
658 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
659}
660
661
662static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
663{
664 return VTD_CAP_SAGAW_MASK & s->cap &
665 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
666}
667
668
669static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
670 VTDPASIDEntry *pe)
671{
672 switch (VTD_PE_GET_TYPE(pe)) {
673 case VTD_SM_PASID_ENTRY_FLT:
674 case VTD_SM_PASID_ENTRY_SLT:
675 case VTD_SM_PASID_ENTRY_NESTED:
676 break;
677 case VTD_SM_PASID_ENTRY_PT:
678 if (!x86_iommu->pt_supported) {
679 return false;
680 }
681 break;
682 default:
683
684 return false;
685 }
686 return true;
687}
688
689static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
690{
691 return pdire->val & 1;
692}
693
694
695
696
697
698static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,
699 uint32_t pasid,
700 VTDPASIDDirEntry *pdire)
701{
702 uint32_t index;
703 dma_addr_t addr, entry_size;
704
705 index = VTD_PASID_DIR_INDEX(pasid);
706 entry_size = VTD_PASID_DIR_ENTRY_SIZE;
707 addr = pasid_dir_base + index * entry_size;
708 if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) {
709 return -VTD_FR_PASID_TABLE_INV;
710 }
711
712 return 0;
713}
714
715static inline bool vtd_pe_present(VTDPASIDEntry *pe)
716{
717 return pe->val[0] & VTD_PASID_ENTRY_P;
718}
719
720static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
721 uint32_t pasid,
722 dma_addr_t addr,
723 VTDPASIDEntry *pe)
724{
725 uint32_t index;
726 dma_addr_t entry_size;
727 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
728
729 index = VTD_PASID_TABLE_INDEX(pasid);
730 entry_size = VTD_PASID_ENTRY_SIZE;
731 addr = addr + index * entry_size;
732 if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) {
733 return -VTD_FR_PASID_TABLE_INV;
734 }
735
736
737 if (!vtd_pe_type_check(x86_iommu, pe)) {
738 return -VTD_FR_PASID_TABLE_INV;
739 }
740
741 if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
742 return -VTD_FR_PASID_TABLE_INV;
743 }
744
745 return 0;
746}
747
748
749
750
751
752static int vtd_get_pe_from_pdire(IntelIOMMUState *s,
753 uint32_t pasid,
754 VTDPASIDDirEntry *pdire,
755 VTDPASIDEntry *pe)
756{
757 dma_addr_t addr = pdire->val & VTD_PASID_TABLE_BASE_ADDR_MASK;
758
759 return vtd_get_pe_in_pasid_leaf_table(s, pasid, addr, pe);
760}
761
762
763
764
765
766
767
768static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
769 dma_addr_t pasid_dir_base,
770 uint32_t pasid,
771 VTDPASIDEntry *pe)
772{
773 int ret;
774 VTDPASIDDirEntry pdire;
775
776 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base,
777 pasid, &pdire);
778 if (ret) {
779 return ret;
780 }
781
782 if (!vtd_pdire_present(&pdire)) {
783 return -VTD_FR_PASID_TABLE_INV;
784 }
785
786 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe);
787 if (ret) {
788 return ret;
789 }
790
791 if (!vtd_pe_present(pe)) {
792 return -VTD_FR_PASID_TABLE_INV;
793 }
794
795 return 0;
796}
797
798static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s,
799 VTDContextEntry *ce,
800 VTDPASIDEntry *pe)
801{
802 uint32_t pasid;
803 dma_addr_t pasid_dir_base;
804 int ret = 0;
805
806 pasid = VTD_CE_GET_RID2PASID(ce);
807 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
808 ret = vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe);
809
810 return ret;
811}
812
813static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,
814 VTDContextEntry *ce,
815 bool *pe_fpd_set)
816{
817 int ret;
818 uint32_t pasid;
819 dma_addr_t pasid_dir_base;
820 VTDPASIDDirEntry pdire;
821 VTDPASIDEntry pe;
822
823 pasid = VTD_CE_GET_RID2PASID(ce);
824 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
825
826
827
828
829
830 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, pasid, &pdire);
831 if (ret) {
832 return ret;
833 }
834
835 if (pdire.val & VTD_PASID_DIR_FPD) {
836 *pe_fpd_set = true;
837 return 0;
838 }
839
840 if (!vtd_pdire_present(&pdire)) {
841 return -VTD_FR_PASID_TABLE_INV;
842 }
843
844
845
846
847
848 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, &pe);
849 if (ret) {
850 return ret;
851 }
852
853 if (pe.val[0] & VTD_PASID_ENTRY_FPD) {
854 *pe_fpd_set = true;
855 }
856
857 return 0;
858}
859
860
861
862
863static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
864{
865 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
866}
867
868static uint32_t vtd_get_iova_level(IntelIOMMUState *s,
869 VTDContextEntry *ce)
870{
871 VTDPASIDEntry pe;
872
873 if (s->root_scalable) {
874 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
875 return VTD_PE_GET_LEVEL(&pe);
876 }
877
878 return vtd_ce_get_level(ce);
879}
880
881static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
882{
883 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
884}
885
886static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s,
887 VTDContextEntry *ce)
888{
889 VTDPASIDEntry pe;
890
891 if (s->root_scalable) {
892 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
893 return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9;
894 }
895
896 return vtd_ce_get_agaw(ce);
897}
898
899static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
900{
901 return ce->lo & VTD_CONTEXT_ENTRY_TT;
902}
903
904
905static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
906 VTDContextEntry *ce)
907{
908 switch (vtd_ce_get_type(ce)) {
909 case VTD_CONTEXT_TT_MULTI_LEVEL:
910
911 break;
912 case VTD_CONTEXT_TT_DEV_IOTLB:
913 if (!x86_iommu->dt_supported) {
914 error_report_once("%s: DT specified but not supported", __func__);
915 return false;
916 }
917 break;
918 case VTD_CONTEXT_TT_PASS_THROUGH:
919 if (!x86_iommu->pt_supported) {
920 error_report_once("%s: PT specified but not supported", __func__);
921 return false;
922 }
923 break;
924 default:
925
926 error_report_once("%s: unknown ce type: %"PRIu32, __func__,
927 vtd_ce_get_type(ce));
928 return false;
929 }
930 return true;
931}
932
933static inline uint64_t vtd_iova_limit(IntelIOMMUState *s,
934 VTDContextEntry *ce, uint8_t aw)
935{
936 uint32_t ce_agaw = vtd_get_iova_agaw(s, ce);
937 return 1ULL << MIN(ce_agaw, aw);
938}
939
940
941static inline bool vtd_iova_range_check(IntelIOMMUState *s,
942 uint64_t iova, VTDContextEntry *ce,
943 uint8_t aw)
944{
945
946
947
948
949 return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1));
950}
951
952static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
953 VTDContextEntry *ce)
954{
955 VTDPASIDEntry pe;
956
957 if (s->root_scalable) {
958 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
959 return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR;
960 }
961
962 return vtd_ce_get_slpt_base(ce);
963}
964
965
966
967
968
969
970static uint64_t vtd_spte_rsvd[5];
971static uint64_t vtd_spte_rsvd_large[5];
972
973static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
974{
975 uint64_t rsvd_mask = vtd_spte_rsvd[level];
976
977 if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
978 (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
979
980 rsvd_mask = vtd_spte_rsvd_large[level];
981 }
982
983 return slpte & rsvd_mask;
984}
985
986
987static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
988{
989 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
990 if (!vtd_bus) {
991
992
993
994
995
996 GHashTableIter iter;
997
998 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
999 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
1000 if (pci_bus_num(vtd_bus->bus) == bus_num) {
1001 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
1002 return vtd_bus;
1003 }
1004 }
1005 vtd_bus = NULL;
1006 }
1007 return vtd_bus;
1008}
1009
1010
1011
1012
1013static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
1014 uint64_t iova, bool is_write,
1015 uint64_t *slptep, uint32_t *slpte_level,
1016 bool *reads, bool *writes, uint8_t aw_bits)
1017{
1018 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce);
1019 uint32_t level = vtd_get_iova_level(s, ce);
1020 uint32_t offset;
1021 uint64_t slpte;
1022 uint64_t access_right_check;
1023
1024 if (!vtd_iova_range_check(s, iova, ce, aw_bits)) {
1025 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")",
1026 __func__, iova);
1027 return -VTD_FR_ADDR_BEYOND_MGAW;
1028 }
1029
1030
1031 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
1032
1033 while (true) {
1034 offset = vtd_iova_level_offset(iova, level);
1035 slpte = vtd_get_slpte(addr, offset);
1036
1037 if (slpte == (uint64_t)-1) {
1038 error_report_once("%s: detected read error on DMAR slpte "
1039 "(iova=0x%" PRIx64 ")", __func__, iova);
1040 if (level == vtd_get_iova_level(s, ce)) {
1041
1042 return -VTD_FR_CONTEXT_ENTRY_INV;
1043 } else {
1044 return -VTD_FR_PAGING_ENTRY_INV;
1045 }
1046 }
1047 *reads = (*reads) && (slpte & VTD_SL_R);
1048 *writes = (*writes) && (slpte & VTD_SL_W);
1049 if (!(slpte & access_right_check)) {
1050 error_report_once("%s: detected slpte permission error "
1051 "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", "
1052 "slpte=0x%" PRIx64 ", write=%d)", __func__,
1053 iova, level, slpte, is_write);
1054 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
1055 }
1056 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
1057 error_report_once("%s: detected splte reserve non-zero "
1058 "iova=0x%" PRIx64 ", level=0x%" PRIx32
1059 "slpte=0x%" PRIx64 ")", __func__, iova,
1060 level, slpte);
1061 return -VTD_FR_PAGING_ENTRY_RSVD;
1062 }
1063
1064 if (vtd_is_last_slpte(slpte, level)) {
1065 *slptep = slpte;
1066 *slpte_level = level;
1067 return 0;
1068 }
1069 addr = vtd_get_slpte_addr(slpte, aw_bits);
1070 level--;
1071 }
1072}
1073
1074typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086typedef struct {
1087 VTDAddressSpace *as;
1088 vtd_page_walk_hook hook_fn;
1089 void *private;
1090 bool notify_unmap;
1091 uint8_t aw;
1092 uint16_t domain_id;
1093} vtd_page_walk_info;
1094
1095static int vtd_page_walk_one(IOMMUTLBEntry *entry, vtd_page_walk_info *info)
1096{
1097 VTDAddressSpace *as = info->as;
1098 vtd_page_walk_hook hook_fn = info->hook_fn;
1099 void *private = info->private;
1100 DMAMap target = {
1101 .iova = entry->iova,
1102 .size = entry->addr_mask,
1103 .translated_addr = entry->translated_addr,
1104 .perm = entry->perm,
1105 };
1106 DMAMap *mapped = iova_tree_find(as->iova_tree, &target);
1107
1108 if (entry->perm == IOMMU_NONE && !info->notify_unmap) {
1109 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask);
1110 return 0;
1111 }
1112
1113 assert(hook_fn);
1114
1115
1116 if (entry->perm) {
1117 if (mapped) {
1118
1119 if (!memcmp(mapped, &target, sizeof(target))) {
1120 trace_vtd_page_walk_one_skip_map(entry->iova, entry->addr_mask,
1121 entry->translated_addr);
1122 return 0;
1123 } else {
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138 IOMMUAccessFlags cache_perm = entry->perm;
1139 int ret;
1140
1141
1142 entry->perm = IOMMU_NONE;
1143 trace_vtd_page_walk_one(info->domain_id,
1144 entry->iova,
1145 entry->translated_addr,
1146 entry->addr_mask,
1147 entry->perm);
1148 ret = hook_fn(entry, private);
1149 if (ret) {
1150 return ret;
1151 }
1152
1153 iova_tree_remove(as->iova_tree, &target);
1154
1155 entry->perm = cache_perm;
1156 }
1157 }
1158 iova_tree_insert(as->iova_tree, &target);
1159 } else {
1160 if (!mapped) {
1161
1162 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask);
1163 return 0;
1164 }
1165 iova_tree_remove(as->iova_tree, &target);
1166 }
1167
1168 trace_vtd_page_walk_one(info->domain_id, entry->iova,
1169 entry->translated_addr, entry->addr_mask,
1170 entry->perm);
1171 return hook_fn(entry, private);
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
1185 uint64_t end, uint32_t level, bool read,
1186 bool write, vtd_page_walk_info *info)
1187{
1188 bool read_cur, write_cur, entry_valid;
1189 uint32_t offset;
1190 uint64_t slpte;
1191 uint64_t subpage_size, subpage_mask;
1192 IOMMUTLBEntry entry;
1193 uint64_t iova = start;
1194 uint64_t iova_next;
1195 int ret = 0;
1196
1197 trace_vtd_page_walk_level(addr, level, start, end);
1198
1199 subpage_size = 1ULL << vtd_slpt_level_shift(level);
1200 subpage_mask = vtd_slpt_level_page_mask(level);
1201
1202 while (iova < end) {
1203 iova_next = (iova & subpage_mask) + subpage_size;
1204
1205 offset = vtd_iova_level_offset(iova, level);
1206 slpte = vtd_get_slpte(addr, offset);
1207
1208 if (slpte == (uint64_t)-1) {
1209 trace_vtd_page_walk_skip_read(iova, iova_next);
1210 goto next;
1211 }
1212
1213 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
1214 trace_vtd_page_walk_skip_reserve(iova, iova_next);
1215 goto next;
1216 }
1217
1218
1219 read_cur = read && (slpte & VTD_SL_R);
1220 write_cur = write && (slpte & VTD_SL_W);
1221
1222
1223
1224
1225
1226
1227 entry_valid = read_cur | write_cur;
1228
1229 if (!vtd_is_last_slpte(slpte, level) && entry_valid) {
1230
1231
1232
1233
1234 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
1235 iova, MIN(iova_next, end), level - 1,
1236 read_cur, write_cur, info);
1237 } else {
1238
1239
1240
1241
1242
1243
1244
1245
1246 entry.target_as = &address_space_memory;
1247 entry.iova = iova & subpage_mask;
1248 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
1249 entry.addr_mask = ~subpage_mask;
1250
1251 entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
1252 ret = vtd_page_walk_one(&entry, info);
1253 }
1254
1255 if (ret < 0) {
1256 return ret;
1257 }
1258
1259next:
1260 iova = iova_next;
1261 }
1262
1263 return 0;
1264}
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce,
1276 uint64_t start, uint64_t end,
1277 vtd_page_walk_info *info)
1278{
1279 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce);
1280 uint32_t level = vtd_get_iova_level(s, ce);
1281
1282 if (!vtd_iova_range_check(s, start, ce, info->aw)) {
1283 return -VTD_FR_ADDR_BEYOND_MGAW;
1284 }
1285
1286 if (!vtd_iova_range_check(s, end, ce, info->aw)) {
1287
1288 end = vtd_iova_limit(s, ce, info->aw);
1289 }
1290
1291 return vtd_page_walk_level(addr, start, end, level, true, true, info);
1292}
1293
1294static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState *s,
1295 VTDRootEntry *re)
1296{
1297
1298 if (!s->root_scalable &&
1299 (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits))))
1300 goto rsvd_err;
1301
1302
1303 if (s->root_scalable &&
1304 ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) ||
1305 (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits))))
1306 goto rsvd_err;
1307
1308 return 0;
1309
1310rsvd_err:
1311 error_report_once("%s: invalid root entry: hi=0x%"PRIx64
1312 ", lo=0x%"PRIx64,
1313 __func__, re->hi, re->lo);
1314 return -VTD_FR_ROOT_ENTRY_RSVD;
1315}
1316
1317static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState *s,
1318 VTDContextEntry *ce)
1319{
1320 if (!s->root_scalable &&
1321 (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI ||
1322 ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) {
1323 error_report_once("%s: invalid context entry: hi=%"PRIx64
1324 ", lo=%"PRIx64" (reserved nonzero)",
1325 __func__, ce->hi, ce->lo);
1326 return -VTD_FR_CONTEXT_ENTRY_RSVD;
1327 }
1328
1329 if (s->root_scalable &&
1330 (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) ||
1331 ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 ||
1332 ce->val[2] ||
1333 ce->val[3])) {
1334 error_report_once("%s: invalid context entry: val[3]=%"PRIx64
1335 ", val[2]=%"PRIx64
1336 ", val[1]=%"PRIx64
1337 ", val[0]=%"PRIx64" (reserved nonzero)",
1338 __func__, ce->val[3], ce->val[2],
1339 ce->val[1], ce->val[0]);
1340 return -VTD_FR_CONTEXT_ENTRY_RSVD;
1341 }
1342
1343 return 0;
1344}
1345
1346static int vtd_ce_rid2pasid_check(IntelIOMMUState *s,
1347 VTDContextEntry *ce)
1348{
1349 VTDPASIDEntry pe;
1350
1351
1352
1353
1354
1355
1356 return vtd_ce_get_rid2pasid_entry(s, ce, &pe);
1357}
1358
1359
1360static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
1361 uint8_t devfn, VTDContextEntry *ce)
1362{
1363 VTDRootEntry re;
1364 int ret_fr;
1365 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1366
1367 ret_fr = vtd_get_root_entry(s, bus_num, &re);
1368 if (ret_fr) {
1369 return ret_fr;
1370 }
1371
1372 if (!vtd_root_entry_present(s, &re, devfn)) {
1373
1374 trace_vtd_re_not_present(bus_num);
1375 return -VTD_FR_ROOT_ENTRY_P;
1376 }
1377
1378 ret_fr = vtd_root_entry_rsvd_bits_check(s, &re);
1379 if (ret_fr) {
1380 return ret_fr;
1381 }
1382
1383 ret_fr = vtd_get_context_entry_from_root(s, &re, devfn, ce);
1384 if (ret_fr) {
1385 return ret_fr;
1386 }
1387
1388 if (!vtd_ce_present(ce)) {
1389
1390 trace_vtd_ce_not_present(bus_num, devfn);
1391 return -VTD_FR_CONTEXT_ENTRY_P;
1392 }
1393
1394 ret_fr = vtd_context_entry_rsvd_bits_check(s, ce);
1395 if (ret_fr) {
1396 return ret_fr;
1397 }
1398
1399
1400 if (!s->root_scalable &&
1401 !vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
1402 error_report_once("%s: invalid context entry: hi=%"PRIx64
1403 ", lo=%"PRIx64" (level %d not supported)",
1404 __func__, ce->hi, ce->lo,
1405 vtd_ce_get_level(ce));
1406 return -VTD_FR_CONTEXT_ENTRY_INV;
1407 }
1408
1409 if (!s->root_scalable) {
1410
1411 if (!vtd_ce_type_check(x86_iommu, ce)) {
1412
1413 return -VTD_FR_CONTEXT_ENTRY_INV;
1414 }
1415 } else {
1416
1417
1418
1419
1420
1421
1422 ret_fr = vtd_ce_rid2pasid_check(s, ce);
1423 if (ret_fr) {
1424 return ret_fr;
1425 }
1426 }
1427
1428 return 0;
1429}
1430
1431static int vtd_sync_shadow_page_hook(IOMMUTLBEntry *entry,
1432 void *private)
1433{
1434 memory_region_notify_iommu((IOMMUMemoryRegion *)private, 0, *entry);
1435 return 0;
1436}
1437
1438static uint16_t vtd_get_domain_id(IntelIOMMUState *s,
1439 VTDContextEntry *ce)
1440{
1441 VTDPASIDEntry pe;
1442
1443 if (s->root_scalable) {
1444 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
1445 return VTD_SM_PASID_ENTRY_DID(pe.val[1]);
1446 }
1447
1448 return VTD_CONTEXT_ENTRY_DID(ce->hi);
1449}
1450
1451static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as,
1452 VTDContextEntry *ce,
1453 hwaddr addr, hwaddr size)
1454{
1455 IntelIOMMUState *s = vtd_as->iommu_state;
1456 vtd_page_walk_info info = {
1457 .hook_fn = vtd_sync_shadow_page_hook,
1458 .private = (void *)&vtd_as->iommu,
1459 .notify_unmap = true,
1460 .aw = s->aw_bits,
1461 .as = vtd_as,
1462 .domain_id = vtd_get_domain_id(s, ce),
1463 };
1464
1465 return vtd_page_walk(s, ce, addr, addr + size, &info);
1466}
1467
1468static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as)
1469{
1470 int ret;
1471 VTDContextEntry ce;
1472 IOMMUNotifier *n;
1473
1474 ret = vtd_dev_to_context_entry(vtd_as->iommu_state,
1475 pci_bus_num(vtd_as->bus),
1476 vtd_as->devfn, &ce);
1477 if (ret) {
1478 if (ret == -VTD_FR_CONTEXT_ENTRY_P) {
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
1489 vtd_address_space_unmap(vtd_as, n);
1490 }
1491 ret = 0;
1492 }
1493 return ret;
1494 }
1495
1496 return vtd_sync_shadow_page_table_range(vtd_as, &ce, 0, UINT64_MAX);
1497}
1498
1499
1500
1501
1502
1503
1504
1505static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
1506{
1507 IntelIOMMUState *s;
1508 VTDContextEntry ce;
1509 VTDPASIDEntry pe;
1510 int ret;
1511
1512 assert(as);
1513
1514 s = as->iommu_state;
1515 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
1516 as->devfn, &ce);
1517 if (ret) {
1518
1519
1520
1521
1522
1523
1524 return false;
1525 }
1526
1527 if (s->root_scalable) {
1528 ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe);
1529 if (ret) {
1530 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32,
1531 __func__, ret);
1532 return false;
1533 }
1534 return (VTD_PE_GET_TYPE(&pe) == VTD_SM_PASID_ENTRY_PT);
1535 }
1536
1537 return (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH);
1538}
1539
1540
1541static bool vtd_switch_address_space(VTDAddressSpace *as)
1542{
1543 bool use_iommu;
1544
1545 bool take_bql = !qemu_mutex_iothread_locked();
1546
1547 assert(as);
1548
1549 use_iommu = as->iommu_state->dmar_enabled && !vtd_dev_pt_enabled(as);
1550
1551 trace_vtd_switch_address_space(pci_bus_num(as->bus),
1552 VTD_PCI_SLOT(as->devfn),
1553 VTD_PCI_FUNC(as->devfn),
1554 use_iommu);
1555
1556
1557
1558
1559
1560
1561 if (take_bql) {
1562 qemu_mutex_lock_iothread();
1563 }
1564
1565
1566 if (use_iommu) {
1567 memory_region_set_enabled(&as->nodmar, false);
1568 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true);
1569 } else {
1570 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false);
1571 memory_region_set_enabled(&as->nodmar, true);
1572 }
1573
1574 if (take_bql) {
1575 qemu_mutex_unlock_iothread();
1576 }
1577
1578 return use_iommu;
1579}
1580
1581static void vtd_switch_address_space_all(IntelIOMMUState *s)
1582{
1583 GHashTableIter iter;
1584 VTDBus *vtd_bus;
1585 int i;
1586
1587 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1588 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
1589 for (i = 0; i < PCI_DEVFN_MAX; i++) {
1590 if (!vtd_bus->dev_as[i]) {
1591 continue;
1592 }
1593 vtd_switch_address_space(vtd_bus->dev_as[i]);
1594 }
1595 }
1596}
1597
1598static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
1599{
1600 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
1601}
1602
1603static const bool vtd_qualified_faults[] = {
1604 [VTD_FR_RESERVED] = false,
1605 [VTD_FR_ROOT_ENTRY_P] = false,
1606 [VTD_FR_CONTEXT_ENTRY_P] = true,
1607 [VTD_FR_CONTEXT_ENTRY_INV] = true,
1608 [VTD_FR_ADDR_BEYOND_MGAW] = true,
1609 [VTD_FR_WRITE] = true,
1610 [VTD_FR_READ] = true,
1611 [VTD_FR_PAGING_ENTRY_INV] = true,
1612 [VTD_FR_ROOT_TABLE_INV] = false,
1613 [VTD_FR_CONTEXT_TABLE_INV] = false,
1614 [VTD_FR_ROOT_ENTRY_RSVD] = false,
1615 [VTD_FR_PAGING_ENTRY_RSVD] = true,
1616 [VTD_FR_CONTEXT_ENTRY_TT] = true,
1617 [VTD_FR_PASID_TABLE_INV] = false,
1618 [VTD_FR_RESERVED_ERR] = false,
1619 [VTD_FR_MAX] = false,
1620};
1621
1622
1623
1624
1625
1626static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
1627{
1628 return vtd_qualified_faults[fault];
1629}
1630
1631static inline bool vtd_is_interrupt_addr(hwaddr addr)
1632{
1633 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
1634}
1635
1636static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
1637{
1638 VTDBus *vtd_bus;
1639 VTDAddressSpace *vtd_as;
1640 bool success = false;
1641
1642 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1643 if (!vtd_bus) {
1644 goto out;
1645 }
1646
1647 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
1648 if (!vtd_as) {
1649 goto out;
1650 }
1651
1652 if (vtd_switch_address_space(vtd_as) == false) {
1653
1654 success = true;
1655 }
1656
1657out:
1658 trace_vtd_pt_enable_fast_path(source_id, success);
1659}
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1674 uint8_t devfn, hwaddr addr, bool is_write,
1675 IOMMUTLBEntry *entry)
1676{
1677 IntelIOMMUState *s = vtd_as->iommu_state;
1678 VTDContextEntry ce;
1679 uint8_t bus_num = pci_bus_num(bus);
1680 VTDContextCacheEntry *cc_entry;
1681 uint64_t slpte, page_mask;
1682 uint32_t level;
1683 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
1684 int ret_fr;
1685 bool is_fpd_set = false;
1686 bool reads = true;
1687 bool writes = true;
1688 uint8_t access_flags;
1689 VTDIOTLBEntry *iotlb_entry;
1690
1691
1692
1693
1694
1695 assert(!vtd_is_interrupt_addr(addr));
1696
1697 vtd_iommu_lock(s);
1698
1699 cc_entry = &vtd_as->context_cache_entry;
1700
1701
1702 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
1703 if (iotlb_entry) {
1704 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
1705 iotlb_entry->domain_id);
1706 slpte = iotlb_entry->slpte;
1707 access_flags = iotlb_entry->access_flags;
1708 page_mask = iotlb_entry->mask;
1709 goto out;
1710 }
1711
1712
1713 if (cc_entry->context_cache_gen == s->context_cache_gen) {
1714 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
1715 cc_entry->context_entry.lo,
1716 cc_entry->context_cache_gen);
1717 ce = cc_entry->context_entry;
1718 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1719 if (!is_fpd_set && s->root_scalable) {
1720 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set);
1721 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1722 }
1723 } else {
1724 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
1725 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1726 if (!ret_fr && !is_fpd_set && s->root_scalable) {
1727 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set);
1728 }
1729 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1730
1731 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1732 cc_entry->context_cache_gen,
1733 s->context_cache_gen);
1734 cc_entry->context_entry = ce;
1735 cc_entry->context_cache_gen = s->context_cache_gen;
1736 }
1737
1738
1739
1740
1741
1742 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
1743 entry->iova = addr & VTD_PAGE_MASK_4K;
1744 entry->translated_addr = entry->iova;
1745 entry->addr_mask = ~VTD_PAGE_MASK_4K;
1746 entry->perm = IOMMU_RW;
1747 trace_vtd_translate_pt(source_id, entry->iova);
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758 vtd_pt_enable_fast_path(s, source_id);
1759 vtd_iommu_unlock(s);
1760 return true;
1761 }
1762
1763 ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level,
1764 &reads, &writes, s->aw_bits);
1765 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1766
1767 page_mask = vtd_slpt_level_page_mask(level);
1768 access_flags = IOMMU_ACCESS_FLAG(reads, writes);
1769 vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte,
1770 access_flags, level);
1771out:
1772 vtd_iommu_unlock(s);
1773 entry->iova = addr & page_mask;
1774 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
1775 entry->addr_mask = ~page_mask;
1776 entry->perm = access_flags;
1777 return true;
1778
1779error:
1780 vtd_iommu_unlock(s);
1781 entry->iova = 0;
1782 entry->translated_addr = 0;
1783 entry->addr_mask = 0;
1784 entry->perm = IOMMU_NONE;
1785 return false;
1786}
1787
1788static void vtd_root_table_setup(IntelIOMMUState *s)
1789{
1790 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1791 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits);
1792
1793 vtd_update_scalable_state(s);
1794
1795 trace_vtd_reg_dmar_root(s->root, s->root_scalable);
1796}
1797
1798static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1799 uint32_t index, uint32_t mask)
1800{
1801 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1802}
1803
1804static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1805{
1806 uint64_t value = 0;
1807 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1808 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
1809 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits);
1810 s->intr_eime = value & VTD_IRTA_EIME;
1811
1812
1813 vtd_iec_notify_all(s, true, 0, 0);
1814
1815 trace_vtd_reg_ir_root(s->intr_root, s->intr_size);
1816}
1817
1818static void vtd_iommu_replay_all(IntelIOMMUState *s)
1819{
1820 VTDAddressSpace *vtd_as;
1821
1822 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
1823 vtd_sync_shadow_page_table(vtd_as);
1824 }
1825}
1826
1827static void vtd_context_global_invalidate(IntelIOMMUState *s)
1828{
1829 trace_vtd_inv_desc_cc_global();
1830
1831 vtd_iommu_lock(s);
1832 s->context_cache_gen++;
1833 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1834 vtd_reset_context_cache_locked(s);
1835 }
1836 vtd_iommu_unlock(s);
1837 vtd_address_space_refresh_all(s);
1838
1839
1840
1841
1842
1843
1844
1845 vtd_iommu_replay_all(s);
1846}
1847
1848
1849
1850
1851static void vtd_context_device_invalidate(IntelIOMMUState *s,
1852 uint16_t source_id,
1853 uint16_t func_mask)
1854{
1855 uint16_t mask;
1856 VTDBus *vtd_bus;
1857 VTDAddressSpace *vtd_as;
1858 uint8_t bus_n, devfn;
1859 uint16_t devfn_it;
1860
1861 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1862
1863 switch (func_mask & 3) {
1864 case 0:
1865 mask = 0;
1866 break;
1867 case 1:
1868 mask = 4;
1869 break;
1870 case 2:
1871 mask = 6;
1872 break;
1873 case 3:
1874 mask = 7;
1875 break;
1876 }
1877 mask = ~mask;
1878
1879 bus_n = VTD_SID_TO_BUS(source_id);
1880 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
1881 if (vtd_bus) {
1882 devfn = VTD_SID_TO_DEVFN(source_id);
1883 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
1884 vtd_as = vtd_bus->dev_as[devfn_it];
1885 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
1886 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1887 VTD_PCI_FUNC(devfn_it));
1888 vtd_iommu_lock(s);
1889 vtd_as->context_cache_entry.context_cache_gen = 0;
1890 vtd_iommu_unlock(s);
1891
1892
1893
1894
1895 vtd_switch_address_space(vtd_as);
1896
1897
1898
1899
1900
1901
1902
1903
1904 vtd_sync_shadow_page_table(vtd_as);
1905 }
1906 }
1907 }
1908}
1909
1910
1911
1912
1913
1914static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1915{
1916 uint64_t caig;
1917 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1918
1919 switch (type) {
1920 case VTD_CCMD_DOMAIN_INVL:
1921
1922 case VTD_CCMD_GLOBAL_INVL:
1923 caig = VTD_CCMD_GLOBAL_INVL_A;
1924 vtd_context_global_invalidate(s);
1925 break;
1926
1927 case VTD_CCMD_DEVICE_INVL:
1928 caig = VTD_CCMD_DEVICE_INVL_A;
1929 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1930 break;
1931
1932 default:
1933 error_report_once("%s: invalid context: 0x%" PRIx64,
1934 __func__, val);
1935 caig = 0;
1936 }
1937 return caig;
1938}
1939
1940static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1941{
1942 trace_vtd_inv_desc_iotlb_global();
1943 vtd_reset_iotlb(s);
1944 vtd_iommu_replay_all(s);
1945}
1946
1947static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1948{
1949 VTDContextEntry ce;
1950 VTDAddressSpace *vtd_as;
1951
1952 trace_vtd_inv_desc_iotlb_domain(domain_id);
1953
1954 vtd_iommu_lock(s);
1955 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1956 &domain_id);
1957 vtd_iommu_unlock(s);
1958
1959 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
1960 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1961 vtd_as->devfn, &ce) &&
1962 domain_id == vtd_get_domain_id(s, &ce)) {
1963 vtd_sync_shadow_page_table(vtd_as);
1964 }
1965 }
1966}
1967
1968static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1969 uint16_t domain_id, hwaddr addr,
1970 uint8_t am)
1971{
1972 VTDAddressSpace *vtd_as;
1973 VTDContextEntry ce;
1974 int ret;
1975 hwaddr size = (1 << am) * VTD_PAGE_SIZE;
1976
1977 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
1978 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1979 vtd_as->devfn, &ce);
1980 if (!ret && domain_id == vtd_get_domain_id(s, &ce)) {
1981 if (vtd_as_has_map_notifier(vtd_as)) {
1982
1983
1984
1985
1986
1987 vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
1988 } else {
1989
1990
1991
1992
1993
1994 IOMMUTLBEntry entry = {
1995 .target_as = &address_space_memory,
1996 .iova = addr,
1997 .translated_addr = 0,
1998 .addr_mask = size - 1,
1999 .perm = IOMMU_NONE,
2000 };
2001 memory_region_notify_iommu(&vtd_as->iommu, 0, entry);
2002 }
2003 }
2004 }
2005}
2006
2007static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
2008 hwaddr addr, uint8_t am)
2009{
2010 VTDIOTLBPageInvInfo info;
2011
2012 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
2013
2014 assert(am <= VTD_MAMV);
2015 info.domain_id = domain_id;
2016 info.addr = addr;
2017 info.mask = ~((1 << am) - 1);
2018 vtd_iommu_lock(s);
2019 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
2020 vtd_iommu_unlock(s);
2021 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
2022}
2023
2024
2025
2026
2027
2028static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
2029{
2030 uint64_t iaig;
2031 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
2032 uint16_t domain_id;
2033 hwaddr addr;
2034 uint8_t am;
2035
2036 switch (type) {
2037 case VTD_TLB_GLOBAL_FLUSH:
2038 iaig = VTD_TLB_GLOBAL_FLUSH_A;
2039 vtd_iotlb_global_invalidate(s);
2040 break;
2041
2042 case VTD_TLB_DSI_FLUSH:
2043 domain_id = VTD_TLB_DID(val);
2044 iaig = VTD_TLB_DSI_FLUSH_A;
2045 vtd_iotlb_domain_invalidate(s, domain_id);
2046 break;
2047
2048 case VTD_TLB_PSI_FLUSH:
2049 domain_id = VTD_TLB_DID(val);
2050 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
2051 am = VTD_IVA_AM(addr);
2052 addr = VTD_IVA_ADDR(addr);
2053 if (am > VTD_MAMV) {
2054 error_report_once("%s: address mask overflow: 0x%" PRIx64,
2055 __func__, vtd_get_quad_raw(s, DMAR_IVA_REG));
2056 iaig = 0;
2057 break;
2058 }
2059 iaig = VTD_TLB_PSI_FLUSH_A;
2060 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
2061 break;
2062
2063 default:
2064 error_report_once("%s: invalid granularity: 0x%" PRIx64,
2065 __func__, val);
2066 iaig = 0;
2067 }
2068 return iaig;
2069}
2070
2071static void vtd_fetch_inv_desc(IntelIOMMUState *s);
2072
2073static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
2074{
2075 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
2076 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
2077}
2078
2079static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
2080{
2081 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
2082
2083 trace_vtd_inv_qi_enable(en);
2084
2085 if (en) {
2086 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits);
2087
2088 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 : 0));
2089 s->qi_enabled = true;
2090 trace_vtd_inv_qi_setup(s->iq, s->iq_size);
2091
2092 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
2093
2094 if (s->iq_tail != 0) {
2095
2096
2097
2098
2099
2100 trace_vtd_warn_invalid_qi_tail(s->iq_tail);
2101 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
2102 vtd_fetch_inv_desc(s);
2103 }
2104 }
2105 } else {
2106 if (vtd_queued_inv_disable_check(s)) {
2107
2108 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
2109 s->iq_head = 0;
2110 s->qi_enabled = false;
2111
2112 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
2113 } else {
2114 error_report_once("%s: detected improper state when disable QI "
2115 "(head=0x%x, tail=0x%x, last_type=%d)",
2116 __func__,
2117 s->iq_head, s->iq_tail, s->iq_last_desc_type);
2118 }
2119 }
2120}
2121
2122
2123static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
2124{
2125 vtd_root_table_setup(s);
2126
2127 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
2128 vtd_reset_caches(s);
2129 vtd_address_space_refresh_all(s);
2130}
2131
2132
2133static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
2134{
2135 vtd_interrupt_remap_table_setup(s);
2136
2137 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
2138}
2139
2140
2141static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
2142{
2143 if (s->dmar_enabled == en) {
2144 return;
2145 }
2146
2147 trace_vtd_dmar_enable(en);
2148
2149 if (en) {
2150 s->dmar_enabled = true;
2151
2152 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
2153 } else {
2154 s->dmar_enabled = false;
2155
2156
2157 s->next_frcd_reg = 0;
2158
2159 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
2160 }
2161
2162 vtd_reset_caches(s);
2163 vtd_address_space_refresh_all(s);
2164}
2165
2166
2167static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
2168{
2169 trace_vtd_ir_enable(en);
2170
2171 if (en) {
2172 s->intr_enabled = true;
2173
2174 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
2175 } else {
2176 s->intr_enabled = false;
2177
2178 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
2179 }
2180}
2181
2182
2183static void vtd_handle_gcmd_write(IntelIOMMUState *s)
2184{
2185 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
2186 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
2187 uint32_t changed = status ^ val;
2188
2189 trace_vtd_reg_write_gcmd(status, val);
2190 if (changed & VTD_GCMD_TE) {
2191
2192 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
2193 }
2194 if (val & VTD_GCMD_SRTP) {
2195
2196 vtd_handle_gcmd_srtp(s);
2197 }
2198 if (changed & VTD_GCMD_QIE) {
2199
2200 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
2201 }
2202 if (val & VTD_GCMD_SIRTP) {
2203
2204 vtd_handle_gcmd_sirtp(s);
2205 }
2206 if (changed & VTD_GCMD_IRE) {
2207
2208 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
2209 }
2210}
2211
2212
2213static void vtd_handle_ccmd_write(IntelIOMMUState *s)
2214{
2215 uint64_t ret;
2216 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
2217
2218
2219 if (val & VTD_CCMD_ICC) {
2220 if (s->qi_enabled) {
2221 error_report_once("Queued Invalidation enabled, "
2222 "should not use register-based invalidation");
2223 return;
2224 }
2225 ret = vtd_context_cache_invalidate(s, val);
2226
2227 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
2228 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
2229 ret);
2230 }
2231}
2232
2233
2234static void vtd_handle_iotlb_write(IntelIOMMUState *s)
2235{
2236 uint64_t ret;
2237 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
2238
2239
2240 if (val & VTD_TLB_IVT) {
2241 if (s->qi_enabled) {
2242 error_report_once("Queued Invalidation enabled, "
2243 "should not use register-based invalidation");
2244 return;
2245 }
2246 ret = vtd_iotlb_flush(s, val);
2247
2248 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
2249 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
2250 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
2251 }
2252}
2253
2254
2255static bool vtd_get_inv_desc(IntelIOMMUState *s,
2256 VTDInvDesc *inv_desc)
2257{
2258 dma_addr_t base_addr = s->iq;
2259 uint32_t offset = s->iq_head;
2260 uint32_t dw = s->iq_dw ? 32 : 16;
2261 dma_addr_t addr = base_addr + offset * dw;
2262
2263 if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) {
2264 error_report_once("Read INV DESC failed.");
2265 return false;
2266 }
2267 inv_desc->lo = le64_to_cpu(inv_desc->lo);
2268 inv_desc->hi = le64_to_cpu(inv_desc->hi);
2269 if (dw == 32) {
2270 inv_desc->val[2] = le64_to_cpu(inv_desc->val[2]);
2271 inv_desc->val[3] = le64_to_cpu(inv_desc->val[3]);
2272 }
2273 return true;
2274}
2275
2276static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
2277{
2278 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
2279 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
2280 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64
2281 " (reserved nonzero)", __func__, inv_desc->hi,
2282 inv_desc->lo);
2283 return false;
2284 }
2285 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
2286
2287 uint32_t status_data = (uint32_t)(inv_desc->lo >>
2288 VTD_INV_DESC_WAIT_DATA_SHIFT);
2289
2290 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
2291
2292
2293 dma_addr_t status_addr = inv_desc->hi;
2294 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
2295 status_data = cpu_to_le32(status_data);
2296 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
2297 sizeof(status_data))) {
2298 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
2299 return false;
2300 }
2301 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
2302
2303 vtd_generate_completion_event(s);
2304 } else {
2305 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64
2306 " (unknown type)", __func__, inv_desc->hi,
2307 inv_desc->lo);
2308 return false;
2309 }
2310 return true;
2311}
2312
2313static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
2314 VTDInvDesc *inv_desc)
2315{
2316 uint16_t sid, fmask;
2317
2318 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
2319 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
2320 " (reserved nonzero)", __func__, inv_desc->hi,
2321 inv_desc->lo);
2322 return false;
2323 }
2324 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
2325 case VTD_INV_DESC_CC_DOMAIN:
2326 trace_vtd_inv_desc_cc_domain(
2327 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
2328
2329 case VTD_INV_DESC_CC_GLOBAL:
2330 vtd_context_global_invalidate(s);
2331 break;
2332
2333 case VTD_INV_DESC_CC_DEVICE:
2334 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
2335 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
2336 vtd_context_device_invalidate(s, sid, fmask);
2337 break;
2338
2339 default:
2340 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
2341 " (invalid type)", __func__, inv_desc->hi,
2342 inv_desc->lo);
2343 return false;
2344 }
2345 return true;
2346}
2347
2348static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
2349{
2350 uint16_t domain_id;
2351 uint8_t am;
2352 hwaddr addr;
2353
2354 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
2355 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
2356 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2357 ", lo=0x%"PRIx64" (reserved bits unzero)\n",
2358 __func__, inv_desc->hi, inv_desc->lo);
2359 return false;
2360 }
2361
2362 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
2363 case VTD_INV_DESC_IOTLB_GLOBAL:
2364 vtd_iotlb_global_invalidate(s);
2365 break;
2366
2367 case VTD_INV_DESC_IOTLB_DOMAIN:
2368 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
2369 vtd_iotlb_domain_invalidate(s, domain_id);
2370 break;
2371
2372 case VTD_INV_DESC_IOTLB_PAGE:
2373 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
2374 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
2375 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
2376 if (am > VTD_MAMV) {
2377 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2378 ", lo=0x%"PRIx64" (am=%u > VTD_MAMV=%u)\n",
2379 __func__, inv_desc->hi, inv_desc->lo,
2380 am, (unsigned)VTD_MAMV);
2381 return false;
2382 }
2383 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
2384 break;
2385
2386 default:
2387 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2388 ", lo=0x%"PRIx64" (type mismatch: 0x%llx)\n",
2389 __func__, inv_desc->hi, inv_desc->lo,
2390 inv_desc->lo & VTD_INV_DESC_IOTLB_G);
2391 return false;
2392 }
2393 return true;
2394}
2395
2396static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
2397 VTDInvDesc *inv_desc)
2398{
2399 trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
2400 inv_desc->iec.index,
2401 inv_desc->iec.index_mask);
2402
2403 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
2404 inv_desc->iec.index,
2405 inv_desc->iec.index_mask);
2406 return true;
2407}
2408
2409static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
2410 VTDInvDesc *inv_desc)
2411{
2412 VTDAddressSpace *vtd_dev_as;
2413 IOMMUTLBEntry entry;
2414 struct VTDBus *vtd_bus;
2415 hwaddr addr;
2416 uint64_t sz;
2417 uint16_t sid;
2418 uint8_t devfn;
2419 bool size;
2420 uint8_t bus_num;
2421
2422 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
2423 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
2424 devfn = sid & 0xff;
2425 bus_num = sid >> 8;
2426 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
2427
2428 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
2429 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
2430 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64
2431 ", lo=%"PRIx64" (reserved nonzero)", __func__,
2432 inv_desc->hi, inv_desc->lo);
2433 return false;
2434 }
2435
2436 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
2437 if (!vtd_bus) {
2438 goto done;
2439 }
2440
2441 vtd_dev_as = vtd_bus->dev_as[devfn];
2442 if (!vtd_dev_as) {
2443 goto done;
2444 }
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454 if (size) {
2455 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
2456 addr &= ~(sz - 1);
2457 } else {
2458 sz = VTD_PAGE_SIZE;
2459 }
2460
2461 entry.target_as = &vtd_dev_as->as;
2462 entry.addr_mask = sz - 1;
2463 entry.iova = addr;
2464 entry.perm = IOMMU_NONE;
2465 entry.translated_addr = 0;
2466 memory_region_notify_iommu(&vtd_dev_as->iommu, 0, entry);
2467
2468done:
2469 return true;
2470}
2471
2472static bool vtd_process_inv_desc(IntelIOMMUState *s)
2473{
2474 VTDInvDesc inv_desc;
2475 uint8_t desc_type;
2476
2477 trace_vtd_inv_qi_head(s->iq_head);
2478 if (!vtd_get_inv_desc(s, &inv_desc)) {
2479 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2480 return false;
2481 }
2482
2483 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
2484
2485 s->iq_last_desc_type = desc_type;
2486
2487 switch (desc_type) {
2488 case VTD_INV_DESC_CC:
2489 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
2490 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
2491 return false;
2492 }
2493 break;
2494
2495 case VTD_INV_DESC_IOTLB:
2496 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
2497 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
2498 return false;
2499 }
2500 break;
2501
2502
2503
2504
2505
2506
2507 case VTD_INV_DESC_PC:
2508 break;
2509
2510 case VTD_INV_DESC_PIOTLB:
2511 break;
2512
2513 case VTD_INV_DESC_WAIT:
2514 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
2515 if (!vtd_process_wait_desc(s, &inv_desc)) {
2516 return false;
2517 }
2518 break;
2519
2520 case VTD_INV_DESC_IEC:
2521 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
2522 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
2523 return false;
2524 }
2525 break;
2526
2527 case VTD_INV_DESC_DEVICE:
2528 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
2529 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
2530 return false;
2531 }
2532 break;
2533
2534 default:
2535 error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64
2536 " (unknown type)", __func__, inv_desc.hi,
2537 inv_desc.lo);
2538 return false;
2539 }
2540 s->iq_head++;
2541 if (s->iq_head == s->iq_size) {
2542 s->iq_head = 0;
2543 }
2544 return true;
2545}
2546
2547
2548static void vtd_fetch_inv_desc(IntelIOMMUState *s)
2549{
2550 trace_vtd_inv_qi_fetch();
2551
2552 if (s->iq_tail >= s->iq_size) {
2553
2554 error_report_once("%s: detected invalid QI tail "
2555 "(tail=0x%x, size=0x%x)",
2556 __func__, s->iq_tail, s->iq_size);
2557 vtd_handle_inv_queue_error(s);
2558 return;
2559 }
2560 while (s->iq_head != s->iq_tail) {
2561 if (!vtd_process_inv_desc(s)) {
2562
2563 vtd_handle_inv_queue_error(s);
2564 break;
2565 }
2566
2567 vtd_set_quad_raw(s, DMAR_IQH_REG,
2568 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
2569 VTD_IQH_QH_MASK);
2570 }
2571}
2572
2573
2574static void vtd_handle_iqt_write(IntelIOMMUState *s)
2575{
2576 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
2577
2578 if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) {
2579 error_report_once("%s: RSV bit is set: val=0x%"PRIx64,
2580 __func__, val);
2581 return;
2582 }
2583 s->iq_tail = VTD_IQT_QT(s->iq_dw, val);
2584 trace_vtd_inv_qi_tail(s->iq_tail);
2585
2586 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
2587
2588 vtd_fetch_inv_desc(s);
2589 }
2590}
2591
2592static void vtd_handle_fsts_write(IntelIOMMUState *s)
2593{
2594 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
2595 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
2596 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
2597
2598 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
2599 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
2600 trace_vtd_fsts_clear_ip();
2601 }
2602
2603
2604
2605}
2606
2607static void vtd_handle_fectl_write(IntelIOMMUState *s)
2608{
2609 uint32_t fectl_reg;
2610
2611
2612
2613
2614 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
2615
2616 trace_vtd_reg_write_fectl(fectl_reg);
2617
2618 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
2619 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
2620 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
2621 }
2622}
2623
2624static void vtd_handle_ics_write(IntelIOMMUState *s)
2625{
2626 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
2627 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
2628
2629 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
2630 trace_vtd_reg_ics_clear_ip();
2631 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
2632 }
2633}
2634
2635static void vtd_handle_iectl_write(IntelIOMMUState *s)
2636{
2637 uint32_t iectl_reg;
2638
2639
2640
2641
2642 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
2643
2644 trace_vtd_reg_write_iectl(iectl_reg);
2645
2646 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
2647 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
2648 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
2649 }
2650}
2651
2652static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
2653{
2654 IntelIOMMUState *s = opaque;
2655 uint64_t val;
2656
2657 trace_vtd_reg_read(addr, size);
2658
2659 if (addr + size > DMAR_REG_SIZE) {
2660 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2661 " size=0x%u", __func__, addr, size);
2662 return (uint64_t)-1;
2663 }
2664
2665 switch (addr) {
2666
2667 case DMAR_RTADDR_REG:
2668 if (size == 4) {
2669 val = s->root & ((1ULL << 32) - 1);
2670 } else {
2671 val = s->root;
2672 }
2673 break;
2674
2675 case DMAR_RTADDR_REG_HI:
2676 assert(size == 4);
2677 val = s->root >> 32;
2678 break;
2679
2680
2681 case DMAR_IQA_REG:
2682 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
2683 if (size == 4) {
2684 val = val & ((1ULL << 32) - 1);
2685 }
2686 break;
2687
2688 case DMAR_IQA_REG_HI:
2689 assert(size == 4);
2690 val = s->iq >> 32;
2691 break;
2692
2693 default:
2694 if (size == 4) {
2695 val = vtd_get_long(s, addr);
2696 } else {
2697 val = vtd_get_quad(s, addr);
2698 }
2699 }
2700
2701 return val;
2702}
2703
2704static void vtd_mem_write(void *opaque, hwaddr addr,
2705 uint64_t val, unsigned size)
2706{
2707 IntelIOMMUState *s = opaque;
2708
2709 trace_vtd_reg_write(addr, size, val);
2710
2711 if (addr + size > DMAR_REG_SIZE) {
2712 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2713 " size=0x%u", __func__, addr, size);
2714 return;
2715 }
2716
2717 switch (addr) {
2718
2719 case DMAR_GCMD_REG:
2720 vtd_set_long(s, addr, val);
2721 vtd_handle_gcmd_write(s);
2722 break;
2723
2724
2725 case DMAR_CCMD_REG:
2726 if (size == 4) {
2727 vtd_set_long(s, addr, val);
2728 } else {
2729 vtd_set_quad(s, addr, val);
2730 vtd_handle_ccmd_write(s);
2731 }
2732 break;
2733
2734 case DMAR_CCMD_REG_HI:
2735 assert(size == 4);
2736 vtd_set_long(s, addr, val);
2737 vtd_handle_ccmd_write(s);
2738 break;
2739
2740
2741 case DMAR_IOTLB_REG:
2742 if (size == 4) {
2743 vtd_set_long(s, addr, val);
2744 } else {
2745 vtd_set_quad(s, addr, val);
2746 vtd_handle_iotlb_write(s);
2747 }
2748 break;
2749
2750 case DMAR_IOTLB_REG_HI:
2751 assert(size == 4);
2752 vtd_set_long(s, addr, val);
2753 vtd_handle_iotlb_write(s);
2754 break;
2755
2756
2757 case DMAR_IVA_REG:
2758 if (size == 4) {
2759 vtd_set_long(s, addr, val);
2760 } else {
2761 vtd_set_quad(s, addr, val);
2762 }
2763 break;
2764
2765 case DMAR_IVA_REG_HI:
2766 assert(size == 4);
2767 vtd_set_long(s, addr, val);
2768 break;
2769
2770
2771 case DMAR_FSTS_REG:
2772 assert(size == 4);
2773 vtd_set_long(s, addr, val);
2774 vtd_handle_fsts_write(s);
2775 break;
2776
2777
2778 case DMAR_FECTL_REG:
2779 assert(size == 4);
2780 vtd_set_long(s, addr, val);
2781 vtd_handle_fectl_write(s);
2782 break;
2783
2784
2785 case DMAR_FEDATA_REG:
2786 assert(size == 4);
2787 vtd_set_long(s, addr, val);
2788 break;
2789
2790
2791 case DMAR_FEADDR_REG:
2792 if (size == 4) {
2793 vtd_set_long(s, addr, val);
2794 } else {
2795
2796
2797
2798
2799 vtd_set_quad(s, addr, val);
2800 }
2801 break;
2802
2803
2804 case DMAR_FEUADDR_REG:
2805 assert(size == 4);
2806 vtd_set_long(s, addr, val);
2807 break;
2808
2809
2810 case DMAR_PMEN_REG:
2811 assert(size == 4);
2812 vtd_set_long(s, addr, val);
2813 break;
2814
2815
2816 case DMAR_RTADDR_REG:
2817 if (size == 4) {
2818 vtd_set_long(s, addr, val);
2819 } else {
2820 vtd_set_quad(s, addr, val);
2821 }
2822 break;
2823
2824 case DMAR_RTADDR_REG_HI:
2825 assert(size == 4);
2826 vtd_set_long(s, addr, val);
2827 break;
2828
2829
2830 case DMAR_IQT_REG:
2831 if (size == 4) {
2832 vtd_set_long(s, addr, val);
2833 } else {
2834 vtd_set_quad(s, addr, val);
2835 }
2836 vtd_handle_iqt_write(s);
2837 break;
2838
2839 case DMAR_IQT_REG_HI:
2840 assert(size == 4);
2841 vtd_set_long(s, addr, val);
2842
2843 break;
2844
2845
2846 case DMAR_IQA_REG:
2847 if (size == 4) {
2848 vtd_set_long(s, addr, val);
2849 } else {
2850 vtd_set_quad(s, addr, val);
2851 }
2852 if (s->ecap & VTD_ECAP_SMTS &&
2853 val & VTD_IQA_DW_MASK) {
2854 s->iq_dw = true;
2855 } else {
2856 s->iq_dw = false;
2857 }
2858 break;
2859
2860 case DMAR_IQA_REG_HI:
2861 assert(size == 4);
2862 vtd_set_long(s, addr, val);
2863 break;
2864
2865
2866 case DMAR_ICS_REG:
2867 assert(size == 4);
2868 vtd_set_long(s, addr, val);
2869 vtd_handle_ics_write(s);
2870 break;
2871
2872
2873 case DMAR_IECTL_REG:
2874 assert(size == 4);
2875 vtd_set_long(s, addr, val);
2876 vtd_handle_iectl_write(s);
2877 break;
2878
2879
2880 case DMAR_IEDATA_REG:
2881 assert(size == 4);
2882 vtd_set_long(s, addr, val);
2883 break;
2884
2885
2886 case DMAR_IEADDR_REG:
2887 assert(size == 4);
2888 vtd_set_long(s, addr, val);
2889 break;
2890
2891
2892 case DMAR_IEUADDR_REG:
2893 assert(size == 4);
2894 vtd_set_long(s, addr, val);
2895 break;
2896
2897
2898 case DMAR_FRCD_REG_0_0:
2899 if (size == 4) {
2900 vtd_set_long(s, addr, val);
2901 } else {
2902 vtd_set_quad(s, addr, val);
2903 }
2904 break;
2905
2906 case DMAR_FRCD_REG_0_1:
2907 assert(size == 4);
2908 vtd_set_long(s, addr, val);
2909 break;
2910
2911 case DMAR_FRCD_REG_0_2:
2912 if (size == 4) {
2913 vtd_set_long(s, addr, val);
2914 } else {
2915 vtd_set_quad(s, addr, val);
2916
2917 vtd_update_fsts_ppf(s);
2918 }
2919 break;
2920
2921 case DMAR_FRCD_REG_0_3:
2922 assert(size == 4);
2923 vtd_set_long(s, addr, val);
2924
2925 vtd_update_fsts_ppf(s);
2926 break;
2927
2928 case DMAR_IRTA_REG:
2929 if (size == 4) {
2930 vtd_set_long(s, addr, val);
2931 } else {
2932 vtd_set_quad(s, addr, val);
2933 }
2934 break;
2935
2936 case DMAR_IRTA_REG_HI:
2937 assert(size == 4);
2938 vtd_set_long(s, addr, val);
2939 break;
2940
2941 default:
2942 if (size == 4) {
2943 vtd_set_long(s, addr, val);
2944 } else {
2945 vtd_set_quad(s, addr, val);
2946 }
2947 }
2948}
2949
2950static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
2951 IOMMUAccessFlags flag, int iommu_idx)
2952{
2953 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2954 IntelIOMMUState *s = vtd_as->iommu_state;
2955 IOMMUTLBEntry iotlb = {
2956
2957 .target_as = &address_space_memory,
2958 };
2959 bool success;
2960
2961 if (likely(s->dmar_enabled)) {
2962 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
2963 addr, flag & IOMMU_WO, &iotlb);
2964 } else {
2965
2966 iotlb.iova = addr & VTD_PAGE_MASK_4K;
2967 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
2968 iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
2969 iotlb.perm = IOMMU_RW;
2970 success = true;
2971 }
2972
2973 if (likely(success)) {
2974 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
2975 VTD_PCI_SLOT(vtd_as->devfn),
2976 VTD_PCI_FUNC(vtd_as->devfn),
2977 iotlb.iova, iotlb.translated_addr,
2978 iotlb.addr_mask);
2979 } else {
2980 error_report_once("%s: detected translation failure "
2981 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")",
2982 __func__, pci_bus_num(vtd_as->bus),
2983 VTD_PCI_SLOT(vtd_as->devfn),
2984 VTD_PCI_FUNC(vtd_as->devfn),
2985 addr);
2986 }
2987
2988 return iotlb;
2989}
2990
2991static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
2992 IOMMUNotifierFlag old,
2993 IOMMUNotifierFlag new,
2994 Error **errp)
2995{
2996 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2997 IntelIOMMUState *s = vtd_as->iommu_state;
2998
2999
3000 vtd_as->notifier_flags = new;
3001
3002 if (old == IOMMU_NOTIFIER_NONE) {
3003 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next);
3004 } else if (new == IOMMU_NOTIFIER_NONE) {
3005 QLIST_REMOVE(vtd_as, next);
3006 }
3007 return 0;
3008}
3009
3010static int vtd_post_load(void *opaque, int version_id)
3011{
3012 IntelIOMMUState *iommu = opaque;
3013
3014
3015
3016
3017
3018
3019 vtd_switch_address_space_all(iommu);
3020
3021
3022
3023
3024
3025
3026
3027
3028 vtd_update_scalable_state(iommu);
3029
3030 return 0;
3031}
3032
3033static const VMStateDescription vtd_vmstate = {
3034 .name = "iommu-intel",
3035 .version_id = 1,
3036 .minimum_version_id = 1,
3037 .priority = MIG_PRI_IOMMU,
3038 .post_load = vtd_post_load,
3039 .fields = (VMStateField[]) {
3040 VMSTATE_UINT64(root, IntelIOMMUState),
3041 VMSTATE_UINT64(intr_root, IntelIOMMUState),
3042 VMSTATE_UINT64(iq, IntelIOMMUState),
3043 VMSTATE_UINT32(intr_size, IntelIOMMUState),
3044 VMSTATE_UINT16(iq_head, IntelIOMMUState),
3045 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
3046 VMSTATE_UINT16(iq_size, IntelIOMMUState),
3047 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
3048 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
3049 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
3050 VMSTATE_UNUSED(1),
3051 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
3052 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
3053 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
3054 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
3055 VMSTATE_END_OF_LIST()
3056 }
3057};
3058
3059static const MemoryRegionOps vtd_mem_ops = {
3060 .read = vtd_mem_read,
3061 .write = vtd_mem_write,
3062 .endianness = DEVICE_LITTLE_ENDIAN,
3063 .impl = {
3064 .min_access_size = 4,
3065 .max_access_size = 8,
3066 },
3067 .valid = {
3068 .min_access_size = 4,
3069 .max_access_size = 8,
3070 },
3071};
3072
3073static Property vtd_properties[] = {
3074 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
3075 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
3076 ON_OFF_AUTO_AUTO),
3077 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
3078 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
3079 VTD_HOST_ADDRESS_WIDTH),
3080 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
3081 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
3082 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
3083 DEFINE_PROP_END_OF_LIST(),
3084};
3085
3086
3087static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
3088 VTD_IR_TableEntry *entry, uint16_t sid)
3089{
3090 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
3091 {0xffff, 0xfffb, 0xfff9, 0xfff8};
3092 dma_addr_t addr = 0x00;
3093 uint16_t mask, source_id;
3094 uint8_t bus, bus_max, bus_min;
3095
3096 addr = iommu->intr_root + index * sizeof(*entry);
3097 if (dma_memory_read(&address_space_memory, addr, entry,
3098 sizeof(*entry))) {
3099 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64,
3100 __func__, index, addr);
3101 return -VTD_FR_IR_ROOT_INVAL;
3102 }
3103
3104 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]),
3105 le64_to_cpu(entry->data[0]));
3106
3107 if (!entry->irte.present) {
3108 error_report_once("%s: detected non-present IRTE "
3109 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
3110 __func__, index, le64_to_cpu(entry->data[1]),
3111 le64_to_cpu(entry->data[0]));
3112 return -VTD_FR_IR_ENTRY_P;
3113 }
3114
3115 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
3116 entry->irte.__reserved_2) {
3117 error_report_once("%s: detected non-zero reserved IRTE "
3118 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
3119 __func__, index, le64_to_cpu(entry->data[1]),
3120 le64_to_cpu(entry->data[0]));
3121 return -VTD_FR_IR_IRTE_RSVD;
3122 }
3123
3124 if (sid != X86_IOMMU_SID_INVALID) {
3125
3126 source_id = le32_to_cpu(entry->irte.source_id);
3127 switch (entry->irte.sid_vtype) {
3128 case VTD_SVT_NONE:
3129 break;
3130
3131 case VTD_SVT_ALL:
3132 mask = vtd_svt_mask[entry->irte.sid_q];
3133 if ((source_id & mask) != (sid & mask)) {
3134 error_report_once("%s: invalid IRTE SID "
3135 "(index=%u, sid=%u, source_id=%u)",
3136 __func__, index, sid, source_id);
3137 return -VTD_FR_IR_SID_ERR;
3138 }
3139 break;
3140
3141 case VTD_SVT_BUS:
3142 bus_max = source_id >> 8;
3143 bus_min = source_id & 0xff;
3144 bus = sid >> 8;
3145 if (bus > bus_max || bus < bus_min) {
3146 error_report_once("%s: invalid SVT_BUS "
3147 "(index=%u, bus=%u, min=%u, max=%u)",
3148 __func__, index, bus, bus_min, bus_max);
3149 return -VTD_FR_IR_SID_ERR;
3150 }
3151 break;
3152
3153 default:
3154 error_report_once("%s: detected invalid IRTE SVT "
3155 "(index=%u, type=%d)", __func__,
3156 index, entry->irte.sid_vtype);
3157
3158 return -VTD_FR_IR_SID_ERR;
3159 break;
3160 }
3161 }
3162
3163 return 0;
3164}
3165
3166
3167static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
3168 X86IOMMUIrq *irq, uint16_t sid)
3169{
3170 VTD_IR_TableEntry irte = {};
3171 int ret = 0;
3172
3173 ret = vtd_irte_get(iommu, index, &irte, sid);
3174 if (ret) {
3175 return ret;
3176 }
3177
3178 irq->trigger_mode = irte.irte.trigger_mode;
3179 irq->vector = irte.irte.vector;
3180 irq->delivery_mode = irte.irte.delivery_mode;
3181 irq->dest = le32_to_cpu(irte.irte.dest_id);
3182 if (!iommu->intr_eime) {
3183#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
3184#define VTD_IR_APIC_DEST_SHIFT (8)
3185 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
3186 VTD_IR_APIC_DEST_SHIFT;
3187 }
3188 irq->dest_mode = irte.irte.dest_mode;
3189 irq->redir_hint = irte.irte.redir_hint;
3190
3191 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
3192 irq->delivery_mode, irq->dest, irq->dest_mode);
3193
3194 return 0;
3195}
3196
3197
3198static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
3199 MSIMessage *origin,
3200 MSIMessage *translated,
3201 uint16_t sid)
3202{
3203 int ret = 0;
3204 VTD_IR_MSIAddress addr;
3205 uint16_t index;
3206 X86IOMMUIrq irq = {};
3207
3208 assert(origin && translated);
3209
3210 trace_vtd_ir_remap_msi_req(origin->address, origin->data);
3211
3212 if (!iommu || !iommu->intr_enabled) {
3213 memcpy(translated, origin, sizeof(*origin));
3214 goto out;
3215 }
3216
3217 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
3218 error_report_once("%s: MSI address high 32 bits non-zero detected: "
3219 "address=0x%" PRIx64, __func__, origin->address);
3220 return -VTD_FR_IR_REQ_RSVD;
3221 }
3222
3223 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
3224 if (addr.addr.__head != 0xfee) {
3225 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32,
3226 __func__, addr.data);
3227 return -VTD_FR_IR_REQ_RSVD;
3228 }
3229
3230
3231 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
3232 memcpy(translated, origin, sizeof(*origin));
3233 goto out;
3234 }
3235
3236 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
3237
3238#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
3239#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
3240
3241 if (addr.addr.sub_valid) {
3242
3243 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
3244 }
3245
3246 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
3247 if (ret) {
3248 return ret;
3249 }
3250
3251 if (addr.addr.sub_valid) {
3252 trace_vtd_ir_remap_type("MSI");
3253 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
3254 error_report_once("%s: invalid IR MSI "
3255 "(sid=%u, address=0x%" PRIx64
3256 ", data=0x%" PRIx32 ")",
3257 __func__, sid, origin->address, origin->data);
3258 return -VTD_FR_IR_REQ_RSVD;
3259 }
3260 } else {
3261 uint8_t vector = origin->data & 0xff;
3262 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
3263
3264 trace_vtd_ir_remap_type("IOAPIC");
3265
3266
3267 if (vector != irq.vector) {
3268 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector);
3269 }
3270
3271
3272
3273 if (trigger_mode != irq.trigger_mode) {
3274 trace_vtd_warn_ir_trigger(sid, index, trigger_mode,
3275 irq.trigger_mode);
3276 }
3277 }
3278
3279
3280
3281
3282
3283 irq.msi_addr_last_bits = addr.addr.__not_care;
3284
3285
3286 x86_iommu_irq_to_msi_message(&irq, translated);
3287
3288out:
3289 trace_vtd_ir_remap_msi(origin->address, origin->data,
3290 translated->address, translated->data);
3291 return 0;
3292}
3293
3294static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
3295 MSIMessage *dst, uint16_t sid)
3296{
3297 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
3298 src, dst, sid);
3299}
3300
3301static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
3302 uint64_t *data, unsigned size,
3303 MemTxAttrs attrs)
3304{
3305 return MEMTX_OK;
3306}
3307
3308static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
3309 uint64_t value, unsigned size,
3310 MemTxAttrs attrs)
3311{
3312 int ret = 0;
3313 MSIMessage from = {}, to = {};
3314 uint16_t sid = X86_IOMMU_SID_INVALID;
3315
3316 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
3317 from.data = (uint32_t) value;
3318
3319 if (!attrs.unspecified) {
3320
3321 sid = attrs.requester_id;
3322 }
3323
3324 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
3325 if (ret) {
3326
3327
3328 return MEMTX_ERROR;
3329 }
3330
3331 apic_get_class()->send_msi(&to);
3332
3333 return MEMTX_OK;
3334}
3335
3336static const MemoryRegionOps vtd_mem_ir_ops = {
3337 .read_with_attrs = vtd_mem_ir_read,
3338 .write_with_attrs = vtd_mem_ir_write,
3339 .endianness = DEVICE_LITTLE_ENDIAN,
3340 .impl = {
3341 .min_access_size = 4,
3342 .max_access_size = 4,
3343 },
3344 .valid = {
3345 .min_access_size = 4,
3346 .max_access_size = 4,
3347 },
3348};
3349
3350VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
3351{
3352 uintptr_t key = (uintptr_t)bus;
3353 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
3354 VTDAddressSpace *vtd_dev_as;
3355 char name[128];
3356
3357 if (!vtd_bus) {
3358 uintptr_t *new_key = g_malloc(sizeof(*new_key));
3359 *new_key = (uintptr_t)bus;
3360
3361 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
3362 PCI_DEVFN_MAX);
3363 vtd_bus->bus = bus;
3364 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
3365 }
3366
3367 vtd_dev_as = vtd_bus->dev_as[devfn];
3368
3369 if (!vtd_dev_as) {
3370 snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn),
3371 PCI_FUNC(devfn));
3372 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
3373
3374 vtd_dev_as->bus = bus;
3375 vtd_dev_as->devfn = (uint8_t)devfn;
3376 vtd_dev_as->iommu_state = s;
3377 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
3378 vtd_dev_as->iova_tree = iova_tree_new();
3379
3380 memory_region_init(&vtd_dev_as->root, OBJECT(s), name, UINT64_MAX);
3381 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, "vtd-root");
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392 memory_region_init_alias(&vtd_dev_as->nodmar, OBJECT(s),
3393 "vtd-nodmar", &s->mr_nodmar, 0,
3394 memory_region_size(&s->mr_nodmar));
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406 strcat(name, "-dmar");
3407 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu),
3408 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s),
3409 name, UINT64_MAX);
3410 memory_region_init_alias(&vtd_dev_as->iommu_ir, OBJECT(s), "vtd-ir",
3411 &s->mr_ir, 0, memory_region_size(&s->mr_ir));
3412 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as->iommu),
3413 VTD_INTERRUPT_ADDR_FIRST,
3414 &vtd_dev_as->iommu_ir, 1);
3415
3416
3417
3418
3419
3420
3421 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
3422 MEMORY_REGION(&vtd_dev_as->iommu),
3423 0);
3424 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
3425 &vtd_dev_as->nodmar, 0);
3426
3427 vtd_switch_address_space(vtd_dev_as);
3428 }
3429 return vtd_dev_as;
3430}
3431
3432static uint64_t get_naturally_aligned_size(uint64_t start,
3433 uint64_t size, int gaw)
3434{
3435 uint64_t max_mask = 1ULL << gaw;
3436 uint64_t alignment = start ? start & -start : max_mask;
3437
3438 alignment = MIN(alignment, max_mask);
3439 size = MIN(size, max_mask);
3440
3441 if (alignment <= size) {
3442
3443 return alignment;
3444 } else {
3445
3446 return 1ULL << (63 - clz64(size));
3447 }
3448}
3449
3450
3451static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
3452{
3453 hwaddr size, remain;
3454 hwaddr start = n->start;
3455 hwaddr end = n->end;
3456 IntelIOMMUState *s = as->iommu_state;
3457 DMAMap map;
3458
3459
3460
3461
3462
3463
3464
3465 if (end > VTD_ADDRESS_SIZE(s->aw_bits) - 1) {
3466
3467
3468
3469
3470 end = VTD_ADDRESS_SIZE(s->aw_bits) - 1;
3471 }
3472
3473 assert(start <= end);
3474 size = remain = end - start + 1;
3475
3476 while (remain >= VTD_PAGE_SIZE) {
3477 IOMMUTLBEntry entry;
3478 uint64_t mask = get_naturally_aligned_size(start, remain, s->aw_bits);
3479
3480 assert(mask);
3481
3482 entry.iova = start;
3483 entry.addr_mask = mask - 1;
3484 entry.target_as = &address_space_memory;
3485 entry.perm = IOMMU_NONE;
3486
3487 entry.translated_addr = 0;
3488
3489 memory_region_notify_one(n, &entry);
3490
3491 start += mask;
3492 remain -= mask;
3493 }
3494
3495 assert(!remain);
3496
3497 trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
3498 VTD_PCI_SLOT(as->devfn),
3499 VTD_PCI_FUNC(as->devfn),
3500 n->start, size);
3501
3502 map.iova = n->start;
3503 map.size = size;
3504 iova_tree_remove(as->iova_tree, &map);
3505}
3506
3507static void vtd_address_space_unmap_all(IntelIOMMUState *s)
3508{
3509 VTDAddressSpace *vtd_as;
3510 IOMMUNotifier *n;
3511
3512 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
3513 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
3514 vtd_address_space_unmap(vtd_as, n);
3515 }
3516 }
3517}
3518
3519static void vtd_address_space_refresh_all(IntelIOMMUState *s)
3520{
3521 vtd_address_space_unmap_all(s);
3522 vtd_switch_address_space_all(s);
3523}
3524
3525static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
3526{
3527 memory_region_notify_one((IOMMUNotifier *)private, entry);
3528 return 0;
3529}
3530
3531static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
3532{
3533 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu);
3534 IntelIOMMUState *s = vtd_as->iommu_state;
3535 uint8_t bus_n = pci_bus_num(vtd_as->bus);
3536 VTDContextEntry ce;
3537
3538
3539
3540
3541
3542
3543 vtd_address_space_unmap(vtd_as, n);
3544
3545 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
3546 trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" :
3547 "legacy mode",
3548 bus_n, PCI_SLOT(vtd_as->devfn),
3549 PCI_FUNC(vtd_as->devfn),
3550 vtd_get_domain_id(s, &ce),
3551 ce.hi, ce.lo);
3552 if (vtd_as_has_map_notifier(vtd_as)) {
3553
3554 vtd_page_walk_info info = {
3555 .hook_fn = vtd_replay_hook,
3556 .private = (void *)n,
3557 .notify_unmap = false,
3558 .aw = s->aw_bits,
3559 .as = vtd_as,
3560 .domain_id = vtd_get_domain_id(s, &ce),
3561 };
3562
3563 vtd_page_walk(s, &ce, 0, ~0ULL, &info);
3564 }
3565 } else {
3566 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
3567 PCI_FUNC(vtd_as->devfn));
3568 }
3569
3570 return;
3571}
3572
3573
3574
3575
3576static void vtd_init(IntelIOMMUState *s)
3577{
3578 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3579
3580 memset(s->csr, 0, DMAR_REG_SIZE);
3581 memset(s->wmask, 0, DMAR_REG_SIZE);
3582 memset(s->w1cmask, 0, DMAR_REG_SIZE);
3583 memset(s->womask, 0, DMAR_REG_SIZE);
3584
3585 s->root = 0;
3586 s->root_scalable = false;
3587 s->dmar_enabled = false;
3588 s->intr_enabled = false;
3589 s->iq_head = 0;
3590 s->iq_tail = 0;
3591 s->iq = 0;
3592 s->iq_size = 0;
3593 s->qi_enabled = false;
3594 s->iq_last_desc_type = VTD_INV_DESC_NONE;
3595 s->iq_dw = false;
3596 s->next_frcd_reg = 0;
3597 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
3598 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
3599 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits);
3600 if (s->dma_drain) {
3601 s->cap |= VTD_CAP_DRAIN;
3602 }
3603 if (s->aw_bits == VTD_HOST_AW_48BIT) {
3604 s->cap |= VTD_CAP_SAGAW_48bit;
3605 }
3606 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
3607
3608
3609
3610
3611 vtd_spte_rsvd[0] = ~0ULL;
3612 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
3613 x86_iommu->dt_supported);
3614 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
3615 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
3616 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
3617
3618 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
3619 x86_iommu->dt_supported);
3620 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
3621 x86_iommu->dt_supported);
3622
3623 if (x86_iommu_ir_supported(x86_iommu)) {
3624 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
3625 if (s->intr_eim == ON_OFF_AUTO_ON) {
3626 s->ecap |= VTD_ECAP_EIM;
3627 }
3628 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
3629 }
3630
3631 if (x86_iommu->dt_supported) {
3632 s->ecap |= VTD_ECAP_DT;
3633 }
3634
3635 if (x86_iommu->pt_supported) {
3636 s->ecap |= VTD_ECAP_PT;
3637 }
3638
3639 if (s->caching_mode) {
3640 s->cap |= VTD_CAP_CM;
3641 }
3642
3643
3644 if (s->scalable_mode) {
3645 s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
3646 }
3647
3648 vtd_reset_caches(s);
3649
3650
3651 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
3652 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
3653 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
3654 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
3655 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
3656 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
3657 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffffc00ULL, 0);
3658 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
3659 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
3660
3661
3662 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
3663 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
3664 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
3665 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
3666
3667
3668
3669
3670 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
3671
3672
3673
3674
3675
3676 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
3677
3678 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
3679 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
3680 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff807ULL, 0);
3681 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
3682 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
3683 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
3684 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
3685
3686 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
3687
3688
3689 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
3690 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
3691 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
3692
3693
3694 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
3695 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
3696
3697
3698
3699
3700 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
3701}
3702
3703
3704
3705
3706static void vtd_reset(DeviceState *dev)
3707{
3708 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
3709
3710 vtd_init(s);
3711 vtd_address_space_refresh_all(s);
3712}
3713
3714static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
3715{
3716 IntelIOMMUState *s = opaque;
3717 VTDAddressSpace *vtd_as;
3718
3719 assert(0 <= devfn && devfn < PCI_DEVFN_MAX);
3720
3721 vtd_as = vtd_find_add_as(s, bus, devfn);
3722 return &vtd_as->as;
3723}
3724
3725static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
3726{
3727 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3728
3729 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu_ir_supported(x86_iommu)) {
3730 error_setg(errp, "eim=on cannot be selected without intremap=on");
3731 return false;
3732 }
3733
3734 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
3735 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
3736 && x86_iommu_ir_supported(x86_iommu) ?
3737 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
3738 }
3739 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
3740 if (!kvm_irqchip_in_kernel()) {
3741 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
3742 return false;
3743 }
3744 if (!kvm_enable_x2apic()) {
3745 error_setg(errp, "eim=on requires support on the KVM side"
3746 "(X2APIC_API, first shipped in v4.7)");
3747 return false;
3748 }
3749 }
3750
3751
3752 if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
3753 (s->aw_bits != VTD_HOST_AW_48BIT)) {
3754 error_setg(errp, "Supported values for x-aw-bits are: %d, %d",
3755 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
3756 return false;
3757 }
3758
3759 if (s->scalable_mode && !s->dma_drain) {
3760 error_setg(errp, "Need to set dma_drain for scalable mode");
3761 return false;
3762 }
3763
3764 return true;
3765}
3766
3767static int vtd_machine_done_notify_one(Object *child, void *unused)
3768{
3769 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
3770
3771
3772
3773
3774
3775
3776 if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) {
3777 vtd_panic_require_caching_mode();
3778 }
3779
3780 return 0;
3781}
3782
3783static void vtd_machine_done_hook(Notifier *notifier, void *unused)
3784{
3785 object_child_foreach_recursive(object_get_root(),
3786 vtd_machine_done_notify_one, NULL);
3787}
3788
3789static Notifier vtd_machine_done_notify = {
3790 .notify = vtd_machine_done_hook,
3791};
3792
3793static void vtd_realize(DeviceState *dev, Error **errp)
3794{
3795 MachineState *ms = MACHINE(qdev_get_machine());
3796 PCMachineState *pcms = PC_MACHINE(ms);
3797 X86MachineState *x86ms = X86_MACHINE(ms);
3798 PCIBus *bus = pcms->bus;
3799 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
3800 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
3801
3802 x86_iommu->type = TYPE_INTEL;
3803
3804 if (!vtd_decide_config(s, errp)) {
3805 return;
3806 }
3807
3808 QLIST_INIT(&s->vtd_as_with_notifiers);
3809 qemu_mutex_init(&s->iommu_lock);
3810 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
3811 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
3812 "intel_iommu", DMAR_REG_SIZE);
3813
3814
3815 memory_region_init(&s->mr_nodmar, OBJECT(s), "vtd-nodmar",
3816 UINT64_MAX);
3817 memory_region_init_io(&s->mr_ir, OBJECT(s), &vtd_mem_ir_ops,
3818 s, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE);
3819 memory_region_init_alias(&s->mr_sys_alias, OBJECT(s),
3820 "vtd-sys-alias", get_system_memory(), 0,
3821 memory_region_size(get_system_memory()));
3822 memory_region_add_subregion_overlap(&s->mr_nodmar, 0,
3823 &s->mr_sys_alias, 0);
3824 memory_region_add_subregion_overlap(&s->mr_nodmar,
3825 VTD_INTERRUPT_ADDR_FIRST,
3826 &s->mr_ir, 1);
3827
3828 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
3829
3830 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3831 g_free, g_free);
3832 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3833 g_free, g_free);
3834 vtd_init(s);
3835 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
3836 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
3837
3838 x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
3839 qemu_add_machine_init_done_notifier(&vtd_machine_done_notify);
3840}
3841
3842static void vtd_class_init(ObjectClass *klass, void *data)
3843{
3844 DeviceClass *dc = DEVICE_CLASS(klass);
3845 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
3846
3847 dc->reset = vtd_reset;
3848 dc->vmsd = &vtd_vmstate;
3849 dc->props = vtd_properties;
3850 dc->hotpluggable = false;
3851 x86_class->realize = vtd_realize;
3852 x86_class->int_remap = vtd_int_remap;
3853
3854 dc->user_creatable = true;
3855 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
3856 dc->desc = "Intel IOMMU (VT-d) DMA Remapping device";
3857}
3858
3859static const TypeInfo vtd_info = {
3860 .name = TYPE_INTEL_IOMMU_DEVICE,
3861 .parent = TYPE_X86_IOMMU_DEVICE,
3862 .instance_size = sizeof(IntelIOMMUState),
3863 .class_init = vtd_class_init,
3864};
3865
3866static void vtd_iommu_memory_region_class_init(ObjectClass *klass,
3867 void *data)
3868{
3869 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
3870
3871 imrc->translate = vtd_iommu_translate;
3872 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed;
3873 imrc->replay = vtd_iommu_replay;
3874}
3875
3876static const TypeInfo vtd_iommu_memory_region_info = {
3877 .parent = TYPE_IOMMU_MEMORY_REGION,
3878 .name = TYPE_INTEL_IOMMU_MEMORY_REGION,
3879 .class_init = vtd_iommu_memory_region_class_init,
3880};
3881
3882static void vtd_register_types(void)
3883{
3884 type_register_static(&vtd_info);
3885 type_register_static(&vtd_iommu_memory_region_info);
3886}
3887
3888type_init(vtd_register_types)
3889