qemu/hw/i386/pc_q35.c
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   1/*
   2 * Q35 chipset based pc system emulator
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2009, 2010
   6 *               Isaku Yamahata <yamahata at valinux co jp>
   7 *               VA Linux Systems Japan K.K.
   8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9 *
  10 * This is based on pc.c, but heavily modified.
  11 *
  12 * Permission is hereby granted, free of charge, to any person obtaining a copy
  13 * of this software and associated documentation files (the "Software"), to deal
  14 * in the Software without restriction, including without limitation the rights
  15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16 * copies of the Software, and to permit persons to whom the Software is
  17 * furnished to do so, subject to the following conditions:
  18 *
  19 * The above copyright notice and this permission notice shall be included in
  20 * all copies or substantial portions of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28 * THE SOFTWARE.
  29 */
  30
  31#include "qemu/osdep.h"
  32#include "qemu/units.h"
  33#include "hw/loader.h"
  34#include "sysemu/arch_init.h"
  35#include "hw/i2c/smbus_eeprom.h"
  36#include "hw/rtc/mc146818rtc.h"
  37#include "hw/xen/xen.h"
  38#include "sysemu/kvm.h"
  39#include "hw/kvm/clock.h"
  40#include "hw/pci-host/q35.h"
  41#include "hw/qdev-properties.h"
  42#include "exec/address-spaces.h"
  43#include "hw/i386/x86.h"
  44#include "hw/i386/pc.h"
  45#include "hw/i386/ich9.h"
  46#include "hw/i386/amd_iommu.h"
  47#include "hw/i386/intel_iommu.h"
  48#include "hw/display/ramfb.h"
  49#include "hw/firmware/smbios.h"
  50#include "hw/ide/pci.h"
  51#include "hw/ide/ahci.h"
  52#include "hw/usb.h"
  53#include "qapi/error.h"
  54#include "qemu/error-report.h"
  55#include "sysemu/numa.h"
  56
  57/* ICH9 AHCI has 6 ports */
  58#define MAX_SATA_PORTS     6
  59
  60struct ehci_companions {
  61    const char *name;
  62    int func;
  63    int port;
  64};
  65
  66static const struct ehci_companions ich9_1d[] = {
  67    { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  68    { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  69    { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  70};
  71
  72static const struct ehci_companions ich9_1a[] = {
  73    { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  74    { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  75    { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  76};
  77
  78static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  79{
  80    const struct ehci_companions *comp;
  81    PCIDevice *ehci, *uhci;
  82    BusState *usbbus;
  83    const char *name;
  84    int i;
  85
  86    switch (slot) {
  87    case 0x1d:
  88        name = "ich9-usb-ehci1";
  89        comp = ich9_1d;
  90        break;
  91    case 0x1a:
  92        name = "ich9-usb-ehci2";
  93        comp = ich9_1a;
  94        break;
  95    default:
  96        return -1;
  97    }
  98
  99    ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
 100    qdev_init_nofail(&ehci->qdev);
 101    usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 102
 103    for (i = 0; i < 3; i++) {
 104        uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
 105                                        true, comp[i].name);
 106        qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 107        qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 108        qdev_init_nofail(&uhci->qdev);
 109    }
 110    return 0;
 111}
 112
 113/* PC hardware initialisation */
 114static void pc_q35_init(MachineState *machine)
 115{
 116    PCMachineState *pcms = PC_MACHINE(machine);
 117    PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 118    X86MachineState *x86ms = X86_MACHINE(machine);
 119    Q35PCIHost *q35_host;
 120    PCIHostState *phb;
 121    PCIBus *host_bus;
 122    PCIDevice *lpc;
 123    DeviceState *lpc_dev;
 124    BusState *idebus[MAX_SATA_PORTS];
 125    ISADevice *rtc_state;
 126    MemoryRegion *system_io = get_system_io();
 127    MemoryRegion *pci_memory;
 128    MemoryRegion *rom_memory;
 129    MemoryRegion *ram_memory;
 130    GSIState *gsi_state;
 131    ISABus *isa_bus;
 132    int i;
 133    ICH9LPCState *ich9_lpc;
 134    PCIDevice *ahci;
 135    ram_addr_t lowmem;
 136    DriveInfo *hd[MAX_SATA_PORTS];
 137    MachineClass *mc = MACHINE_GET_CLASS(machine);
 138
 139    /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 140     * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 141     * also known as MMCFG).
 142     * If it doesn't, we need to split it in chunks below and above 4G.
 143     * In any case, try to make sure that guest addresses aligned at
 144     * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 145     */
 146    if (machine->ram_size >= 0xb0000000) {
 147        lowmem = 0x80000000;
 148    } else {
 149        lowmem = 0xb0000000;
 150    }
 151
 152    /* Handle the machine opt max-ram-below-4g.  It is basically doing
 153     * min(qemu limit, user limit).
 154     */
 155    if (!x86ms->max_ram_below_4g) {
 156        x86ms->max_ram_below_4g = 4 * GiB;
 157    }
 158    if (lowmem > x86ms->max_ram_below_4g) {
 159        lowmem = x86ms->max_ram_below_4g;
 160        if (machine->ram_size - lowmem > lowmem &&
 161            lowmem & (1 * GiB - 1)) {
 162            warn_report("There is possibly poor performance as the ram size "
 163                        " (0x%" PRIx64 ") is more then twice the size of"
 164                        " max-ram-below-4g (%"PRIu64") and"
 165                        " max-ram-below-4g is not a multiple of 1G.",
 166                        (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
 167        }
 168    }
 169
 170    if (machine->ram_size >= lowmem) {
 171        x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 172        x86ms->below_4g_mem_size = lowmem;
 173    } else {
 174        x86ms->above_4g_mem_size = 0;
 175        x86ms->below_4g_mem_size = machine->ram_size;
 176    }
 177
 178    if (xen_enabled()) {
 179        xen_hvm_init(pcms, &ram_memory);
 180    }
 181
 182    x86_cpus_init(x86ms, pcmc->default_cpu_version);
 183
 184    kvmclock_create();
 185
 186    /* pci enabled */
 187    if (pcmc->pci_enabled) {
 188        pci_memory = g_new(MemoryRegion, 1);
 189        memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 190        rom_memory = pci_memory;
 191    } else {
 192        pci_memory = NULL;
 193        rom_memory = get_system_memory();
 194    }
 195
 196    pc_guest_info_init(pcms);
 197
 198    if (pcmc->smbios_defaults) {
 199        /* These values are guest ABI, do not change */
 200        smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 201                            mc->name, pcmc->smbios_legacy_mode,
 202                            pcmc->smbios_uuid_encoded,
 203                            SMBIOS_ENTRY_POINT_21);
 204    }
 205
 206    /* allocate ram and load rom/bios */
 207    if (!xen_enabled()) {
 208        pc_memory_init(pcms, get_system_memory(),
 209                       rom_memory, &ram_memory);
 210    }
 211
 212    /* create pci host bus */
 213    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 214
 215    object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 216    object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 217                             MCH_HOST_PROP_RAM_MEM, NULL);
 218    object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 219                             MCH_HOST_PROP_PCI_MEM, NULL);
 220    object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 221                             MCH_HOST_PROP_SYSTEM_MEM, NULL);
 222    object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 223                             MCH_HOST_PROP_IO_MEM, NULL);
 224    object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size,
 225                            PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 226    object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
 227                            PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 228    /* pci */
 229    qdev_init_nofail(DEVICE(q35_host));
 230    phb = PCI_HOST_BRIDGE(q35_host);
 231    host_bus = phb->bus;
 232    /* create ISA bus */
 233    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 234                                          ICH9_LPC_FUNC), true,
 235                                          TYPE_ICH9_LPC_DEVICE);
 236
 237    object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 238                             TYPE_HOTPLUG_HANDLER,
 239                             (Object **)&pcms->acpi_dev,
 240                             object_property_allow_set_link,
 241                             OBJ_PROP_LINK_STRONG, &error_abort);
 242    object_property_set_link(OBJECT(machine), OBJECT(lpc),
 243                             PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 244
 245    /* irq lines */
 246    gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 247
 248    ich9_lpc = ICH9_LPC_DEVICE(lpc);
 249    lpc_dev = DEVICE(lpc);
 250    for (i = 0; i < GSI_NUM_PINS; i++) {
 251        qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 252    }
 253    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 254                 ICH9_LPC_NB_PIRQS);
 255    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 256    isa_bus = ich9_lpc->isa_bus;
 257
 258    pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 259
 260    if (pcmc->pci_enabled) {
 261        ioapic_init_gsi(gsi_state, "q35");
 262    }
 263
 264    if (tcg_enabled()) {
 265        x86_register_ferr_irq(x86ms->gsi[13]);
 266    }
 267
 268    assert(pcms->vmport != ON_OFF_AUTO__MAX);
 269    if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 270        pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 271    }
 272
 273    /* init basic PC hardware */
 274    pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 275                         (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
 276                         0xff0104);
 277
 278    /* connect pm stuff to lpc */
 279    ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 280
 281    if (pcms->sata_enabled) {
 282        /* ahci and SATA device, for q35 1 ahci controller is built-in */
 283        ahci = pci_create_simple_multifunction(host_bus,
 284                                               PCI_DEVFN(ICH9_SATA1_DEV,
 285                                                         ICH9_SATA1_FUNC),
 286                                               true, "ich9-ahci");
 287        idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 288        idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 289        g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 290        ide_drive_get(hd, ahci_get_num_ports(ahci));
 291        ahci_ide_create_devs(ahci, hd);
 292    } else {
 293        idebus[0] = idebus[1] = NULL;
 294    }
 295
 296    if (machine_usb(machine)) {
 297        /* Should we create 6 UHCI according to ich9 spec? */
 298        ehci_create_ich9_with_companions(host_bus, 0x1d);
 299    }
 300
 301    if (pcms->smbus_enabled) {
 302        /* TODO: Populate SPD eeprom data.  */
 303        pcms->smbus = ich9_smb_init(host_bus,
 304                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 305                                    0xb100);
 306        smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 307    }
 308
 309    pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 310
 311    /* the rest devices to which pci devfn is automatically assigned */
 312    pc_vga_init(isa_bus, host_bus);
 313    pc_nic_init(pcmc, isa_bus, host_bus);
 314
 315    if (machine->nvdimms_state->is_enabled) {
 316        nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 317                               x86ms->fw_cfg, OBJECT(pcms));
 318    }
 319}
 320
 321#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 322    static void pc_init_##suffix(MachineState *machine) \
 323    { \
 324        void (*compat)(MachineState *m) = (compatfn); \
 325        if (compat) { \
 326            compat(machine); \
 327        } \
 328        pc_q35_init(machine); \
 329    } \
 330    DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 331
 332
 333static void pc_q35_machine_options(MachineClass *m)
 334{
 335    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 336    pcmc->default_nic_model = "e1000e";
 337
 338    m->family = "pc_q35";
 339    m->desc = "Standard PC (Q35 + ICH9, 2009)";
 340    m->units_per_default_bus = 1;
 341    m->default_machine_opts = "firmware=bios-256k.bin";
 342    m->default_display = "std";
 343    m->default_kernel_irqchip_split = false;
 344    m->no_floppy = 1;
 345    machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 346    machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 347    machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 348    m->max_cpus = 288;
 349}
 350
 351static void pc_q35_4_2_machine_options(MachineClass *m)
 352{
 353    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 354    pc_q35_machine_options(m);
 355    m->alias = "q35";
 356    pcmc->default_cpu_version = 1;
 357}
 358
 359DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 360                   pc_q35_4_2_machine_options);
 361
 362static void pc_q35_4_1_machine_options(MachineClass *m)
 363{
 364    pc_q35_4_2_machine_options(m);
 365    m->alias = NULL;
 366    compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 367    compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 368}
 369
 370DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 371                   pc_q35_4_1_machine_options);
 372
 373static void pc_q35_4_0_1_machine_options(MachineClass *m)
 374{
 375    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 376    pc_q35_4_1_machine_options(m);
 377    m->alias = NULL;
 378    pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 379    /*
 380     * This is the default machine for the 4.0-stable branch. It is basically
 381     * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 382     * 4.0 compat props.
 383     */
 384    compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 385    compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 386}
 387
 388DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 389                   pc_q35_4_0_1_machine_options);
 390
 391static void pc_q35_4_0_machine_options(MachineClass *m)
 392{
 393    pc_q35_4_0_1_machine_options(m);
 394    m->default_kernel_irqchip_split = true;
 395    m->alias = NULL;
 396    /* Compat props are applied by the 4.0.1 machine */
 397}
 398
 399DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 400                   pc_q35_4_0_machine_options);
 401
 402static void pc_q35_3_1_machine_options(MachineClass *m)
 403{
 404    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 405
 406    pc_q35_4_0_machine_options(m);
 407    m->default_kernel_irqchip_split = false;
 408    pcmc->do_not_add_smb_acpi = true;
 409    m->smbus_no_migration_support = true;
 410    m->alias = NULL;
 411    pcmc->pvh_enabled = false;
 412    compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 413    compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 414}
 415
 416DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 417                   pc_q35_3_1_machine_options);
 418
 419static void pc_q35_3_0_machine_options(MachineClass *m)
 420{
 421    pc_q35_3_1_machine_options(m);
 422    compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 423    compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 424}
 425
 426DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 427                    pc_q35_3_0_machine_options);
 428
 429static void pc_q35_2_12_machine_options(MachineClass *m)
 430{
 431    pc_q35_3_0_machine_options(m);
 432    compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 433    compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 434}
 435
 436DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 437                   pc_q35_2_12_machine_options);
 438
 439static void pc_q35_2_11_machine_options(MachineClass *m)
 440{
 441    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 442
 443    pc_q35_2_12_machine_options(m);
 444    pcmc->default_nic_model = "e1000";
 445    compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 446    compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 447}
 448
 449DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 450                   pc_q35_2_11_machine_options);
 451
 452static void pc_q35_2_10_machine_options(MachineClass *m)
 453{
 454    pc_q35_2_11_machine_options(m);
 455    compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 456    compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 457    m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 458    m->auto_enable_numa_with_memhp = false;
 459}
 460
 461DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 462                   pc_q35_2_10_machine_options);
 463
 464static void pc_q35_2_9_machine_options(MachineClass *m)
 465{
 466    pc_q35_2_10_machine_options(m);
 467    compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 468    compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 469}
 470
 471DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 472                   pc_q35_2_9_machine_options);
 473
 474static void pc_q35_2_8_machine_options(MachineClass *m)
 475{
 476    pc_q35_2_9_machine_options(m);
 477    compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 478    compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 479}
 480
 481DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 482                   pc_q35_2_8_machine_options);
 483
 484static void pc_q35_2_7_machine_options(MachineClass *m)
 485{
 486    pc_q35_2_8_machine_options(m);
 487    m->max_cpus = 255;
 488    compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 489    compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 490}
 491
 492DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 493                   pc_q35_2_7_machine_options);
 494
 495static void pc_q35_2_6_machine_options(MachineClass *m)
 496{
 497    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 498
 499    pc_q35_2_7_machine_options(m);
 500    pcmc->legacy_cpu_hotplug = true;
 501    pcmc->linuxboot_dma_enabled = false;
 502    compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 503    compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 504}
 505
 506DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 507                   pc_q35_2_6_machine_options);
 508
 509static void pc_q35_2_5_machine_options(MachineClass *m)
 510{
 511    X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 512
 513    pc_q35_2_6_machine_options(m);
 514    x86mc->save_tsc_khz = false;
 515    m->legacy_fw_cfg_order = 1;
 516    compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 517    compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 518}
 519
 520DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 521                   pc_q35_2_5_machine_options);
 522
 523static void pc_q35_2_4_machine_options(MachineClass *m)
 524{
 525    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 526
 527    pc_q35_2_5_machine_options(m);
 528    m->hw_version = "2.4.0";
 529    pcmc->broken_reserved_end = true;
 530    compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 531    compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 532}
 533
 534DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 535                   pc_q35_2_4_machine_options);
 536