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13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "cpu.h"
16#include "hw/sysbus.h"
17#include "migration/vmstate.h"
18#include "qemu/timer.h"
19#include "hw/intc/armv7m_nvic.h"
20#include "hw/irq.h"
21#include "hw/qdev-properties.h"
22#include "target/arm/cpu.h"
23#include "exec/exec-all.h"
24#include "exec/memop.h"
25#include "qemu/log.h"
26#include "qemu/module.h"
27#include "trace.h"
28
29
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52
53#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
54#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
55
56
57
58
59#define NVIC_NOEXC_PRIO 0x100
60
61#define NVIC_NS_PRIO_LIMIT 0x80
62
63static const uint8_t nvic_id[] = {
64 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
65};
66
67static int nvic_pending_prio(NVICState *s)
68{
69
70
71
72 return s->vectpending_prio;
73}
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89static bool nvic_rettobase(NVICState *s)
90{
91 int irq, nhand = 0;
92 bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
93
94 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
95 if (s->vectors[irq].active ||
96 (check_sec && irq < NVIC_INTERNAL_VECTORS &&
97 s->sec_vectors[irq].active)) {
98 nhand++;
99 if (nhand == 2) {
100 return 0;
101 }
102 }
103 }
104
105 return 1;
106}
107
108
109
110
111
112static bool nvic_isrpending(NVICState *s)
113{
114 int irq;
115
116
117
118
119 if (s->vectpending > NVIC_FIRST_IRQ) {
120 return true;
121 }
122 if (s->vectpending == 0) {
123 return false;
124 }
125
126 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
127 if (s->vectors[irq].pending) {
128 return true;
129 }
130 }
131 return false;
132}
133
134static bool exc_is_banked(int exc)
135{
136
137
138
139 return exc == ARMV7M_EXCP_HARD ||
140 exc == ARMV7M_EXCP_MEM ||
141 exc == ARMV7M_EXCP_USAGE ||
142 exc == ARMV7M_EXCP_SVC ||
143 exc == ARMV7M_EXCP_PENDSV ||
144 exc == ARMV7M_EXCP_SYSTICK;
145}
146
147
148
149
150
151static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
152{
153 return ~0U << (s->prigroup[secure] + 1);
154}
155
156static bool exc_targets_secure(NVICState *s, int exc)
157{
158
159 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
160 return false;
161 }
162
163 if (exc >= NVIC_FIRST_IRQ) {
164 return !s->itns[exc];
165 }
166
167
168 assert(!exc_is_banked(exc));
169
170 switch (exc) {
171 case ARMV7M_EXCP_NMI:
172 case ARMV7M_EXCP_BUS:
173 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
174 case ARMV7M_EXCP_SECURE:
175 return true;
176 case ARMV7M_EXCP_DEBUG:
177
178 return false;
179 default:
180
181
182
183
184
185 return true;
186 }
187}
188
189static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
190{
191
192
193
194
195 if (rawprio < 0) {
196 return rawprio;
197 }
198 rawprio &= nvic_gprio_mask(s, targets_secure);
199
200
201
202 if (!targets_secure &&
203 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
204 rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
205 }
206 return rawprio;
207}
208
209
210
211
212static void nvic_recompute_state_secure(NVICState *s)
213{
214 int i, bank;
215 int pend_prio = NVIC_NOEXC_PRIO;
216 int active_prio = NVIC_NOEXC_PRIO;
217 int pend_irq = 0;
218 bool pending_is_s_banked = false;
219 int pend_subprio = 0;
220
221
222
223
224
225
226
227
228
229
230 for (i = 1; i < s->num_irq; i++) {
231 for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
232 VecInfo *vec;
233 int prio, subprio;
234 bool targets_secure;
235
236 if (bank == M_REG_S) {
237 if (!exc_is_banked(i)) {
238 continue;
239 }
240 vec = &s->sec_vectors[i];
241 targets_secure = true;
242 } else {
243 vec = &s->vectors[i];
244 targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
245 }
246
247 prio = exc_group_prio(s, vec->prio, targets_secure);
248 subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure);
249 if (vec->enabled && vec->pending &&
250 ((prio < pend_prio) ||
251 (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) {
252 pend_prio = prio;
253 pend_subprio = subprio;
254 pend_irq = i;
255 pending_is_s_banked = (bank == M_REG_S);
256 }
257 if (vec->active && prio < active_prio) {
258 active_prio = prio;
259 }
260 }
261 }
262
263 s->vectpending_is_s_banked = pending_is_s_banked;
264 s->vectpending = pend_irq;
265 s->vectpending_prio = pend_prio;
266 s->exception_prio = active_prio;
267
268 trace_nvic_recompute_state_secure(s->vectpending,
269 s->vectpending_is_s_banked,
270 s->vectpending_prio,
271 s->exception_prio);
272}
273
274
275static void nvic_recompute_state(NVICState *s)
276{
277 int i;
278 int pend_prio = NVIC_NOEXC_PRIO;
279 int active_prio = NVIC_NOEXC_PRIO;
280 int pend_irq = 0;
281
282
283
284
285
286
287
288
289 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
290 nvic_recompute_state_secure(s);
291 return;
292 }
293
294 for (i = 1; i < s->num_irq; i++) {
295 VecInfo *vec = &s->vectors[i];
296
297 if (vec->enabled && vec->pending && vec->prio < pend_prio) {
298 pend_prio = vec->prio;
299 pend_irq = i;
300 }
301 if (vec->active && vec->prio < active_prio) {
302 active_prio = vec->prio;
303 }
304 }
305
306 if (active_prio > 0) {
307 active_prio &= nvic_gprio_mask(s, false);
308 }
309
310 if (pend_prio > 0) {
311 pend_prio &= nvic_gprio_mask(s, false);
312 }
313
314 s->vectpending = pend_irq;
315 s->vectpending_prio = pend_prio;
316 s->exception_prio = active_prio;
317
318 trace_nvic_recompute_state(s->vectpending,
319 s->vectpending_prio,
320 s->exception_prio);
321}
322
323
324
325
326
327static inline int nvic_exec_prio(NVICState *s)
328{
329 CPUARMState *env = &s->cpu->env;
330 int running = NVIC_NOEXC_PRIO;
331
332 if (env->v7m.basepri[M_REG_NS] > 0) {
333 running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
334 }
335
336 if (env->v7m.basepri[M_REG_S] > 0) {
337 int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
338 if (running > basepri) {
339 running = basepri;
340 }
341 }
342
343 if (env->v7m.primask[M_REG_NS]) {
344 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
345 if (running > NVIC_NS_PRIO_LIMIT) {
346 running = NVIC_NS_PRIO_LIMIT;
347 }
348 } else {
349 running = 0;
350 }
351 }
352
353 if (env->v7m.primask[M_REG_S]) {
354 running = 0;
355 }
356
357 if (env->v7m.faultmask[M_REG_NS]) {
358 if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
359 running = -1;
360 } else {
361 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
362 if (running > NVIC_NS_PRIO_LIMIT) {
363 running = NVIC_NS_PRIO_LIMIT;
364 }
365 } else {
366 running = 0;
367 }
368 }
369 }
370
371 if (env->v7m.faultmask[M_REG_S]) {
372 running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
373 }
374
375
376 return MIN(running, s->exception_prio);
377}
378
379bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
380{
381
382
383
384
385
386
387
388
389 NVICState *s = opaque;
390
391 if (s->cpu->env.v7m.faultmask[secure]) {
392 return true;
393 }
394
395 if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
396 s->vectors[ARMV7M_EXCP_HARD].active) {
397 return true;
398 }
399
400 if (s->vectors[ARMV7M_EXCP_NMI].active &&
401 exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
402 return true;
403 }
404
405 return false;
406}
407
408bool armv7m_nvic_can_take_pending_exception(void *opaque)
409{
410 NVICState *s = opaque;
411
412 return nvic_exec_prio(s) > nvic_pending_prio(s);
413}
414
415int armv7m_nvic_raw_execution_priority(void *opaque)
416{
417 NVICState *s = opaque;
418
419 return s->exception_prio;
420}
421
422
423
424
425
426static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
427{
428 assert(irq > ARMV7M_EXCP_NMI);
429 assert(irq < s->num_irq);
430
431 prio &= MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits);
432
433 if (secure) {
434 assert(exc_is_banked(irq));
435 s->sec_vectors[irq].prio = prio;
436 } else {
437 s->vectors[irq].prio = prio;
438 }
439
440 trace_nvic_set_prio(irq, secure, prio);
441}
442
443
444
445
446
447static int get_prio(NVICState *s, unsigned irq, bool secure)
448{
449 assert(irq > ARMV7M_EXCP_NMI);
450 assert(irq < s->num_irq);
451
452 if (secure) {
453 assert(exc_is_banked(irq));
454 return s->sec_vectors[irq].prio;
455 } else {
456 return s->vectors[irq].prio;
457 }
458}
459
460
461
462
463
464
465static void nvic_irq_update(NVICState *s)
466{
467 int lvl;
468 int pend_prio;
469
470 nvic_recompute_state(s);
471 pend_prio = nvic_pending_prio(s);
472
473
474
475
476
477
478
479 lvl = (pend_prio < s->exception_prio);
480 trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
481 qemu_set_irq(s->excpout, lvl);
482}
483
484
485
486
487
488
489
490
491
492
493
494
495
496static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
497{
498 NVICState *s = (NVICState *)opaque;
499 VecInfo *vec;
500
501 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
502
503 if (secure) {
504 assert(exc_is_banked(irq));
505 vec = &s->sec_vectors[irq];
506 } else {
507 vec = &s->vectors[irq];
508 }
509 trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
510 if (vec->pending) {
511 vec->pending = 0;
512 nvic_irq_update(s);
513 }
514}
515
516static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
517 bool derived)
518{
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535 NVICState *s = (NVICState *)opaque;
536 bool banked = exc_is_banked(irq);
537 VecInfo *vec;
538 bool targets_secure;
539
540 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
541 assert(!secure || banked);
542
543 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
544
545 targets_secure = banked ? secure : exc_targets_secure(s, irq);
546
547 trace_nvic_set_pending(irq, secure, targets_secure,
548 derived, vec->enabled, vec->prio);
549
550 if (derived) {
551
552 assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV);
553
554 if (irq == ARMV7M_EXCP_DEBUG &&
555 exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) {
556
557
558
559 return;
560 }
561
562 if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) {
563
564
565
566
567
568
569
570
571
572
573
574 cpu_abort(&s->cpu->parent_obj,
575 "Lockup: can't take terminal derived exception "
576 "(original exception priority %d)\n",
577 s->vectpending_prio);
578 }
579
580
581
582
583
584
585 }
586
587 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
588
589
590
591
592
593
594
595
596
597
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599
600
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602
603
604
605
606
607
608 int running = nvic_exec_prio(s);
609 bool escalate = false;
610
611 if (exc_group_prio(s, vec->prio, secure) >= running) {
612 trace_nvic_escalate_prio(irq, vec->prio, running);
613 escalate = true;
614 } else if (!vec->enabled) {
615 trace_nvic_escalate_disabled(irq);
616 escalate = true;
617 }
618
619 if (escalate) {
620
621
622
623
624
625
626 irq = ARMV7M_EXCP_HARD;
627 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
628 (targets_secure ||
629 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
630 vec = &s->sec_vectors[irq];
631 } else {
632 vec = &s->vectors[irq];
633 }
634 if (running <= vec->prio) {
635
636
637
638
639
640 cpu_abort(&s->cpu->parent_obj,
641 "Lockup: can't escalate %d to HardFault "
642 "(current priority %d)\n", irq, running);
643 }
644
645
646 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
647 }
648 }
649
650 if (!vec->pending) {
651 vec->pending = 1;
652 nvic_irq_update(s);
653 }
654}
655
656void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
657{
658 do_armv7m_nvic_set_pending(opaque, irq, secure, false);
659}
660
661void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
662{
663 do_armv7m_nvic_set_pending(opaque, irq, secure, true);
664}
665
666void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
667{
668
669
670
671
672
673
674 NVICState *s = (NVICState *)opaque;
675 bool banked = exc_is_banked(irq);
676 VecInfo *vec;
677 bool targets_secure;
678 bool escalate = false;
679
680
681
682
683
684 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S];
685 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure];
686
687 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
688 assert(!secure || banked);
689
690 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
691
692 targets_secure = banked ? secure : exc_targets_secure(s, irq);
693
694 switch (irq) {
695 case ARMV7M_EXCP_DEBUG:
696 if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) {
697
698 return;
699 }
700 break;
701 case ARMV7M_EXCP_MEM:
702 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK);
703 break;
704 case ARMV7M_EXCP_USAGE:
705 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK);
706 break;
707 case ARMV7M_EXCP_BUS:
708 escalate = !(fpccr_s & R_V7M_FPCCR_BFRDY_MASK);
709 break;
710 case ARMV7M_EXCP_SECURE:
711 escalate = !(fpccr_s & R_V7M_FPCCR_SFRDY_MASK);
712 break;
713 default:
714 g_assert_not_reached();
715 }
716
717 if (escalate) {
718
719
720
721
722 irq = ARMV7M_EXCP_HARD;
723 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
724 (targets_secure ||
725 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
726 vec = &s->sec_vectors[irq];
727 } else {
728 vec = &s->vectors[irq];
729 }
730 }
731
732 if (!vec->enabled ||
733 nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) {
734 if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) {
735
736
737
738
739 cpu_abort(&s->cpu->parent_obj,
740 "Lockup: can't escalate to HardFault during "
741 "lazy FP register stacking\n");
742 }
743 }
744
745 if (escalate) {
746 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
747 }
748 if (!vec->pending) {
749 vec->pending = 1;
750
751
752
753
754
755
756
757
758 nvic_recompute_state(s);
759 }
760}
761
762
763void armv7m_nvic_acknowledge_irq(void *opaque)
764{
765 NVICState *s = (NVICState *)opaque;
766 CPUARMState *env = &s->cpu->env;
767 const int pending = s->vectpending;
768 const int running = nvic_exec_prio(s);
769 VecInfo *vec;
770
771 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
772
773 if (s->vectpending_is_s_banked) {
774 vec = &s->sec_vectors[pending];
775 } else {
776 vec = &s->vectors[pending];
777 }
778
779 assert(vec->enabled);
780 assert(vec->pending);
781
782 assert(s->vectpending_prio < running);
783
784 trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
785
786 vec->active = 1;
787 vec->pending = 0;
788
789 write_v7m_exception(env, s->vectpending);
790
791 nvic_irq_update(s);
792}
793
794void armv7m_nvic_get_pending_irq_info(void *opaque,
795 int *pirq, bool *ptargets_secure)
796{
797 NVICState *s = (NVICState *)opaque;
798 const int pending = s->vectpending;
799 bool targets_secure;
800
801 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
802
803 if (s->vectpending_is_s_banked) {
804 targets_secure = true;
805 } else {
806 targets_secure = !exc_is_banked(pending) &&
807 exc_targets_secure(s, pending);
808 }
809
810 trace_nvic_get_pending_irq_info(pending, targets_secure);
811
812 *ptargets_secure = targets_secure;
813 *pirq = pending;
814}
815
816int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
817{
818 NVICState *s = (NVICState *)opaque;
819 VecInfo *vec = NULL;
820 int ret;
821
822 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
823
824
825
826
827
828
829
830
831
832 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
833 switch (armv7m_nvic_raw_execution_priority(s)) {
834 case -1:
835 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
836 vec = &s->vectors[ARMV7M_EXCP_HARD];
837 } else {
838 vec = &s->sec_vectors[ARMV7M_EXCP_HARD];
839 }
840 break;
841 case -2:
842 vec = &s->vectors[ARMV7M_EXCP_NMI];
843 break;
844 case -3:
845 vec = &s->sec_vectors[ARMV7M_EXCP_HARD];
846 break;
847 default:
848 break;
849 }
850 }
851
852 if (!vec) {
853 if (secure && exc_is_banked(irq)) {
854 vec = &s->sec_vectors[irq];
855 } else {
856 vec = &s->vectors[irq];
857 }
858 }
859
860 trace_nvic_complete_irq(irq, secure);
861
862 if (!vec->active) {
863
864 return -1;
865 }
866
867
868
869
870
871
872
873
874
875 if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
876 ret = -1;
877 } else {
878 ret = nvic_rettobase(s);
879 }
880
881 vec->active = 0;
882 if (vec->level) {
883
884
885
886 assert(irq >= NVIC_FIRST_IRQ);
887 vec->pending = 1;
888 }
889
890 nvic_irq_update(s);
891
892 return ret;
893}
894
895bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
896{
897
898
899
900
901
902
903
904
905
906 NVICState *s = (NVICState *)opaque;
907 bool banked = exc_is_banked(irq);
908 VecInfo *vec;
909 int running = nvic_exec_prio(s);
910
911 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
912 assert(!secure || banked);
913
914
915
916
917
918
919 if (irq == ARMV7M_EXCP_HARD) {
920 return running > -1;
921 }
922
923 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
924
925 return vec->enabled &&
926 exc_group_prio(s, vec->prio, secure) < running;
927}
928
929
930static void set_irq_level(void *opaque, int n, int level)
931{
932 NVICState *s = opaque;
933 VecInfo *vec;
934
935 n += NVIC_FIRST_IRQ;
936
937 assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
938
939 trace_nvic_set_irq_level(n, level);
940
941
942
943
944
945
946
947
948 vec = &s->vectors[n];
949 if (level != vec->level) {
950 vec->level = level;
951 if (level) {
952 armv7m_nvic_set_pending(s, n, false);
953 }
954 }
955}
956
957
958static void nvic_nmi_trigger(void *opaque, int n, int level)
959{
960 NVICState *s = opaque;
961
962 trace_nvic_set_nmi_level(level);
963
964
965
966
967
968
969
970 if (level) {
971 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
972 }
973}
974
975static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
976{
977 ARMCPU *cpu = s->cpu;
978 uint32_t val;
979
980 switch (offset) {
981 case 4:
982 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
983 goto bad_offset;
984 }
985 return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
986 case 0xc:
987 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
988 goto bad_offset;
989 }
990
991
992
993 return 0;
994 case 0x380 ... 0x3bf:
995 {
996 int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
997 int i;
998
999 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1000 goto bad_offset;
1001 }
1002 if (!attrs.secure) {
1003 return 0;
1004 }
1005 val = 0;
1006 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
1007 if (s->itns[startvec + i]) {
1008 val |= (1 << i);
1009 }
1010 }
1011 return val;
1012 }
1013 case 0xd00:
1014 return cpu->midr;
1015 case 0xd04:
1016
1017 val = cpu->env.v7m.exception;
1018
1019 val |= (s->vectpending & 0xff) << 12;
1020
1021 if (nvic_isrpending(s)) {
1022 val |= (1 << 22);
1023 }
1024
1025 if (nvic_rettobase(s)) {
1026 val |= (1 << 11);
1027 }
1028 if (attrs.secure) {
1029
1030 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
1031 val |= (1 << 26);
1032 }
1033
1034 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
1035 val |= (1 << 28);
1036 }
1037 } else {
1038
1039 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
1040 val |= (1 << 26);
1041 }
1042
1043 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
1044 val |= (1 << 28);
1045 }
1046 }
1047
1048 if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))
1049 && s->vectors[ARMV7M_EXCP_NMI].pending) {
1050 val |= (1 << 31);
1051 }
1052
1053
1054 return val;
1055 case 0xd08:
1056 return cpu->env.v7m.vecbase[attrs.secure];
1057 case 0xd0c:
1058 val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
1059 if (attrs.secure) {
1060
1061 val |= cpu->env.v7m.aircr;
1062 } else {
1063 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1064
1065
1066
1067
1068 val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
1069 }
1070 }
1071 return val;
1072 case 0xd10:
1073 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1074 goto bad_offset;
1075 }
1076 return cpu->env.v7m.scr[attrs.secure];
1077 case 0xd14:
1078
1079
1080
1081 val = cpu->env.v7m.ccr[attrs.secure];
1082 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
1083 return val;
1084 case 0xd24:
1085 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1086 goto bad_offset;
1087 }
1088 val = 0;
1089 if (attrs.secure) {
1090 if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
1091 val |= (1 << 0);
1092 }
1093 if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
1094 val |= (1 << 2);
1095 }
1096 if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
1097 val |= (1 << 3);
1098 }
1099 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
1100 val |= (1 << 7);
1101 }
1102 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
1103 val |= (1 << 10);
1104 }
1105 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
1106 val |= (1 << 11);
1107 }
1108 if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
1109 val |= (1 << 12);
1110 }
1111 if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
1112 val |= (1 << 13);
1113 }
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
1115 val |= (1 << 15);
1116 }
1117 if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
1118 val |= (1 << 16);
1119 }
1120 if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
1121 val |= (1 << 18);
1122 }
1123 if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
1124 val |= (1 << 21);
1125 }
1126
1127 if (s->vectors[ARMV7M_EXCP_SECURE].active) {
1128 val |= (1 << 4);
1129 }
1130 if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
1131 val |= (1 << 19);
1132 }
1133 if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
1134 val |= (1 << 20);
1135 }
1136 } else {
1137 if (s->vectors[ARMV7M_EXCP_MEM].active) {
1138 val |= (1 << 0);
1139 }
1140 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1141
1142 if (s->vectors[ARMV7M_EXCP_HARD].active) {
1143 val |= (1 << 2);
1144 }
1145 if (s->vectors[ARMV7M_EXCP_HARD].pending) {
1146 val |= (1 << 21);
1147 }
1148 }
1149 if (s->vectors[ARMV7M_EXCP_USAGE].active) {
1150 val |= (1 << 3);
1151 }
1152 if (s->vectors[ARMV7M_EXCP_SVC].active) {
1153 val |= (1 << 7);
1154 }
1155 if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
1156 val |= (1 << 10);
1157 }
1158 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
1159 val |= (1 << 11);
1160 }
1161 if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
1162 val |= (1 << 12);
1163 }
1164 if (s->vectors[ARMV7M_EXCP_MEM].pending) {
1165 val |= (1 << 13);
1166 }
1167 if (s->vectors[ARMV7M_EXCP_SVC].pending) {
1168 val |= (1 << 15);
1169 }
1170 if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
1171 val |= (1 << 16);
1172 }
1173 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
1174 val |= (1 << 18);
1175 }
1176 }
1177 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1178 if (s->vectors[ARMV7M_EXCP_BUS].active) {
1179 val |= (1 << 1);
1180 }
1181 if (s->vectors[ARMV7M_EXCP_BUS].pending) {
1182 val |= (1 << 14);
1183 }
1184 if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
1185 val |= (1 << 17);
1186 }
1187 if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
1188 s->vectors[ARMV7M_EXCP_NMI].active) {
1189
1190 val |= (1 << 5);
1191 }
1192 }
1193
1194
1195 if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
1196 val |= (1 << 8);
1197 }
1198 return val;
1199 case 0xd2c:
1200 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1201 goto bad_offset;
1202 }
1203 return cpu->env.v7m.hfsr;
1204 case 0xd30:
1205 return cpu->env.v7m.dfsr;
1206 case 0xd34:
1207 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1208 goto bad_offset;
1209 }
1210 return cpu->env.v7m.mmfar[attrs.secure];
1211 case 0xd38:
1212 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1213 goto bad_offset;
1214 }
1215 if (!attrs.secure &&
1216 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1217 return 0;
1218 }
1219 return cpu->env.v7m.bfar;
1220 case 0xd3c:
1221
1222 qemu_log_mask(LOG_UNIMP,
1223 "Aux Fault status registers unimplemented\n");
1224 return 0;
1225 case 0xd40:
1226 return cpu->id_pfr0;
1227 case 0xd44:
1228 return cpu->id_pfr1;
1229 case 0xd48:
1230 return cpu->id_dfr0;
1231 case 0xd4c:
1232 return cpu->id_afr0;
1233 case 0xd50:
1234 return cpu->id_mmfr0;
1235 case 0xd54:
1236 return cpu->id_mmfr1;
1237 case 0xd58:
1238 return cpu->id_mmfr2;
1239 case 0xd5c:
1240 return cpu->id_mmfr3;
1241 case 0xd60:
1242 return cpu->isar.id_isar0;
1243 case 0xd64:
1244 return cpu->isar.id_isar1;
1245 case 0xd68:
1246 return cpu->isar.id_isar2;
1247 case 0xd6c:
1248 return cpu->isar.id_isar3;
1249 case 0xd70:
1250 return cpu->isar.id_isar4;
1251 case 0xd74:
1252 return cpu->isar.id_isar5;
1253 case 0xd78:
1254 return cpu->clidr;
1255 case 0xd7c:
1256 return cpu->ctr;
1257 case 0xd80:
1258 {
1259 int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK;
1260 return cpu->ccsidr[idx];
1261 }
1262 case 0xd84:
1263 return cpu->env.v7m.csselr[attrs.secure];
1264 case 0xd88:
1265 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1266 return 0;
1267 }
1268 return cpu->env.v7m.cpacr[attrs.secure];
1269 case 0xd8c:
1270 if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1271 return 0;
1272 }
1273 return cpu->env.v7m.nsacr;
1274
1275 case 0xd90:
1276
1277 return cpu->pmsav7_dregion << 8;
1278 break;
1279 case 0xd94:
1280 return cpu->env.v7m.mpu_ctrl[attrs.secure];
1281 case 0xd98:
1282 return cpu->env.pmsav7.rnr[attrs.secure];
1283 case 0xd9c:
1284 case 0xda4:
1285 case 0xdac:
1286 case 0xdb4:
1287 {
1288 int region = cpu->env.pmsav7.rnr[attrs.secure];
1289
1290 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1291
1292
1293
1294
1295
1296 int aliasno = (offset - 0xd9c) / 8;
1297 if (aliasno) {
1298 region = deposit32(region, 0, 2, aliasno);
1299 }
1300 if (region >= cpu->pmsav7_dregion) {
1301 return 0;
1302 }
1303 return cpu->env.pmsav8.rbar[attrs.secure][region];
1304 }
1305
1306 if (region >= cpu->pmsav7_dregion) {
1307 return 0;
1308 }
1309 return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
1310 }
1311 case 0xda0:
1312 case 0xda8:
1313 case 0xdb0:
1314 case 0xdb8:
1315 {
1316 int region = cpu->env.pmsav7.rnr[attrs.secure];
1317
1318 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1319
1320
1321
1322
1323 int aliasno = (offset - 0xda0) / 8;
1324 if (aliasno) {
1325 region = deposit32(region, 0, 2, aliasno);
1326 }
1327 if (region >= cpu->pmsav7_dregion) {
1328 return 0;
1329 }
1330 return cpu->env.pmsav8.rlar[attrs.secure][region];
1331 }
1332
1333 if (region >= cpu->pmsav7_dregion) {
1334 return 0;
1335 }
1336 return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
1337 (cpu->env.pmsav7.drsr[region] & 0xffff);
1338 }
1339 case 0xdc0:
1340 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1341 goto bad_offset;
1342 }
1343 return cpu->env.pmsav8.mair0[attrs.secure];
1344 case 0xdc4:
1345 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1346 goto bad_offset;
1347 }
1348 return cpu->env.pmsav8.mair1[attrs.secure];
1349 case 0xdd0:
1350 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1351 goto bad_offset;
1352 }
1353 if (!attrs.secure) {
1354 return 0;
1355 }
1356 return cpu->env.sau.ctrl;
1357 case 0xdd4:
1358 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1359 goto bad_offset;
1360 }
1361 if (!attrs.secure) {
1362 return 0;
1363 }
1364 return cpu->sau_sregion;
1365 case 0xdd8:
1366 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1367 goto bad_offset;
1368 }
1369 if (!attrs.secure) {
1370 return 0;
1371 }
1372 return cpu->env.sau.rnr;
1373 case 0xddc:
1374 {
1375 int region = cpu->env.sau.rnr;
1376
1377 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1378 goto bad_offset;
1379 }
1380 if (!attrs.secure) {
1381 return 0;
1382 }
1383 if (region >= cpu->sau_sregion) {
1384 return 0;
1385 }
1386 return cpu->env.sau.rbar[region];
1387 }
1388 case 0xde0:
1389 {
1390 int region = cpu->env.sau.rnr;
1391
1392 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1393 goto bad_offset;
1394 }
1395 if (!attrs.secure) {
1396 return 0;
1397 }
1398 if (region >= cpu->sau_sregion) {
1399 return 0;
1400 }
1401 return cpu->env.sau.rlar[region];
1402 }
1403 case 0xde4:
1404 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1405 goto bad_offset;
1406 }
1407 if (!attrs.secure) {
1408 return 0;
1409 }
1410 return cpu->env.v7m.sfsr;
1411 case 0xde8:
1412 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1413 goto bad_offset;
1414 }
1415 if (!attrs.secure) {
1416 return 0;
1417 }
1418 return cpu->env.v7m.sfar;
1419 case 0xf34:
1420 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1421 return 0;
1422 }
1423 if (attrs.secure) {
1424 return cpu->env.v7m.fpccr[M_REG_S];
1425 } else {
1426
1427
1428
1429
1430
1431
1432 uint32_t value = cpu->env.v7m.fpccr[M_REG_S];
1433 uint32_t mask = R_V7M_FPCCR_LSPEN_MASK |
1434 R_V7M_FPCCR_CLRONRET_MASK |
1435 R_V7M_FPCCR_MONRDY_MASK;
1436
1437 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
1438 mask |= R_V7M_FPCCR_BFRDY_MASK | R_V7M_FPCCR_HFRDY_MASK;
1439 }
1440
1441 value &= mask;
1442
1443 value |= cpu->env.v7m.fpccr[M_REG_NS];
1444 return value;
1445 }
1446 case 0xf38:
1447 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1448 return 0;
1449 }
1450 return cpu->env.v7m.fpcar[attrs.secure];
1451 case 0xf3c:
1452 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1453 return 0;
1454 }
1455 return cpu->env.v7m.fpdscr[attrs.secure];
1456 case 0xf40:
1457 return cpu->isar.mvfr0;
1458 case 0xf44:
1459 return cpu->isar.mvfr1;
1460 case 0xf48:
1461 return cpu->isar.mvfr2;
1462 default:
1463 bad_offset:
1464 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
1465 return 0;
1466 }
1467}
1468
1469static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
1470 MemTxAttrs attrs)
1471{
1472 ARMCPU *cpu = s->cpu;
1473
1474 switch (offset) {
1475 case 0xc:
1476 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1477 goto bad_offset;
1478 }
1479
1480 break;
1481 case 0x380 ... 0x3bf:
1482 {
1483 int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
1484 int i;
1485
1486 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1487 goto bad_offset;
1488 }
1489 if (!attrs.secure) {
1490 break;
1491 }
1492 for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
1493 s->itns[startvec + i] = (value >> i) & 1;
1494 }
1495 nvic_irq_update(s);
1496 break;
1497 }
1498 case 0xd04:
1499 if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
1500 if (value & (1 << 31)) {
1501 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
1502 } else if (value & (1 << 30) &&
1503 arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1504
1505 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
1506 }
1507 }
1508 if (value & (1 << 28)) {
1509 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
1510 } else if (value & (1 << 27)) {
1511 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
1512 }
1513 if (value & (1 << 26)) {
1514 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
1515 } else if (value & (1 << 25)) {
1516 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
1517 }
1518 break;
1519 case 0xd08:
1520 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
1521 break;
1522 case 0xd0c:
1523 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
1524 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
1525 if (attrs.secure ||
1526 !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
1527 qemu_irq_pulse(s->sysresetreq);
1528 }
1529 }
1530 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
1531 qemu_log_mask(LOG_GUEST_ERROR,
1532 "Setting VECTCLRACTIVE when not in DEBUG mode "
1533 "is UNPREDICTABLE\n");
1534 }
1535 if (value & R_V7M_AIRCR_VECTRESET_MASK) {
1536
1537 qemu_log_mask(LOG_GUEST_ERROR,
1538 "Setting VECTRESET when not in DEBUG mode "
1539 "is UNPREDICTABLE\n");
1540 }
1541 if (arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1542 s->prigroup[attrs.secure] =
1543 extract32(value,
1544 R_V7M_AIRCR_PRIGROUP_SHIFT,
1545 R_V7M_AIRCR_PRIGROUP_LENGTH);
1546 }
1547 if (attrs.secure) {
1548
1549 cpu->env.v7m.aircr = value &
1550 (R_V7M_AIRCR_SYSRESETREQS_MASK |
1551 R_V7M_AIRCR_BFHFNMINS_MASK |
1552 R_V7M_AIRCR_PRIS_MASK);
1553
1554
1555
1556
1557 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
1558 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
1559 s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
1560 } else {
1561 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
1562 s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
1563 }
1564 }
1565 nvic_irq_update(s);
1566 }
1567 break;
1568 case 0xd10:
1569 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1570 goto bad_offset;
1571 }
1572
1573
1574
1575
1576
1577 value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK);
1578 cpu->env.v7m.scr[attrs.secure] = value;
1579 break;
1580 case 0xd14:
1581 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1582 goto bad_offset;
1583 }
1584
1585
1586 value &= (R_V7M_CCR_STKALIGN_MASK |
1587 R_V7M_CCR_BFHFNMIGN_MASK |
1588 R_V7M_CCR_DIV_0_TRP_MASK |
1589 R_V7M_CCR_UNALIGN_TRP_MASK |
1590 R_V7M_CCR_USERSETMPEND_MASK |
1591 R_V7M_CCR_NONBASETHRDENA_MASK);
1592
1593 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1594
1595 value |= R_V7M_CCR_NONBASETHRDENA_MASK
1596 | R_V7M_CCR_STKALIGN_MASK;
1597 }
1598 if (attrs.secure) {
1599
1600 cpu->env.v7m.ccr[M_REG_NS] =
1601 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
1602 | (value & R_V7M_CCR_BFHFNMIGN_MASK);
1603 value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
1604 }
1605
1606 cpu->env.v7m.ccr[attrs.secure] = value;
1607 break;
1608 case 0xd24:
1609 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1610 goto bad_offset;
1611 }
1612 if (attrs.secure) {
1613 s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
1614
1615 s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
1616 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
1617 s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
1618 (value & (1 << 10)) != 0;
1619 s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
1620 (value & (1 << 11)) != 0;
1621 s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
1622 (value & (1 << 12)) != 0;
1623 s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
1624 s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
1625 s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
1626 s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
1627 s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
1628 (value & (1 << 18)) != 0;
1629 s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
1630
1631 s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
1632 s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
1633 s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
1634 } else {
1635 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
1636 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1637
1638 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
1639 }
1640 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
1641 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
1642 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
1643 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
1644 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
1645 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
1646 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
1647 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
1648 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
1649 }
1650 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1651 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
1652 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
1653 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
1654 }
1655
1656
1657
1658 if (!attrs.secure && cpu->env.v7m.secure &&
1659 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
1660 (value & (1 << 5)) == 0) {
1661 s->vectors[ARMV7M_EXCP_NMI].active = 0;
1662 }
1663
1664
1665
1666
1667
1668
1669 if (!attrs.secure && cpu->env.v7m.secure &&
1670 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
1671 (value & (1 << 2)) == 0) {
1672 s->vectors[ARMV7M_EXCP_HARD].active = 0;
1673 }
1674
1675
1676 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
1677 nvic_irq_update(s);
1678 break;
1679 case 0xd2c:
1680 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1681 goto bad_offset;
1682 }
1683 cpu->env.v7m.hfsr &= ~value;
1684 break;
1685 case 0xd30:
1686 cpu->env.v7m.dfsr &= ~value;
1687 break;
1688 case 0xd34:
1689 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1690 goto bad_offset;
1691 }
1692 cpu->env.v7m.mmfar[attrs.secure] = value;
1693 return;
1694 case 0xd38:
1695 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1696 goto bad_offset;
1697 }
1698 if (!attrs.secure &&
1699 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1700 return;
1701 }
1702 cpu->env.v7m.bfar = value;
1703 return;
1704 case 0xd3c:
1705 qemu_log_mask(LOG_UNIMP,
1706 "NVIC: Aux fault status registers unimplemented\n");
1707 break;
1708 case 0xd84:
1709 if (!arm_v7m_csselr_razwi(cpu)) {
1710 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK;
1711 }
1712 break;
1713 case 0xd88:
1714 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1715
1716 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
1717 }
1718 break;
1719 case 0xd8c:
1720 if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1721
1722 cpu->env.v7m.nsacr = value & (3 << 10);
1723 }
1724 break;
1725 case 0xd90:
1726 return;
1727 case 0xd94:
1728 if ((value &
1729 (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK))
1730 == R_V7M_MPU_CTRL_HFNMIENA_MASK) {
1731 qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
1732 "UNPREDICTABLE\n");
1733 }
1734 cpu->env.v7m.mpu_ctrl[attrs.secure]
1735 = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
1736 R_V7M_MPU_CTRL_HFNMIENA_MASK |
1737 R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
1738 tlb_flush(CPU(cpu));
1739 break;
1740 case 0xd98:
1741 if (value >= cpu->pmsav7_dregion) {
1742 qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %"
1743 PRIu32 "/%" PRIu32 "\n",
1744 value, cpu->pmsav7_dregion);
1745 } else {
1746 cpu->env.pmsav7.rnr[attrs.secure] = value;
1747 }
1748 break;
1749 case 0xd9c:
1750 case 0xda4:
1751 case 0xdac:
1752 case 0xdb4:
1753 {
1754 int region;
1755
1756 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1757
1758
1759
1760
1761
1762 int aliasno = (offset - 0xd9c) / 8;
1763
1764 region = cpu->env.pmsav7.rnr[attrs.secure];
1765 if (aliasno) {
1766 region = deposit32(region, 0, 2, aliasno);
1767 }
1768 if (region >= cpu->pmsav7_dregion) {
1769 return;
1770 }
1771 cpu->env.pmsav8.rbar[attrs.secure][region] = value;
1772 tlb_flush(CPU(cpu));
1773 return;
1774 }
1775
1776 if (value & (1 << 4)) {
1777
1778
1779
1780 region = extract32(value, 0, 4);
1781 if (region >= cpu->pmsav7_dregion) {
1782 qemu_log_mask(LOG_GUEST_ERROR,
1783 "MPU region out of range %u/%" PRIu32 "\n",
1784 region, cpu->pmsav7_dregion);
1785 return;
1786 }
1787 cpu->env.pmsav7.rnr[attrs.secure] = region;
1788 } else {
1789 region = cpu->env.pmsav7.rnr[attrs.secure];
1790 }
1791
1792 if (region >= cpu->pmsav7_dregion) {
1793 return;
1794 }
1795
1796 cpu->env.pmsav7.drbar[region] = value & ~0x1f;
1797 tlb_flush(CPU(cpu));
1798 break;
1799 }
1800 case 0xda0:
1801 case 0xda8:
1802 case 0xdb0:
1803 case 0xdb8:
1804 {
1805 int region = cpu->env.pmsav7.rnr[attrs.secure];
1806
1807 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1808
1809
1810
1811
1812 int aliasno = (offset - 0xd9c) / 8;
1813
1814 region = cpu->env.pmsav7.rnr[attrs.secure];
1815 if (aliasno) {
1816 region = deposit32(region, 0, 2, aliasno);
1817 }
1818 if (region >= cpu->pmsav7_dregion) {
1819 return;
1820 }
1821 cpu->env.pmsav8.rlar[attrs.secure][region] = value;
1822 tlb_flush(CPU(cpu));
1823 return;
1824 }
1825
1826 if (region >= cpu->pmsav7_dregion) {
1827 return;
1828 }
1829
1830 cpu->env.pmsav7.drsr[region] = value & 0xff3f;
1831 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f;
1832 tlb_flush(CPU(cpu));
1833 break;
1834 }
1835 case 0xdc0:
1836 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1837 goto bad_offset;
1838 }
1839 if (cpu->pmsav7_dregion) {
1840
1841 cpu->env.pmsav8.mair0[attrs.secure] = value;
1842 }
1843
1844
1845
1846 break;
1847 case 0xdc4:
1848 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1849 goto bad_offset;
1850 }
1851 if (cpu->pmsav7_dregion) {
1852
1853 cpu->env.pmsav8.mair1[attrs.secure] = value;
1854 }
1855
1856
1857
1858 break;
1859 case 0xdd0:
1860 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1861 goto bad_offset;
1862 }
1863 if (!attrs.secure) {
1864 return;
1865 }
1866 cpu->env.sau.ctrl = value & 3;
1867 break;
1868 case 0xdd4:
1869 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1870 goto bad_offset;
1871 }
1872 break;
1873 case 0xdd8:
1874 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1875 goto bad_offset;
1876 }
1877 if (!attrs.secure) {
1878 return;
1879 }
1880 if (value >= cpu->sau_sregion) {
1881 qemu_log_mask(LOG_GUEST_ERROR, "SAU region out of range %"
1882 PRIu32 "/%" PRIu32 "\n",
1883 value, cpu->sau_sregion);
1884 } else {
1885 cpu->env.sau.rnr = value;
1886 }
1887 break;
1888 case 0xddc:
1889 {
1890 int region = cpu->env.sau.rnr;
1891
1892 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1893 goto bad_offset;
1894 }
1895 if (!attrs.secure) {
1896 return;
1897 }
1898 if (region >= cpu->sau_sregion) {
1899 return;
1900 }
1901 cpu->env.sau.rbar[region] = value & ~0x1f;
1902 tlb_flush(CPU(cpu));
1903 break;
1904 }
1905 case 0xde0:
1906 {
1907 int region = cpu->env.sau.rnr;
1908
1909 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1910 goto bad_offset;
1911 }
1912 if (!attrs.secure) {
1913 return;
1914 }
1915 if (region >= cpu->sau_sregion) {
1916 return;
1917 }
1918 cpu->env.sau.rlar[region] = value & ~0x1c;
1919 tlb_flush(CPU(cpu));
1920 break;
1921 }
1922 case 0xde4:
1923 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1924 goto bad_offset;
1925 }
1926 if (!attrs.secure) {
1927 return;
1928 }
1929 cpu->env.v7m.sfsr &= ~value;
1930 break;
1931 case 0xde8:
1932 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1933 goto bad_offset;
1934 }
1935 if (!attrs.secure) {
1936 return;
1937 }
1938 cpu->env.v7m.sfsr = value;
1939 break;
1940 case 0xf00:
1941 {
1942 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
1943
1944 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
1945 goto bad_offset;
1946 }
1947
1948 if (excnum < s->num_irq) {
1949 armv7m_nvic_set_pending(s, excnum, false);
1950 }
1951 break;
1952 }
1953 case 0xf34:
1954 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1955
1956 uint32_t fpccr_s;
1957
1958 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1959
1960 value &= (R_V7M_FPCCR_LSPACT_MASK |
1961 R_V7M_FPCCR_USER_MASK |
1962 R_V7M_FPCCR_THREAD_MASK |
1963 R_V7M_FPCCR_HFRDY_MASK |
1964 R_V7M_FPCCR_MMRDY_MASK |
1965 R_V7M_FPCCR_BFRDY_MASK |
1966 R_V7M_FPCCR_MONRDY_MASK |
1967 R_V7M_FPCCR_LSPEN_MASK |
1968 R_V7M_FPCCR_ASPEN_MASK);
1969 }
1970 value &= ~R_V7M_FPCCR_RES0_MASK;
1971
1972 if (!attrs.secure) {
1973
1974 fpccr_s = cpu->env.v7m.fpccr[M_REG_S];
1975 if (!(fpccr_s & R_V7M_FPCCR_LSPENS_MASK)) {
1976 uint32_t lspen = FIELD_EX32(value, V7M_FPCCR, LSPEN);
1977 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, LSPEN, lspen);
1978 }
1979 if (!(fpccr_s & R_V7M_FPCCR_CLRONRETS_MASK)) {
1980 uint32_t cor = FIELD_EX32(value, V7M_FPCCR, CLRONRET);
1981 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, CLRONRET, cor);
1982 }
1983 if ((s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
1984 uint32_t hfrdy = FIELD_EX32(value, V7M_FPCCR, HFRDY);
1985 uint32_t bfrdy = FIELD_EX32(value, V7M_FPCCR, BFRDY);
1986 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, HFRDY, hfrdy);
1987 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, BFRDY, bfrdy);
1988 }
1989
1990 {
1991 uint32_t monrdy = FIELD_EX32(value, V7M_FPCCR, MONRDY);
1992 fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, MONRDY, monrdy);
1993 }
1994
1995
1996
1997
1998
1999 value &= R_V7M_FPCCR_BANKED_MASK;
2000 cpu->env.v7m.fpccr[M_REG_NS] = value;
2001 } else {
2002 fpccr_s = value;
2003 }
2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s;
2005 }
2006 break;
2007 case 0xf38:
2008 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
2009 value &= ~7;
2010 cpu->env.v7m.fpcar[attrs.secure] = value;
2011 }
2012 break;
2013 case 0xf3c:
2014 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
2015 value &= 0x07c00000;
2016 cpu->env.v7m.fpdscr[attrs.secure] = value;
2017 }
2018 break;
2019 case 0xf50:
2020 case 0xf58:
2021 case 0xf5c:
2022 case 0xf60:
2023 case 0xf64:
2024 case 0xf68:
2025 case 0xf6c:
2026 case 0xf70:
2027 case 0xf74:
2028 case 0xf78:
2029
2030 break;
2031 default:
2032 bad_offset:
2033 qemu_log_mask(LOG_GUEST_ERROR,
2034 "NVIC: Bad write offset 0x%x\n", offset);
2035 }
2036}
2037
2038static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
2039{
2040
2041 switch (offset) {
2042 case 0xf00:
2043
2044
2045
2046 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK;
2047 default:
2048
2049 return false;
2050 }
2051}
2052
2053static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
2054{
2055
2056
2057
2058
2059
2060 switch (exc) {
2061 case ARMV7M_EXCP_MEM:
2062 case ARMV7M_EXCP_USAGE:
2063 case ARMV7M_EXCP_SVC:
2064 case ARMV7M_EXCP_PENDSV:
2065 case ARMV7M_EXCP_SYSTICK:
2066
2067 return attrs.secure;
2068 case ARMV7M_EXCP_BUS:
2069
2070 if (!attrs.secure &&
2071 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
2072 return -1;
2073 }
2074 return M_REG_NS;
2075 case ARMV7M_EXCP_SECURE:
2076
2077 if (!attrs.secure) {
2078 return -1;
2079 }
2080 return M_REG_NS;
2081 case ARMV7M_EXCP_DEBUG:
2082
2083 return M_REG_NS;
2084 case 8 ... 10:
2085 case 13:
2086
2087 return -1;
2088 default:
2089
2090 g_assert_not_reached();
2091 }
2092}
2093
2094static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
2095 uint64_t *data, unsigned size,
2096 MemTxAttrs attrs)
2097{
2098 NVICState *s = (NVICState *)opaque;
2099 uint32_t offset = addr;
2100 unsigned i, startvec, end;
2101 uint32_t val;
2102
2103 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
2104
2105 return MEMTX_ERROR;
2106 }
2107
2108 switch (offset) {
2109
2110 case 0x100 ... 0x13f:
2111 offset += 0x80;
2112
2113 case 0x180 ... 0x1bf:
2114 val = 0;
2115 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
2116
2117 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
2118 if (s->vectors[startvec + i].enabled &&
2119 (attrs.secure || s->itns[startvec + i])) {
2120 val |= (1 << i);
2121 }
2122 }
2123 break;
2124 case 0x200 ... 0x23f:
2125 offset += 0x80;
2126
2127 case 0x280 ... 0x2bf:
2128 val = 0;
2129 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ;
2130 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
2131 if (s->vectors[startvec + i].pending &&
2132 (attrs.secure || s->itns[startvec + i])) {
2133 val |= (1 << i);
2134 }
2135 }
2136 break;
2137 case 0x300 ... 0x33f:
2138 val = 0;
2139
2140 if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) {
2141 break;
2142 }
2143
2144 startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ;
2145
2146 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
2147 if (s->vectors[startvec + i].active &&
2148 (attrs.secure || s->itns[startvec + i])) {
2149 val |= (1 << i);
2150 }
2151 }
2152 break;
2153 case 0x400 ... 0x5ef:
2154 val = 0;
2155 startvec = offset - 0x400 + NVIC_FIRST_IRQ;
2156
2157 for (i = 0; i < size && startvec + i < s->num_irq; i++) {
2158 if (attrs.secure || s->itns[startvec + i]) {
2159 val |= s->vectors[startvec + i].prio << (8 * i);
2160 }
2161 }
2162 break;
2163 case 0xd18 ... 0xd1b:
2164 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
2165 val = 0;
2166 break;
2167 }
2168
2169 case 0xd1c ... 0xd23:
2170 val = 0;
2171 for (i = 0; i < size; i++) {
2172 unsigned hdlidx = (offset - 0xd14) + i;
2173 int sbank = shpr_bank(s, hdlidx, attrs);
2174
2175 if (sbank < 0) {
2176 continue;
2177 }
2178 val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
2179 }
2180 break;
2181 case 0xd28 ... 0xd2b:
2182 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
2183 val = 0;
2184 break;
2185 };
2186
2187
2188
2189
2190
2191 val = s->cpu->env.v7m.cfsr[attrs.secure];
2192 if (!attrs.secure &&
2193 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
2194 val &= ~R_V7M_CFSR_BFSR_MASK;
2195 } else {
2196 val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
2197 }
2198 val = extract32(val, (offset - 0xd28) * 8, size * 8);
2199 break;
2200 case 0xfe0 ... 0xfff:
2201 if (offset & 3) {
2202 val = 0;
2203 } else {
2204 val = nvic_id[(offset - 0xfe0) >> 2];
2205 }
2206 break;
2207 default:
2208 if (size == 4) {
2209 val = nvic_readl(s, offset, attrs);
2210 } else {
2211 qemu_log_mask(LOG_GUEST_ERROR,
2212 "NVIC: Bad read of size %d at offset 0x%x\n",
2213 size, offset);
2214 val = 0;
2215 }
2216 }
2217
2218 trace_nvic_sysreg_read(addr, val, size);
2219 *data = val;
2220 return MEMTX_OK;
2221}
2222
2223static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
2224 uint64_t value, unsigned size,
2225 MemTxAttrs attrs)
2226{
2227 NVICState *s = (NVICState *)opaque;
2228 uint32_t offset = addr;
2229 unsigned i, startvec, end;
2230 unsigned setval = 0;
2231
2232 trace_nvic_sysreg_write(addr, value, size);
2233
2234 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
2235
2236 return MEMTX_ERROR;
2237 }
2238
2239 switch (offset) {
2240 case 0x100 ... 0x13f:
2241 offset += 0x80;
2242 setval = 1;
2243
2244 case 0x180 ... 0x1bf:
2245 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
2246
2247 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
2248 if (value & (1 << i) &&
2249 (attrs.secure || s->itns[startvec + i])) {
2250 s->vectors[startvec + i].enabled = setval;
2251 }
2252 }
2253 nvic_irq_update(s);
2254 goto exit_ok;
2255 case 0x200 ... 0x23f:
2256
2257
2258
2259 offset += 0x80;
2260 setval = 1;
2261
2262 case 0x280 ... 0x2bf:
2263 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ;
2264
2265 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
2266 if (value & (1 << i) &&
2267 (attrs.secure || s->itns[startvec + i])) {
2268 s->vectors[startvec + i].pending = setval;
2269 }
2270 }
2271 nvic_irq_update(s);
2272 goto exit_ok;
2273 case 0x300 ... 0x33f:
2274 goto exit_ok;
2275 case 0x400 ... 0x5ef:
2276 startvec = (offset - 0x400) + NVIC_FIRST_IRQ;
2277
2278 for (i = 0; i < size && startvec + i < s->num_irq; i++) {
2279 if (attrs.secure || s->itns[startvec + i]) {
2280 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
2281 }
2282 }
2283 nvic_irq_update(s);
2284 goto exit_ok;
2285 case 0xd18 ... 0xd1b:
2286 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
2287 goto exit_ok;
2288 }
2289
2290 case 0xd1c ... 0xd23:
2291 for (i = 0; i < size; i++) {
2292 unsigned hdlidx = (offset - 0xd14) + i;
2293 int newprio = extract32(value, i * 8, 8);
2294 int sbank = shpr_bank(s, hdlidx, attrs);
2295
2296 if (sbank < 0) {
2297 continue;
2298 }
2299 set_prio(s, hdlidx, sbank, newprio);
2300 }
2301 nvic_irq_update(s);
2302 goto exit_ok;
2303 case 0xd28 ... 0xd2b:
2304 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
2305 goto exit_ok;
2306 }
2307
2308
2309
2310 value <<= ((offset - 0xd28) * 8);
2311
2312 if (!attrs.secure &&
2313 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
2314
2315 value &= ~R_V7M_CFSR_BFSR_MASK;
2316 }
2317
2318 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
2319 if (attrs.secure) {
2320
2321
2322
2323 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
2324 }
2325 goto exit_ok;
2326 }
2327 if (size == 4) {
2328 nvic_writel(s, offset, value, attrs);
2329 goto exit_ok;
2330 }
2331 qemu_log_mask(LOG_GUEST_ERROR,
2332 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
2333
2334
2335 exit_ok:
2336
2337 arm_rebuild_hflags(&s->cpu->env);
2338 return MEMTX_OK;
2339}
2340
2341static const MemoryRegionOps nvic_sysreg_ops = {
2342 .read_with_attrs = nvic_sysreg_read,
2343 .write_with_attrs = nvic_sysreg_write,
2344 .endianness = DEVICE_NATIVE_ENDIAN,
2345};
2346
2347static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
2348 uint64_t value, unsigned size,
2349 MemTxAttrs attrs)
2350{
2351 MemoryRegion *mr = opaque;
2352
2353 if (attrs.secure) {
2354
2355 attrs.secure = 0;
2356 return memory_region_dispatch_write(mr, addr, value,
2357 size_memop(size) | MO_TE, attrs);
2358 } else {
2359
2360 if (attrs.user) {
2361 return MEMTX_ERROR;
2362 }
2363 return MEMTX_OK;
2364 }
2365}
2366
2367static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
2368 uint64_t *data, unsigned size,
2369 MemTxAttrs attrs)
2370{
2371 MemoryRegion *mr = opaque;
2372
2373 if (attrs.secure) {
2374
2375 attrs.secure = 0;
2376 return memory_region_dispatch_read(mr, addr, data,
2377 size_memop(size) | MO_TE, attrs);
2378 } else {
2379
2380 if (attrs.user) {
2381 return MEMTX_ERROR;
2382 }
2383 *data = 0;
2384 return MEMTX_OK;
2385 }
2386}
2387
2388static const MemoryRegionOps nvic_sysreg_ns_ops = {
2389 .read_with_attrs = nvic_sysreg_ns_read,
2390 .write_with_attrs = nvic_sysreg_ns_write,
2391 .endianness = DEVICE_NATIVE_ENDIAN,
2392};
2393
2394static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
2395 uint64_t value, unsigned size,
2396 MemTxAttrs attrs)
2397{
2398 NVICState *s = opaque;
2399 MemoryRegion *mr;
2400
2401
2402 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
2403 return memory_region_dispatch_write(mr, addr, value,
2404 size_memop(size) | MO_TE, attrs);
2405}
2406
2407static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
2408 uint64_t *data, unsigned size,
2409 MemTxAttrs attrs)
2410{
2411 NVICState *s = opaque;
2412 MemoryRegion *mr;
2413
2414
2415 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
2416 return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
2417 attrs);
2418}
2419
2420static const MemoryRegionOps nvic_systick_ops = {
2421 .read_with_attrs = nvic_systick_read,
2422 .write_with_attrs = nvic_systick_write,
2423 .endianness = DEVICE_NATIVE_ENDIAN,
2424};
2425
2426static int nvic_post_load(void *opaque, int version_id)
2427{
2428 NVICState *s = opaque;
2429 unsigned i;
2430 int resetprio;
2431
2432
2433 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
2434
2435 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
2436 s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
2437 s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
2438 return 1;
2439 }
2440 for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) {
2441 if (s->vectors[i].prio & ~0xff) {
2442 return 1;
2443 }
2444 }
2445
2446 nvic_recompute_state(s);
2447
2448 return 0;
2449}
2450
2451static const VMStateDescription vmstate_VecInfo = {
2452 .name = "armv7m_nvic_info",
2453 .version_id = 1,
2454 .minimum_version_id = 1,
2455 .fields = (VMStateField[]) {
2456 VMSTATE_INT16(prio, VecInfo),
2457 VMSTATE_UINT8(enabled, VecInfo),
2458 VMSTATE_UINT8(pending, VecInfo),
2459 VMSTATE_UINT8(active, VecInfo),
2460 VMSTATE_UINT8(level, VecInfo),
2461 VMSTATE_END_OF_LIST()
2462 }
2463};
2464
2465static bool nvic_security_needed(void *opaque)
2466{
2467 NVICState *s = opaque;
2468
2469 return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
2470}
2471
2472static int nvic_security_post_load(void *opaque, int version_id)
2473{
2474 NVICState *s = opaque;
2475 int i;
2476
2477
2478 if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
2479 && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
2480
2481
2482
2483
2484 return 1;
2485 }
2486 for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
2487 if (s->sec_vectors[i].prio & ~0xff) {
2488 return 1;
2489 }
2490 }
2491 return 0;
2492}
2493
2494static const VMStateDescription vmstate_nvic_security = {
2495 .name = "armv7m_nvic/m-security",
2496 .version_id = 1,
2497 .minimum_version_id = 1,
2498 .needed = nvic_security_needed,
2499 .post_load = &nvic_security_post_load,
2500 .fields = (VMStateField[]) {
2501 VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
2502 vmstate_VecInfo, VecInfo),
2503 VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
2504 VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
2505 VMSTATE_END_OF_LIST()
2506 }
2507};
2508
2509static const VMStateDescription vmstate_nvic = {
2510 .name = "armv7m_nvic",
2511 .version_id = 4,
2512 .minimum_version_id = 4,
2513 .post_load = &nvic_post_load,
2514 .fields = (VMStateField[]) {
2515 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
2516 vmstate_VecInfo, VecInfo),
2517 VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
2518 VMSTATE_END_OF_LIST()
2519 },
2520 .subsections = (const VMStateDescription*[]) {
2521 &vmstate_nvic_security,
2522 NULL
2523 }
2524};
2525
2526static Property props_nvic[] = {
2527
2528 DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
2529 DEFINE_PROP_END_OF_LIST()
2530};
2531
2532static void armv7m_nvic_reset(DeviceState *dev)
2533{
2534 int resetprio;
2535 NVICState *s = NVIC(dev);
2536
2537 memset(s->vectors, 0, sizeof(s->vectors));
2538 memset(s->sec_vectors, 0, sizeof(s->sec_vectors));
2539 s->prigroup[M_REG_NS] = 0;
2540 s->prigroup[M_REG_S] = 0;
2541
2542 s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
2543
2544
2545
2546 s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
2547 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
2548 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
2549
2550
2551 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0;
2552
2553 resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
2554 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
2555 s->vectors[ARMV7M_EXCP_NMI].prio = -2;
2556 s->vectors[ARMV7M_EXCP_HARD].prio = -1;
2557
2558 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
2559 s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
2560 s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
2561 s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
2562 s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
2563
2564
2565 s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
2566
2567 s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
2568 } else {
2569 s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
2570 }
2571
2572
2573
2574
2575
2576
2577
2578 s->exception_prio = NVIC_NOEXC_PRIO;
2579 s->vectpending = 0;
2580 s->vectpending_is_s_banked = false;
2581 s->vectpending_prio = NVIC_NOEXC_PRIO;
2582
2583 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
2584 memset(s->itns, 0, sizeof(s->itns));
2585 } else {
2586
2587
2588
2589
2590 int i;
2591
2592 for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
2593 s->itns[i] = true;
2594 }
2595 }
2596}
2597
2598static void nvic_systick_trigger(void *opaque, int n, int level)
2599{
2600 NVICState *s = opaque;
2601
2602 if (level) {
2603
2604
2605
2606
2607
2608
2609 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n);
2610 }
2611}
2612
2613static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
2614{
2615 NVICState *s = NVIC(dev);
2616 Error *err = NULL;
2617 int regionlen;
2618
2619
2620 if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
2621 error_setg(errp, "The NVIC can only be used with a Cortex-M CPU");
2622 return;
2623 }
2624
2625 if (s->num_irq > NVIC_MAX_IRQ) {
2626 error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq);
2627 return;
2628 }
2629
2630 qdev_init_gpio_in(dev, set_irq_level, s->num_irq);
2631
2632
2633 s->num_irq += NVIC_FIRST_IRQ;
2634
2635 s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
2636
2637 object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true,
2638 "realized", &err);
2639 if (err != NULL) {
2640 error_propagate(errp, err);
2641 return;
2642 }
2643 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
2644 qdev_get_gpio_in_named(dev, "systick-trigger",
2645 M_REG_NS));
2646
2647 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
2648
2649
2650
2651
2652 sysbus_init_child_obj(OBJECT(dev), "systick-reg-s",
2653 &s->systick[M_REG_S],
2654 sizeof(s->systick[M_REG_S]), TYPE_SYSTICK);
2655
2656 object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true,
2657 "realized", &err);
2658 if (err != NULL) {
2659 error_propagate(errp, err);
2660 return;
2661 }
2662 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
2663 qdev_get_gpio_in_named(dev, "systick-trigger",
2664 M_REG_S));
2665 }
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691 regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
2692 memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
2693
2694
2695
2696 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
2697 "nvic_sysregs", 0x1000);
2698 memory_region_add_subregion(&s->container, 0, &s->sysregmem);
2699
2700 memory_region_init_io(&s->systickmem, OBJECT(s),
2701 &nvic_systick_ops, s,
2702 "nvic_systick", 0xe0);
2703
2704 memory_region_add_subregion_overlap(&s->container, 0x10,
2705 &s->systickmem, 1);
2706
2707 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
2708 memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
2709 &nvic_sysreg_ns_ops, &s->sysregmem,
2710 "nvic_sysregs_ns", 0x1000);
2711 memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
2712 memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
2713 &nvic_sysreg_ns_ops, &s->systickmem,
2714 "nvic_systick_ns", 0xe0);
2715 memory_region_add_subregion_overlap(&s->container, 0x20010,
2716 &s->systick_ns_mem, 1);
2717 }
2718
2719 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
2720}
2721
2722static void armv7m_nvic_instance_init(Object *obj)
2723{
2724
2725
2726
2727
2728
2729
2730 DeviceState *dev = DEVICE(obj);
2731 NVICState *nvic = NVIC(obj);
2732 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2733
2734 sysbus_init_child_obj(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
2735 sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK);
2736
2737
2738
2739
2740 sysbus_init_irq(sbd, &nvic->excpout);
2741 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
2742 qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger",
2743 M_REG_NUM_BANKS);
2744 qdev_init_gpio_in_named(dev, nvic_nmi_trigger, "NMI", 1);
2745}
2746
2747static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
2748{
2749 DeviceClass *dc = DEVICE_CLASS(klass);
2750
2751 dc->vmsd = &vmstate_nvic;
2752 dc->props = props_nvic;
2753 dc->reset = armv7m_nvic_reset;
2754 dc->realize = armv7m_nvic_realize;
2755}
2756
2757static const TypeInfo armv7m_nvic_info = {
2758 .name = TYPE_NVIC,
2759 .parent = TYPE_SYS_BUS_DEVICE,
2760 .instance_init = armv7m_nvic_instance_init,
2761 .instance_size = sizeof(NVICState),
2762 .class_init = armv7m_nvic_class_init,
2763 .class_size = sizeof(SysBusDeviceClass),
2764};
2765
2766static void armv7m_nvic_register_types(void)
2767{
2768 type_register_static(&armv7m_nvic_info);
2769}
2770
2771type_init(armv7m_nvic_register_types)
2772