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25#include "qemu/osdep.h"
26#include <zlib.h>
27
28#include "hw/irq.h"
29#include "hw/net/cadence_gem.h"
30#include "hw/qdev-properties.h"
31#include "migration/vmstate.h"
32#include "qapi/error.h"
33#include "qemu/log.h"
34#include "qemu/module.h"
35#include "sysemu/dma.h"
36#include "net/checksum.h"
37
38#ifdef CADENCE_GEM_ERR_DEBUG
39#define DB_PRINT(...) do { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } while (0)
43#else
44 #define DB_PRINT(...)
45#endif
46
47#define GEM_NWCTRL (0x00000000/4)
48#define GEM_NWCFG (0x00000004/4)
49#define GEM_NWSTATUS (0x00000008/4)
50#define GEM_USERIO (0x0000000C/4)
51#define GEM_DMACFG (0x00000010/4)
52#define GEM_TXSTATUS (0x00000014/4)
53#define GEM_RXQBASE (0x00000018/4)
54#define GEM_TXQBASE (0x0000001C/4)
55#define GEM_RXSTATUS (0x00000020/4)
56#define GEM_ISR (0x00000024/4)
57#define GEM_IER (0x00000028/4)
58#define GEM_IDR (0x0000002C/4)
59#define GEM_IMR (0x00000030/4)
60#define GEM_PHYMNTNC (0x00000034/4)
61#define GEM_RXPAUSE (0x00000038/4)
62#define GEM_TXPAUSE (0x0000003C/4)
63#define GEM_TXPARTIALSF (0x00000040/4)
64#define GEM_RXPARTIALSF (0x00000044/4)
65#define GEM_HASHLO (0x00000080/4)
66#define GEM_HASHHI (0x00000084/4)
67#define GEM_SPADDR1LO (0x00000088/4)
68#define GEM_SPADDR1HI (0x0000008C/4)
69#define GEM_SPADDR2LO (0x00000090/4)
70#define GEM_SPADDR2HI (0x00000094/4)
71#define GEM_SPADDR3LO (0x00000098/4)
72#define GEM_SPADDR3HI (0x0000009C/4)
73#define GEM_SPADDR4LO (0x000000A0/4)
74#define GEM_SPADDR4HI (0x000000A4/4)
75#define GEM_TIDMATCH1 (0x000000A8/4)
76#define GEM_TIDMATCH2 (0x000000AC/4)
77#define GEM_TIDMATCH3 (0x000000B0/4)
78#define GEM_TIDMATCH4 (0x000000B4/4)
79#define GEM_WOLAN (0x000000B8/4)
80#define GEM_IPGSTRETCH (0x000000BC/4)
81#define GEM_SVLAN (0x000000C0/4)
82#define GEM_MODID (0x000000FC/4)
83#define GEM_OCTTXLO (0x00000100/4)
84#define GEM_OCTTXHI (0x00000104/4)
85#define GEM_TXCNT (0x00000108/4)
86#define GEM_TXBCNT (0x0000010C/4)
87#define GEM_TXMCNT (0x00000110/4)
88#define GEM_TXPAUSECNT (0x00000114/4)
89#define GEM_TX64CNT (0x00000118/4)
90#define GEM_TX65CNT (0x0000011C/4)
91#define GEM_TX128CNT (0x00000120/4)
92#define GEM_TX256CNT (0x00000124/4)
93#define GEM_TX512CNT (0x00000128/4)
94#define GEM_TX1024CNT (0x0000012C/4)
95#define GEM_TX1519CNT (0x00000130/4)
96#define GEM_TXURUNCNT (0x00000134/4)
97#define GEM_SINGLECOLLCNT (0x00000138/4)
98#define GEM_MULTCOLLCNT (0x0000013C/4)
99#define GEM_EXCESSCOLLCNT (0x00000140/4)
100#define GEM_LATECOLLCNT (0x00000144/4)
101#define GEM_DEFERTXCNT (0x00000148/4)
102#define GEM_CSENSECNT (0x0000014C/4)
103#define GEM_OCTRXLO (0x00000150/4)
104#define GEM_OCTRXHI (0x00000154/4)
105#define GEM_RXCNT (0x00000158/4)
106#define GEM_RXBROADCNT (0x0000015C/4)
107#define GEM_RXMULTICNT (0x00000160/4)
108#define GEM_RXPAUSECNT (0x00000164/4)
109#define GEM_RX64CNT (0x00000168/4)
110#define GEM_RX65CNT (0x0000016C/4)
111#define GEM_RX128CNT (0x00000170/4)
112#define GEM_RX256CNT (0x00000174/4)
113#define GEM_RX512CNT (0x00000178/4)
114#define GEM_RX1024CNT (0x0000017C/4)
115#define GEM_RX1519CNT (0x00000180/4)
116#define GEM_RXUNDERCNT (0x00000184/4)
117#define GEM_RXOVERCNT (0x00000188/4)
118#define GEM_RXJABCNT (0x0000018C/4)
119#define GEM_RXFCSCNT (0x00000190/4)
120#define GEM_RXLENERRCNT (0x00000194/4)
121#define GEM_RXSYMERRCNT (0x00000198/4)
122#define GEM_RXALIGNERRCNT (0x0000019C/4)
123#define GEM_RXRSCERRCNT (0x000001A0/4)
124#define GEM_RXORUNCNT (0x000001A4/4)
125#define GEM_RXIPCSERRCNT (0x000001A8/4)
126#define GEM_RXTCPCCNT (0x000001AC/4)
127#define GEM_RXUDPCCNT (0x000001B0/4)
128
129#define GEM_1588S (0x000001D0/4)
130#define GEM_1588NS (0x000001D4/4)
131#define GEM_1588ADJ (0x000001D8/4)
132#define GEM_1588INC (0x000001DC/4)
133#define GEM_PTPETXS (0x000001E0/4)
134#define GEM_PTPETXNS (0x000001E4/4)
135#define GEM_PTPERXS (0x000001E8/4)
136#define GEM_PTPERXNS (0x000001EC/4)
137#define GEM_PTPPTXS (0x000001E0/4)
138#define GEM_PTPPTXNS (0x000001E4/4)
139#define GEM_PTPPRXS (0x000001E8/4)
140#define GEM_PTPPRXNS (0x000001EC/4)
141
142
143#define GEM_DESCONF (0x00000280/4)
144#define GEM_DESCONF2 (0x00000284/4)
145#define GEM_DESCONF3 (0x00000288/4)
146#define GEM_DESCONF4 (0x0000028C/4)
147#define GEM_DESCONF5 (0x00000290/4)
148#define GEM_DESCONF6 (0x00000294/4)
149#define GEM_DESCONF6_64B_MASK (1U << 23)
150#define GEM_DESCONF7 (0x00000298/4)
151
152#define GEM_INT_Q1_STATUS (0x00000400 / 4)
153#define GEM_INT_Q1_MASK (0x00000640 / 4)
154
155#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
156#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
157
158#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
159#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
160
161#define GEM_TBQPH (0x000004C8 / 4)
162#define GEM_RBQPH (0x000004D4 / 4)
163
164#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
165#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
166
167#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
168#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
169
170#define GEM_INT_Q1_MASK (0x00000640 / 4)
171#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
172
173#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
174
175#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
176#define GEM_ST1R_DSTC_ENABLE (1 << 28)
177#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
178#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
179#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
180#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
181#define GEM_ST1R_QUEUE_SHIFT (0)
182#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
183
184#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
185
186#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
187#define GEM_ST2R_COMPARE_A_SHIFT (13)
188#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
189#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
190#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
191#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
192 + 1)
193#define GEM_ST2R_QUEUE_SHIFT (0)
194#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
195
196#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
197#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
198
199#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
200#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
201#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
202#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
203
204
205#define GEM_NWCTRL_TXSTART 0x00000200
206#define GEM_NWCTRL_TXENA 0x00000008
207#define GEM_NWCTRL_RXENA 0x00000004
208#define GEM_NWCTRL_LOCALLOOP 0x00000002
209
210#define GEM_NWCFG_STRIP_FCS 0x00020000
211#define GEM_NWCFG_LERR_DISC 0x00010000
212#define GEM_NWCFG_BUFF_OFST_M 0x0000C000
213#define GEM_NWCFG_BUFF_OFST_S 14
214#define GEM_NWCFG_UCAST_HASH 0x00000080
215#define GEM_NWCFG_MCAST_HASH 0x00000040
216#define GEM_NWCFG_BCAST_REJ 0x00000020
217#define GEM_NWCFG_PROMISC 0x00000010
218
219#define GEM_DMACFG_ADDR_64B (1U << 30)
220#define GEM_DMACFG_TX_BD_EXT (1U << 29)
221#define GEM_DMACFG_RX_BD_EXT (1U << 28)
222#define GEM_DMACFG_RBUFSZ_M 0x00FF0000
223#define GEM_DMACFG_RBUFSZ_S 16
224#define GEM_DMACFG_RBUFSZ_MUL 64
225#define GEM_DMACFG_TXCSUM_OFFL 0x00000800
226
227#define GEM_TXSTATUS_TXCMPL 0x00000020
228#define GEM_TXSTATUS_USED 0x00000001
229
230#define GEM_RXSTATUS_FRMRCVD 0x00000002
231#define GEM_RXSTATUS_NOBUF 0x00000001
232
233
234#define GEM_INT_TXCMPL 0x00000080
235#define GEM_INT_TXUSED 0x00000008
236#define GEM_INT_RXUSED 0x00000004
237#define GEM_INT_RXCMPL 0x00000002
238
239#define GEM_PHYMNTNC_OP_R 0x20000000
240#define GEM_PHYMNTNC_OP_W 0x10000000
241#define GEM_PHYMNTNC_ADDR 0x0F800000
242#define GEM_PHYMNTNC_ADDR_SHFT 23
243#define GEM_PHYMNTNC_REG 0x007C0000
244#define GEM_PHYMNTNC_REG_SHIFT 18
245
246
247#define BOARD_PHY_ADDRESS 23
248
249#define PHY_REG_CONTROL 0
250#define PHY_REG_STATUS 1
251#define PHY_REG_PHYID1 2
252#define PHY_REG_PHYID2 3
253#define PHY_REG_ANEGADV 4
254#define PHY_REG_LINKPABIL 5
255#define PHY_REG_ANEGEXP 6
256#define PHY_REG_NEXTP 7
257#define PHY_REG_LINKPNEXTP 8
258#define PHY_REG_100BTCTRL 9
259#define PHY_REG_1000BTSTAT 10
260#define PHY_REG_EXTSTAT 15
261#define PHY_REG_PHYSPCFC_CTL 16
262#define PHY_REG_PHYSPCFC_ST 17
263#define PHY_REG_INT_EN 18
264#define PHY_REG_INT_ST 19
265#define PHY_REG_EXT_PHYSPCFC_CTL 20
266#define PHY_REG_RXERR 21
267#define PHY_REG_EACD 22
268#define PHY_REG_LED 24
269#define PHY_REG_LED_OVRD 25
270#define PHY_REG_EXT_PHYSPCFC_CTL2 26
271#define PHY_REG_EXT_PHYSPCFC_ST 27
272#define PHY_REG_CABLE_DIAG 28
273
274#define PHY_REG_CONTROL_RST 0x8000
275#define PHY_REG_CONTROL_LOOP 0x4000
276#define PHY_REG_CONTROL_ANEG 0x1000
277#define PHY_REG_CONTROL_ANRESTART 0x0200
278
279#define PHY_REG_STATUS_LINK 0x0004
280#define PHY_REG_STATUS_ANEGCMPL 0x0020
281
282#define PHY_REG_INT_ST_ANEGCMPL 0x0800
283#define PHY_REG_INT_ST_LINKC 0x0400
284#define PHY_REG_INT_ST_ENERGY 0x0010
285
286
287#define GEM_RX_REJECT (-1)
288#define GEM_RX_PROMISCUOUS_ACCEPT (-2)
289#define GEM_RX_BROADCAST_ACCEPT (-3)
290#define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
291#define GEM_RX_UNICAST_HASH_ACCEPT (-5)
292
293#define GEM_RX_SAR_ACCEPT 0
294
295
296
297#define DESC_1_USED 0x80000000
298#define DESC_1_LENGTH 0x00001FFF
299
300#define DESC_1_TX_WRAP 0x40000000
301#define DESC_1_TX_LAST 0x00008000
302
303#define DESC_0_RX_WRAP 0x00000002
304#define DESC_0_RX_OWNERSHIP 0x00000001
305
306#define R_DESC_1_RX_SAR_SHIFT 25
307#define R_DESC_1_RX_SAR_LENGTH 2
308#define R_DESC_1_RX_SAR_MATCH (1 << 27)
309#define R_DESC_1_RX_UNICAST_HASH (1 << 29)
310#define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
311#define R_DESC_1_RX_BROADCAST (1 << 31)
312
313#define DESC_1_RX_SOF 0x00004000
314#define DESC_1_RX_EOF 0x00008000
315
316#define GEM_MODID_VALUE 0x00020118
317
318static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
319{
320 uint64_t ret = desc[0];
321
322 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
323 ret |= (uint64_t)desc[2] << 32;
324 }
325 return ret;
326}
327
328static inline unsigned tx_desc_get_used(uint32_t *desc)
329{
330 return (desc[1] & DESC_1_USED) ? 1 : 0;
331}
332
333static inline void tx_desc_set_used(uint32_t *desc)
334{
335 desc[1] |= DESC_1_USED;
336}
337
338static inline unsigned tx_desc_get_wrap(uint32_t *desc)
339{
340 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
341}
342
343static inline unsigned tx_desc_get_last(uint32_t *desc)
344{
345 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
346}
347
348static inline void tx_desc_set_last(uint32_t *desc)
349{
350 desc[1] |= DESC_1_TX_LAST;
351}
352
353static inline unsigned tx_desc_get_length(uint32_t *desc)
354{
355 return desc[1] & DESC_1_LENGTH;
356}
357
358static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
359{
360 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
361 DB_PRINT("bufaddr: 0x%08x\n", *desc);
362 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
363 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
364 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
365 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
366}
367
368static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
369{
370 uint64_t ret = desc[0] & ~0x3UL;
371
372 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
373 ret |= (uint64_t)desc[2] << 32;
374 }
375 return ret;
376}
377
378static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
379{
380 int ret = 2;
381
382 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
383 ret += 2;
384 }
385 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
386 : GEM_DMACFG_TX_BD_EXT)) {
387 ret += 2;
388 }
389
390 assert(ret <= DESC_MAX_NUM_WORDS);
391 return ret;
392}
393
394static inline unsigned rx_desc_get_wrap(uint32_t *desc)
395{
396 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
397}
398
399static inline unsigned rx_desc_get_ownership(uint32_t *desc)
400{
401 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
402}
403
404static inline void rx_desc_set_ownership(uint32_t *desc)
405{
406 desc[0] |= DESC_0_RX_OWNERSHIP;
407}
408
409static inline void rx_desc_set_sof(uint32_t *desc)
410{
411 desc[1] |= DESC_1_RX_SOF;
412}
413
414static inline void rx_desc_set_eof(uint32_t *desc)
415{
416 desc[1] |= DESC_1_RX_EOF;
417}
418
419static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
420{
421 desc[1] &= ~DESC_1_LENGTH;
422 desc[1] |= len;
423}
424
425static inline void rx_desc_set_broadcast(uint32_t *desc)
426{
427 desc[1] |= R_DESC_1_RX_BROADCAST;
428}
429
430static inline void rx_desc_set_unicast_hash(uint32_t *desc)
431{
432 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
433}
434
435static inline void rx_desc_set_multicast_hash(uint32_t *desc)
436{
437 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
438}
439
440static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
441{
442 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
443 sar_idx);
444 desc[1] |= R_DESC_1_RX_SAR_MATCH;
445}
446
447
448static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
449
450
451
452
453
454
455static void gem_init_register_masks(CadenceGEMState *s)
456{
457
458 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
459 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
460 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
461 s->regs_ro[GEM_DMACFG] = 0x8E00F000;
462 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
463 s->regs_ro[GEM_RXQBASE] = 0x00000003;
464 s->regs_ro[GEM_TXQBASE] = 0x00000003;
465 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
466 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
467 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
468 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
469
470
471 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
472 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
473
474
475 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
476 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
477 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
478
479
480 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
481 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
482 s->regs_wo[GEM_IER] = 0x07FFFFFF;
483 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
484}
485
486
487
488
489
490static void phy_update_link(CadenceGEMState *s)
491{
492 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
493
494
495 if (qemu_get_queue(s->nic)->link_down) {
496 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
497 PHY_REG_STATUS_LINK);
498 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
499 } else {
500 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
501 PHY_REG_STATUS_LINK);
502 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
503 PHY_REG_INT_ST_ANEGCMPL |
504 PHY_REG_INT_ST_ENERGY);
505 }
506}
507
508static int gem_can_receive(NetClientState *nc)
509{
510 CadenceGEMState *s;
511 int i;
512
513 s = qemu_get_nic_opaque(nc);
514
515
516 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
517 if (s->can_rx_state != 1) {
518 s->can_rx_state = 1;
519 DB_PRINT("can't receive - no enable\n");
520 }
521 return 0;
522 }
523
524 for (i = 0; i < s->num_priority_queues; i++) {
525 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
526 break;
527 }
528 };
529
530 if (i == s->num_priority_queues) {
531 if (s->can_rx_state != 2) {
532 s->can_rx_state = 2;
533 DB_PRINT("can't receive - all the buffer descriptors are busy\n");
534 }
535 return 0;
536 }
537
538 if (s->can_rx_state != 0) {
539 s->can_rx_state = 0;
540 DB_PRINT("can receive\n");
541 }
542 return 1;
543}
544
545
546
547
548
549static void gem_update_int_status(CadenceGEMState *s)
550{
551 int i;
552
553 if (!s->regs[GEM_ISR]) {
554
555 for (i = 0; i < s->num_priority_queues; ++i) {
556 qemu_set_irq(s->irq[i], 0);
557 }
558 return;
559 }
560
561
562
563
564 if (s->num_priority_queues == 1) {
565
566 DB_PRINT("asserting int.\n");
567 qemu_set_irq(s->irq[0], 1);
568 return;
569 }
570
571 for (i = 0; i < s->num_priority_queues; ++i) {
572 if (s->regs[GEM_INT_Q1_STATUS + i]) {
573 DB_PRINT("asserting int. (q=%d)\n", i);
574 qemu_set_irq(s->irq[i], 1);
575 }
576 }
577}
578
579
580
581
582
583static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
584 unsigned bytes)
585{
586 uint64_t octets;
587
588
589 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
590 s->regs[GEM_OCTRXHI];
591 octets += bytes;
592 s->regs[GEM_OCTRXLO] = octets >> 32;
593 s->regs[GEM_OCTRXHI] = octets;
594
595
596 s->regs[GEM_RXCNT]++;
597
598
599 if (!memcmp(packet, broadcast_addr, 6)) {
600 s->regs[GEM_RXBROADCNT]++;
601 }
602
603
604 if (packet[0] == 0x01) {
605 s->regs[GEM_RXMULTICNT]++;
606 }
607
608 if (bytes <= 64) {
609 s->regs[GEM_RX64CNT]++;
610 } else if (bytes <= 127) {
611 s->regs[GEM_RX65CNT]++;
612 } else if (bytes <= 255) {
613 s->regs[GEM_RX128CNT]++;
614 } else if (bytes <= 511) {
615 s->regs[GEM_RX256CNT]++;
616 } else if (bytes <= 1023) {
617 s->regs[GEM_RX512CNT]++;
618 } else if (bytes <= 1518) {
619 s->regs[GEM_RX1024CNT]++;
620 } else {
621 s->regs[GEM_RX1519CNT]++;
622 }
623}
624
625
626
627
628static unsigned get_bit(const uint8_t *mac, unsigned bit)
629{
630 unsigned byte;
631
632 byte = mac[bit / 8];
633 byte >>= (bit & 0x7);
634 byte &= 1;
635
636 return byte;
637}
638
639
640
641
642static unsigned calc_mac_hash(const uint8_t *mac)
643{
644 int index_bit, mac_bit;
645 unsigned hash_index;
646
647 hash_index = 0;
648 mac_bit = 5;
649 for (index_bit = 5; index_bit >= 0; index_bit--) {
650 hash_index |= (get_bit(mac, mac_bit) ^
651 get_bit(mac, mac_bit + 6) ^
652 get_bit(mac, mac_bit + 12) ^
653 get_bit(mac, mac_bit + 18) ^
654 get_bit(mac, mac_bit + 24) ^
655 get_bit(mac, mac_bit + 30) ^
656 get_bit(mac, mac_bit + 36) ^
657 get_bit(mac, mac_bit + 42)) << index_bit;
658 mac_bit--;
659 }
660
661 return hash_index;
662}
663
664
665
666
667
668
669
670
671
672
673
674static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
675{
676 uint8_t *gem_spaddr;
677 int i;
678
679
680 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
681 return GEM_RX_PROMISCUOUS_ACCEPT;
682 }
683
684 if (!memcmp(packet, broadcast_addr, 6)) {
685
686 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
687 return GEM_RX_REJECT;
688 }
689 return GEM_RX_BROADCAST_ACCEPT;
690 }
691
692
693 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
694 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
695 unsigned hash_index;
696
697 hash_index = calc_mac_hash(packet);
698 if (hash_index < 32) {
699 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
700 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
701 GEM_RX_UNICAST_HASH_ACCEPT;
702 }
703 } else {
704 hash_index -= 32;
705 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
706 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
707 GEM_RX_UNICAST_HASH_ACCEPT;
708 }
709 }
710 }
711
712
713 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
714 for (i = 3; i >= 0; i--) {
715 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
716 return GEM_RX_SAR_ACCEPT + i;
717 }
718 }
719
720
721 return GEM_RX_REJECT;
722}
723
724
725static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
726 unsigned rxbufsize)
727{
728 uint32_t reg;
729 bool matched, mismatched;
730 int i, j;
731
732 for (i = 0; i < s->num_type1_screeners; i++) {
733 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
734 matched = false;
735 mismatched = false;
736
737
738 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
739 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
740 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
741 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
742 matched = true;
743 } else {
744 mismatched = true;
745 }
746 }
747
748
749 if (reg & GEM_ST1R_DSTC_ENABLE) {
750 uint8_t dscp = rxbuf_ptr[14 + 1];
751 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
752 GEM_ST1R_DSTC_MATCH_WIDTH)) {
753 matched = true;
754 } else {
755 mismatched = true;
756 }
757 }
758
759 if (matched && !mismatched) {
760 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
761 }
762 }
763
764 for (i = 0; i < s->num_type2_screeners; i++) {
765 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
766 matched = false;
767 mismatched = false;
768
769 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
770 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
771 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
772 GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
773
774 if (et_idx > s->num_type2_screeners) {
775 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
776 "register index: %d\n", et_idx);
777 }
778 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
779 et_idx]) {
780 matched = true;
781 } else {
782 mismatched = true;
783 }
784 }
785
786
787 for (j = 0; j < 3; j++) {
788 uint32_t cr0, cr1, mask;
789 uint16_t rx_cmp;
790 int offset;
791 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
792 GEM_ST2R_COMPARE_WIDTH);
793
794 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
795 continue;
796 }
797 if (cr_idx > s->num_type2_screeners) {
798 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
799 "register index: %d\n", cr_idx);
800 }
801
802 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
803 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
804 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
805 GEM_T2CW1_OFFSET_VALUE_WIDTH);
806
807 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
808 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
809 case 3:
810 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
811 "unimplemented - assuming UDP\n");
812 offset += 8;
813
814 case 2:
815 offset += 20;
816
817 case 1:
818 offset += 14;
819 break;
820 case 0:
821
822 break;
823 }
824
825 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
826 mask = extract32(cr0, 0, 16);
827
828 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
829 matched = true;
830 } else {
831 mismatched = true;
832 }
833 }
834
835 if (matched && !mismatched) {
836 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
837 }
838 }
839
840
841 return 0;
842}
843
844static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
845{
846 hwaddr desc_addr = 0;
847
848 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
849 desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
850 }
851 desc_addr <<= 32;
852 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
853 return desc_addr;
854}
855
856static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
857{
858 return gem_get_desc_addr(s, true, q);
859}
860
861static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
862{
863 return gem_get_desc_addr(s, false, q);
864}
865
866static void gem_get_rx_desc(CadenceGEMState *s, int q)
867{
868 hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
869
870 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr);
871
872
873 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
874 (uint8_t *)s->rx_desc[q],
875 sizeof(uint32_t) * gem_get_desc_len(s, true));
876
877
878 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
879 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
880 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
881 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
882
883 gem_update_int_status(s);
884 }
885}
886
887
888
889
890
891static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
892{
893 CadenceGEMState *s;
894 unsigned rxbufsize, bytes_to_copy;
895 unsigned rxbuf_offset;
896 uint8_t rxbuf[2048];
897 uint8_t *rxbuf_ptr;
898 bool first_desc = true;
899 int maf;
900 int q = 0;
901
902 s = qemu_get_nic_opaque(nc);
903
904
905 maf = gem_mac_address_filter(s, buf);
906 if (maf == GEM_RX_REJECT) {
907 return -1;
908 }
909
910
911 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
912 unsigned type_len;
913
914
915 type_len = buf[12] << 8 | buf[13];
916
917 if (type_len < 0x600) {
918 if (size < type_len) {
919
920 return -1;
921 }
922 }
923 }
924
925
926
927
928 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
929 GEM_NWCFG_BUFF_OFST_S;
930
931
932
933
934 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
935 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
936 bytes_to_copy = size;
937
938
939
940
941 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
942 rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
943 }
944
945
946
947
948
949 if (size < 60) {
950 size = 60;
951 }
952
953
954 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
955 rxbuf_ptr = (void *)buf;
956 } else {
957 unsigned crc_val;
958
959 if (size > sizeof(rxbuf) - sizeof(crc_val)) {
960 size = sizeof(rxbuf) - sizeof(crc_val);
961 }
962 bytes_to_copy = size;
963
964
965
966
967 memcpy(rxbuf, buf, size);
968 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
969 rxbuf_ptr = rxbuf;
970 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
971 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
972
973 bytes_to_copy += 4;
974 size += 4;
975 }
976
977 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
978
979
980 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
981
982 while (bytes_to_copy) {
983 hwaddr desc_addr;
984
985
986 if (!gem_can_receive(nc)) {
987 return -1;
988 }
989
990 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
991 rx_desc_get_buffer(s->rx_desc[q]));
992
993
994 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
995 rxbuf_offset,
996 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr,
997 MIN(bytes_to_copy, rxbufsize));
998 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
999 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
1000
1001
1002 if (first_desc) {
1003 rx_desc_set_sof(s->rx_desc[q]);
1004 first_desc = false;
1005 }
1006 if (bytes_to_copy == 0) {
1007 rx_desc_set_eof(s->rx_desc[q]);
1008 rx_desc_set_length(s->rx_desc[q], size);
1009 }
1010 rx_desc_set_ownership(s->rx_desc[q]);
1011
1012 switch (maf) {
1013 case GEM_RX_PROMISCUOUS_ACCEPT:
1014 break;
1015 case GEM_RX_BROADCAST_ACCEPT:
1016 rx_desc_set_broadcast(s->rx_desc[q]);
1017 break;
1018 case GEM_RX_UNICAST_HASH_ACCEPT:
1019 rx_desc_set_unicast_hash(s->rx_desc[q]);
1020 break;
1021 case GEM_RX_MULTICAST_HASH_ACCEPT:
1022 rx_desc_set_multicast_hash(s->rx_desc[q]);
1023 break;
1024 case GEM_RX_REJECT:
1025 abort();
1026 default:
1027 rx_desc_set_sar(s->rx_desc[q], maf);
1028 }
1029
1030
1031 desc_addr = gem_get_rx_desc_addr(s, q);
1032 address_space_write(&s->dma_as, desc_addr,
1033 MEMTXATTRS_UNSPECIFIED,
1034 (uint8_t *)s->rx_desc[q],
1035 sizeof(uint32_t) * gem_get_desc_len(s, true));
1036
1037
1038 if (rx_desc_get_wrap(s->rx_desc[q])) {
1039 DB_PRINT("wrapping RX descriptor list\n");
1040 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
1041 } else {
1042 DB_PRINT("incrementing RX descriptor list\n");
1043 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
1044 }
1045
1046 gem_get_rx_desc(s, q);
1047 }
1048
1049
1050 gem_receive_updatestats(s, buf, size);
1051
1052 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
1053 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
1054
1055
1056 gem_update_int_status(s);
1057
1058 return size;
1059}
1060
1061
1062
1063
1064
1065static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
1066 unsigned bytes)
1067{
1068 uint64_t octets;
1069
1070
1071 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1072 s->regs[GEM_OCTTXHI];
1073 octets += bytes;
1074 s->regs[GEM_OCTTXLO] = octets >> 32;
1075 s->regs[GEM_OCTTXHI] = octets;
1076
1077
1078 s->regs[GEM_TXCNT]++;
1079
1080
1081 if (!memcmp(packet, broadcast_addr, 6)) {
1082 s->regs[GEM_TXBCNT]++;
1083 }
1084
1085
1086 if (packet[0] == 0x01) {
1087 s->regs[GEM_TXMCNT]++;
1088 }
1089
1090 if (bytes <= 64) {
1091 s->regs[GEM_TX64CNT]++;
1092 } else if (bytes <= 127) {
1093 s->regs[GEM_TX65CNT]++;
1094 } else if (bytes <= 255) {
1095 s->regs[GEM_TX128CNT]++;
1096 } else if (bytes <= 511) {
1097 s->regs[GEM_TX256CNT]++;
1098 } else if (bytes <= 1023) {
1099 s->regs[GEM_TX512CNT]++;
1100 } else if (bytes <= 1518) {
1101 s->regs[GEM_TX1024CNT]++;
1102 } else {
1103 s->regs[GEM_TX1519CNT]++;
1104 }
1105}
1106
1107
1108
1109
1110
1111static void gem_transmit(CadenceGEMState *s)
1112{
1113 uint32_t desc[DESC_MAX_NUM_WORDS];
1114 hwaddr packet_desc_addr;
1115 uint8_t tx_packet[2048];
1116 uint8_t *p;
1117 unsigned total_bytes;
1118 int q = 0;
1119
1120
1121 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1122 return;
1123 }
1124
1125 DB_PRINT("\n");
1126
1127
1128
1129
1130
1131 p = tx_packet;
1132 total_bytes = 0;
1133
1134 for (q = s->num_priority_queues - 1; q >= 0; q--) {
1135
1136 packet_desc_addr = gem_get_tx_desc_addr(s, q);
1137
1138 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1139 address_space_read(&s->dma_as, packet_desc_addr,
1140 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1141 sizeof(uint32_t) * gem_get_desc_len(s, false));
1142
1143 while (tx_desc_get_used(desc) == 0) {
1144
1145
1146 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1147 return;
1148 }
1149 print_gem_tx_desc(desc, q);
1150
1151
1152
1153
1154 if ((tx_desc_get_buffer(s, desc) == 0) ||
1155 (tx_desc_get_length(desc) == 0)) {
1156 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1157 (unsigned)packet_desc_addr);
1158 break;
1159 }
1160
1161 if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1162 (p - tx_packet)) {
1163 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1164 "0x%x\n", (unsigned)packet_desc_addr,
1165 (unsigned)tx_desc_get_length(desc),
1166 sizeof(tx_packet) - (p - tx_packet));
1167 break;
1168 }
1169
1170
1171
1172
1173 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc),
1174 MEMTXATTRS_UNSPECIFIED,
1175 p, tx_desc_get_length(desc));
1176 p += tx_desc_get_length(desc);
1177 total_bytes += tx_desc_get_length(desc);
1178
1179
1180 if (tx_desc_get_last(desc)) {
1181 uint32_t desc_first[DESC_MAX_NUM_WORDS];
1182 hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
1183
1184
1185
1186
1187 address_space_read(&s->dma_as, desc_addr,
1188 MEMTXATTRS_UNSPECIFIED,
1189 (uint8_t *)desc_first,
1190 sizeof(desc_first));
1191 tx_desc_set_used(desc_first);
1192 address_space_write(&s->dma_as, desc_addr,
1193 MEMTXATTRS_UNSPECIFIED,
1194 (uint8_t *)desc_first,
1195 sizeof(desc_first));
1196
1197 if (tx_desc_get_wrap(desc)) {
1198 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1199 } else {
1200 s->tx_desc_addr[q] = packet_desc_addr +
1201 4 * gem_get_desc_len(s, false);
1202 }
1203 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1204
1205 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1206 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1207
1208
1209 if (s->num_priority_queues > 1) {
1210 s->regs[GEM_INT_Q1_STATUS + q] |=
1211 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1212 }
1213
1214
1215 gem_update_int_status(s);
1216
1217
1218 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1219 net_checksum_calculate(tx_packet, total_bytes);
1220 }
1221
1222
1223 gem_transmit_updatestats(s, tx_packet, total_bytes);
1224
1225
1226 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1227 GEM_NWCTRL_LOCALLOOP)) {
1228 gem_receive(qemu_get_queue(s->nic), tx_packet,
1229 total_bytes);
1230 } else {
1231 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1232 total_bytes);
1233 }
1234
1235
1236 p = tx_packet;
1237 total_bytes = 0;
1238 }
1239
1240
1241 if (tx_desc_get_wrap(desc)) {
1242 tx_desc_set_last(desc);
1243 packet_desc_addr = s->regs[GEM_TXQBASE];
1244 } else {
1245 packet_desc_addr += 4 * gem_get_desc_len(s, false);
1246 }
1247 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1248 address_space_read(&s->dma_as, packet_desc_addr,
1249 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1250 sizeof(uint32_t) * gem_get_desc_len(s, false));
1251 }
1252
1253 if (tx_desc_get_used(desc)) {
1254 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1255 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1256 gem_update_int_status(s);
1257 }
1258 }
1259}
1260
1261static void gem_phy_reset(CadenceGEMState *s)
1262{
1263 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
1264 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
1265 s->phy_regs[PHY_REG_STATUS] = 0x7969;
1266 s->phy_regs[PHY_REG_PHYID1] = 0x0141;
1267 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
1268 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
1269 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
1270 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
1271 s->phy_regs[PHY_REG_NEXTP] = 0x2001;
1272 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
1273 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
1274 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
1275 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
1276 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
1277 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
1278 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
1279 s->phy_regs[PHY_REG_LED] = 0x4100;
1280 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
1281 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
1282
1283 phy_update_link(s);
1284}
1285
1286static void gem_reset(DeviceState *d)
1287{
1288 int i;
1289 CadenceGEMState *s = CADENCE_GEM(d);
1290 const uint8_t *a;
1291 uint32_t queues_mask = 0;
1292
1293 DB_PRINT("\n");
1294
1295
1296 memset(&s->regs[0], 0, sizeof(s->regs));
1297 s->regs[GEM_NWCFG] = 0x00080000;
1298 s->regs[GEM_NWSTATUS] = 0x00000006;
1299 s->regs[GEM_DMACFG] = 0x00020784;
1300 s->regs[GEM_IMR] = 0x07ffffff;
1301 s->regs[GEM_TXPAUSE] = 0x0000ffff;
1302 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1303 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1304 s->regs[GEM_MODID] = s->revision;
1305 s->regs[GEM_DESCONF] = 0x02500111;
1306 s->regs[GEM_DESCONF2] = 0x2ab13fff;
1307 s->regs[GEM_DESCONF5] = 0x002f2045;
1308 s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
1309
1310 if (s->num_priority_queues > 1) {
1311 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
1312 s->regs[GEM_DESCONF6] |= queues_mask;
1313 }
1314
1315
1316 a = &s->conf.macaddr.a[0];
1317 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1318 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1319
1320 for (i = 0; i < 4; i++) {
1321 s->sar_active[i] = false;
1322 }
1323
1324 gem_phy_reset(s);
1325
1326 gem_update_int_status(s);
1327}
1328
1329static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1330{
1331 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1332 return s->phy_regs[reg_num];
1333}
1334
1335static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1336{
1337 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1338
1339 switch (reg_num) {
1340 case PHY_REG_CONTROL:
1341 if (val & PHY_REG_CONTROL_RST) {
1342
1343 gem_phy_reset(s);
1344 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1345 s->phy_loop = 0;
1346 }
1347 if (val & PHY_REG_CONTROL_ANEG) {
1348
1349 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
1350 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1351 }
1352 if (val & PHY_REG_CONTROL_LOOP) {
1353 DB_PRINT("PHY placed in loopback\n");
1354 s->phy_loop = 1;
1355 } else {
1356 s->phy_loop = 0;
1357 }
1358 break;
1359 }
1360 s->phy_regs[reg_num] = val;
1361}
1362
1363
1364
1365
1366
1367static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1368{
1369 CadenceGEMState *s;
1370 uint32_t retval;
1371 s = (CadenceGEMState *)opaque;
1372
1373 offset >>= 2;
1374 retval = s->regs[offset];
1375
1376 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1377
1378 switch (offset) {
1379 case GEM_ISR:
1380 DB_PRINT("lowering irqs on ISR read\n");
1381
1382 break;
1383 case GEM_PHYMNTNC:
1384 if (retval & GEM_PHYMNTNC_OP_R) {
1385 uint32_t phy_addr, reg_num;
1386
1387 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1388 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1389 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1390 retval &= 0xFFFF0000;
1391 retval |= gem_phy_read(s, reg_num);
1392 } else {
1393 retval |= 0xFFFF;
1394 }
1395 }
1396 break;
1397 }
1398
1399
1400 s->regs[offset] &= ~(s->regs_rtc[offset]);
1401
1402
1403 retval &= ~(s->regs_wo[offset]);
1404
1405 DB_PRINT("0x%08x\n", retval);
1406 gem_update_int_status(s);
1407 return retval;
1408}
1409
1410
1411
1412
1413
1414static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1415 unsigned size)
1416{
1417 CadenceGEMState *s = (CadenceGEMState *)opaque;
1418 uint32_t readonly;
1419 int i;
1420
1421 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1422 offset >>= 2;
1423
1424
1425 val &= ~(s->regs_ro[offset]);
1426
1427 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1428
1429
1430 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1431
1432
1433 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1434
1435
1436 switch (offset) {
1437 case GEM_NWCTRL:
1438 if (val & GEM_NWCTRL_RXENA) {
1439 for (i = 0; i < s->num_priority_queues; ++i) {
1440 gem_get_rx_desc(s, i);
1441 }
1442 }
1443 if (val & GEM_NWCTRL_TXSTART) {
1444 gem_transmit(s);
1445 }
1446 if (!(val & GEM_NWCTRL_TXENA)) {
1447
1448 for (i = 0; i < s->num_priority_queues; i++) {
1449 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1450 }
1451 }
1452 if (gem_can_receive(qemu_get_queue(s->nic))) {
1453 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1454 }
1455 break;
1456
1457 case GEM_TXSTATUS:
1458 gem_update_int_status(s);
1459 break;
1460 case GEM_RXQBASE:
1461 s->rx_desc_addr[0] = val;
1462 break;
1463 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
1464 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1465 break;
1466 case GEM_TXQBASE:
1467 s->tx_desc_addr[0] = val;
1468 break;
1469 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
1470 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1471 break;
1472 case GEM_RXSTATUS:
1473 gem_update_int_status(s);
1474 break;
1475 case GEM_IER:
1476 s->regs[GEM_IMR] &= ~val;
1477 gem_update_int_status(s);
1478 break;
1479 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1480 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1481 gem_update_int_status(s);
1482 break;
1483 case GEM_IDR:
1484 s->regs[GEM_IMR] |= val;
1485 gem_update_int_status(s);
1486 break;
1487 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1488 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1489 gem_update_int_status(s);
1490 break;
1491 case GEM_SPADDR1LO:
1492 case GEM_SPADDR2LO:
1493 case GEM_SPADDR3LO:
1494 case GEM_SPADDR4LO:
1495 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1496 break;
1497 case GEM_SPADDR1HI:
1498 case GEM_SPADDR2HI:
1499 case GEM_SPADDR3HI:
1500 case GEM_SPADDR4HI:
1501 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1502 break;
1503 case GEM_PHYMNTNC:
1504 if (val & GEM_PHYMNTNC_OP_W) {
1505 uint32_t phy_addr, reg_num;
1506
1507 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1508 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1509 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1510 gem_phy_write(s, reg_num, val);
1511 }
1512 }
1513 break;
1514 }
1515
1516 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1517}
1518
1519static const MemoryRegionOps gem_ops = {
1520 .read = gem_read,
1521 .write = gem_write,
1522 .endianness = DEVICE_LITTLE_ENDIAN,
1523};
1524
1525static void gem_set_link(NetClientState *nc)
1526{
1527 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1528
1529 DB_PRINT("\n");
1530 phy_update_link(s);
1531 gem_update_int_status(s);
1532}
1533
1534static NetClientInfo net_gem_info = {
1535 .type = NET_CLIENT_DRIVER_NIC,
1536 .size = sizeof(NICState),
1537 .can_receive = gem_can_receive,
1538 .receive = gem_receive,
1539 .link_status_changed = gem_set_link,
1540};
1541
1542static void gem_realize(DeviceState *dev, Error **errp)
1543{
1544 CadenceGEMState *s = CADENCE_GEM(dev);
1545 int i;
1546
1547 address_space_init(&s->dma_as,
1548 s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
1549
1550 if (s->num_priority_queues == 0 ||
1551 s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1552 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1553 s->num_priority_queues);
1554 return;
1555 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1556 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1557 s->num_type1_screeners);
1558 return;
1559 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1560 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1561 s->num_type2_screeners);
1562 return;
1563 }
1564
1565 for (i = 0; i < s->num_priority_queues; ++i) {
1566 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1567 }
1568
1569 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1570
1571 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1572 object_get_typename(OBJECT(dev)), dev->id, s);
1573}
1574
1575static void gem_init(Object *obj)
1576{
1577 CadenceGEMState *s = CADENCE_GEM(obj);
1578 DeviceState *dev = DEVICE(obj);
1579
1580 DB_PRINT("\n");
1581
1582 gem_init_register_masks(s);
1583 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1584 "enet", sizeof(s->regs));
1585
1586 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1587
1588 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1589 (Object **)&s->dma_mr,
1590 qdev_prop_allow_set_link_before_realize,
1591 OBJ_PROP_LINK_STRONG,
1592 &error_abort);
1593}
1594
1595static const VMStateDescription vmstate_cadence_gem = {
1596 .name = "cadence_gem",
1597 .version_id = 4,
1598 .minimum_version_id = 4,
1599 .fields = (VMStateField[]) {
1600 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1601 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1602 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1603 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1604 MAX_PRIORITY_QUEUES),
1605 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1606 MAX_PRIORITY_QUEUES),
1607 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1608 VMSTATE_END_OF_LIST(),
1609 }
1610};
1611
1612static Property gem_properties[] = {
1613 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1614 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1615 GEM_MODID_VALUE),
1616 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1617 num_priority_queues, 1),
1618 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1619 num_type1_screeners, 4),
1620 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1621 num_type2_screeners, 4),
1622 DEFINE_PROP_END_OF_LIST(),
1623};
1624
1625static void gem_class_init(ObjectClass *klass, void *data)
1626{
1627 DeviceClass *dc = DEVICE_CLASS(klass);
1628
1629 dc->realize = gem_realize;
1630 dc->props = gem_properties;
1631 dc->vmsd = &vmstate_cadence_gem;
1632 dc->reset = gem_reset;
1633}
1634
1635static const TypeInfo gem_info = {
1636 .name = TYPE_CADENCE_GEM,
1637 .parent = TYPE_SYS_BUS_DEVICE,
1638 .instance_size = sizeof(CadenceGEMState),
1639 .instance_init = gem_init,
1640 .class_init = gem_class_init,
1641};
1642
1643static void gem_register_types(void)
1644{
1645 type_register_static(&gem_info);
1646}
1647
1648type_init(gem_register_types)
1649