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20#include "qemu/osdep.h"
21#include "hw/irq.h"
22#include "hw/qdev-properties.h"
23#include "hw/sysbus.h"
24#include "migration/vmstate.h"
25#include "net/net.h"
26#include "qapi/error.h"
27#include "qemu/module.h"
28#include "qemu/timer.h"
29#include <zlib.h>
30
31
32
33#define SONIC_PROM_SIZE 0x1000
34
35#ifdef DEBUG_SONIC
36#define DPRINTF(fmt, ...) \
37do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
38static const char* reg_names[] = {
39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
47#else
48#define DPRINTF(fmt, ...) do {} while (0)
49#endif
50
51#define SONIC_ERROR(fmt, ...) \
52do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54#define SONIC_CR 0x00
55#define SONIC_DCR 0x01
56#define SONIC_RCR 0x02
57#define SONIC_TCR 0x03
58#define SONIC_IMR 0x04
59#define SONIC_ISR 0x05
60#define SONIC_UTDA 0x06
61#define SONIC_CTDA 0x07
62#define SONIC_TPS 0x08
63#define SONIC_TFC 0x09
64#define SONIC_TSA0 0x0a
65#define SONIC_TSA1 0x0b
66#define SONIC_TFS 0x0c
67#define SONIC_URDA 0x0d
68#define SONIC_CRDA 0x0e
69#define SONIC_CRBA0 0x0f
70#define SONIC_CRBA1 0x10
71#define SONIC_RBWC0 0x11
72#define SONIC_RBWC1 0x12
73#define SONIC_EOBC 0x13
74#define SONIC_URRA 0x14
75#define SONIC_RSA 0x15
76#define SONIC_REA 0x16
77#define SONIC_RRP 0x17
78#define SONIC_RWP 0x18
79#define SONIC_TRBA0 0x19
80#define SONIC_TRBA1 0x1a
81#define SONIC_LLFA 0x1f
82#define SONIC_TTDA 0x20
83#define SONIC_CEP 0x21
84#define SONIC_CAP2 0x22
85#define SONIC_CAP1 0x23
86#define SONIC_CAP0 0x24
87#define SONIC_CE 0x25
88#define SONIC_CDP 0x26
89#define SONIC_CDC 0x27
90#define SONIC_SR 0x28
91#define SONIC_WT0 0x29
92#define SONIC_WT1 0x2a
93#define SONIC_RSC 0x2b
94#define SONIC_CRCT 0x2c
95#define SONIC_FAET 0x2d
96#define SONIC_MPT 0x2e
97#define SONIC_MDT 0x2f
98#define SONIC_DCR2 0x3f
99
100#define SONIC_CR_HTX 0x0001
101#define SONIC_CR_TXP 0x0002
102#define SONIC_CR_RXDIS 0x0004
103#define SONIC_CR_RXEN 0x0008
104#define SONIC_CR_STP 0x0010
105#define SONIC_CR_ST 0x0020
106#define SONIC_CR_RST 0x0080
107#define SONIC_CR_RRRA 0x0100
108#define SONIC_CR_LCAM 0x0200
109#define SONIC_CR_MASK 0x03bf
110
111#define SONIC_DCR_DW 0x0020
112#define SONIC_DCR_LBR 0x2000
113#define SONIC_DCR_EXBUS 0x8000
114
115#define SONIC_RCR_PRX 0x0001
116#define SONIC_RCR_LBK 0x0002
117#define SONIC_RCR_FAER 0x0004
118#define SONIC_RCR_CRCR 0x0008
119#define SONIC_RCR_CRS 0x0020
120#define SONIC_RCR_LPKT 0x0040
121#define SONIC_RCR_BC 0x0080
122#define SONIC_RCR_MC 0x0100
123#define SONIC_RCR_LB0 0x0200
124#define SONIC_RCR_LB1 0x0400
125#define SONIC_RCR_AMC 0x0800
126#define SONIC_RCR_PRO 0x1000
127#define SONIC_RCR_BRD 0x2000
128#define SONIC_RCR_RNT 0x4000
129
130#define SONIC_TCR_PTX 0x0001
131#define SONIC_TCR_BCM 0x0002
132#define SONIC_TCR_FU 0x0004
133#define SONIC_TCR_EXC 0x0040
134#define SONIC_TCR_CRSL 0x0080
135#define SONIC_TCR_NCRS 0x0100
136#define SONIC_TCR_EXD 0x0400
137#define SONIC_TCR_CRCI 0x2000
138#define SONIC_TCR_PINT 0x8000
139
140#define SONIC_ISR_RBAE 0x0010
141#define SONIC_ISR_RBE 0x0020
142#define SONIC_ISR_RDE 0x0040
143#define SONIC_ISR_TC 0x0080
144#define SONIC_ISR_TXDN 0x0200
145#define SONIC_ISR_PKTRX 0x0400
146#define SONIC_ISR_PINT 0x0800
147#define SONIC_ISR_LCD 0x1000
148
149#define SONIC_DESC_EOL 0x0001
150#define SONIC_DESC_ADDR 0xFFFE
151
152#define TYPE_DP8393X "dp8393x"
153#define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
154
155typedef struct dp8393xState {
156 SysBusDevice parent_obj;
157
158
159 uint8_t it_shift;
160 bool big_endian;
161 bool last_rba_is_full;
162 qemu_irq irq;
163#ifdef DEBUG_SONIC
164 int irq_level;
165#endif
166 QEMUTimer *watchdog;
167 int64_t wt_last_update;
168 NICConf conf;
169 NICState *nic;
170 MemoryRegion mmio;
171 MemoryRegion prom;
172
173
174 uint8_t cam[16][6];
175 uint16_t regs[0x40];
176
177
178 uint8_t tx_buffer[0x10000];
179 uint16_t data[12];
180 int loopback_packet;
181
182
183 void *dma_mr;
184 AddressSpace as;
185} dp8393xState;
186
187
188
189
190
191
192
193static uint32_t dp8393x_cdp(dp8393xState *s)
194{
195 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
196}
197
198static uint32_t dp8393x_crba(dp8393xState *s)
199{
200 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
201}
202
203static uint32_t dp8393x_crda(dp8393xState *s)
204{
205 return (s->regs[SONIC_URDA] << 16) |
206 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
207}
208
209static uint32_t dp8393x_rbwc(dp8393xState *s)
210{
211 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
212}
213
214static uint32_t dp8393x_rrp(dp8393xState *s)
215{
216 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
217}
218
219static uint32_t dp8393x_tsa(dp8393xState *s)
220{
221 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
222}
223
224static uint32_t dp8393x_ttda(dp8393xState *s)
225{
226 return (s->regs[SONIC_UTDA] << 16) |
227 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
228}
229
230static uint32_t dp8393x_wt(dp8393xState *s)
231{
232 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
233}
234
235static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
236{
237 uint16_t val;
238
239 if (s->big_endian) {
240 val = be16_to_cpu(s->data[offset * width + width - 1]);
241 } else {
242 val = le16_to_cpu(s->data[offset * width]);
243 }
244 return val;
245}
246
247static void dp8393x_put(dp8393xState *s, int width, int offset,
248 uint16_t val)
249{
250 if (s->big_endian) {
251 if (width == 2) {
252 s->data[offset * 2] = 0;
253 s->data[offset * 2 + 1] = cpu_to_be16(val);
254 } else {
255 s->data[offset] = cpu_to_be16(val);
256 }
257 } else {
258 if (width == 2) {
259 s->data[offset * 2] = cpu_to_le16(val);
260 s->data[offset * 2 + 1] = 0;
261 } else {
262 s->data[offset] = cpu_to_le16(val);
263 }
264 }
265}
266
267static void dp8393x_update_irq(dp8393xState *s)
268{
269 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
270
271#ifdef DEBUG_SONIC
272 if (level != s->irq_level) {
273 s->irq_level = level;
274 if (level) {
275 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
276 } else {
277 DPRINTF("lower irq\n");
278 }
279 }
280#endif
281
282 qemu_set_irq(s->irq, level);
283}
284
285static void dp8393x_do_load_cam(dp8393xState *s)
286{
287 int width, size;
288 uint16_t index = 0;
289
290 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
291 size = sizeof(uint16_t) * 4 * width;
292
293 while (s->regs[SONIC_CDC] & 0x1f) {
294
295 address_space_rw(&s->as, dp8393x_cdp(s),
296 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
297 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
298 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
299 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
300 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
301 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
302 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
303 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
304 s->cam[index][0], s->cam[index][1], s->cam[index][2],
305 s->cam[index][3], s->cam[index][4], s->cam[index][5]);
306
307 s->regs[SONIC_CDC]--;
308 s->regs[SONIC_CDP] += size;
309 index++;
310 }
311
312
313 address_space_rw(&s->as, dp8393x_cdp(s),
314 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
315 s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
316 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
317
318
319 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
320 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
321 dp8393x_update_irq(s);
322}
323
324static void dp8393x_do_read_rra(dp8393xState *s)
325{
326 int width, size;
327
328
329 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
330 size = sizeof(uint16_t) * 4 * width;
331 address_space_rw(&s->as, dp8393x_rrp(s),
332 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
333
334
335 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
336 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
337 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
338 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
339 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
340 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
341 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
342
343
344 s->regs[SONIC_RRP] += size;
345
346
347 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
348 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
349 }
350
351
352 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
353 {
354 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
355 dp8393x_update_irq(s);
356 }
357
358
359 s->last_rba_is_full = false;
360}
361
362static void dp8393x_do_software_reset(dp8393xState *s)
363{
364 timer_del(s->watchdog);
365
366 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
367 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
368}
369
370static void dp8393x_set_next_tick(dp8393xState *s)
371{
372 uint32_t ticks;
373 int64_t delay;
374
375 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
376 timer_del(s->watchdog);
377 return;
378 }
379
380 ticks = dp8393x_wt(s);
381 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
382 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
383 timer_mod(s->watchdog, s->wt_last_update + delay);
384}
385
386static void dp8393x_update_wt_regs(dp8393xState *s)
387{
388 int64_t elapsed;
389 uint32_t val;
390
391 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
392 timer_del(s->watchdog);
393 return;
394 }
395
396 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
397 val = dp8393x_wt(s);
398 val -= elapsed / 5000000;
399 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
400 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
401 dp8393x_set_next_tick(s);
402
403}
404
405static void dp8393x_do_start_timer(dp8393xState *s)
406{
407 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
408 dp8393x_set_next_tick(s);
409}
410
411static void dp8393x_do_stop_timer(dp8393xState *s)
412{
413 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
414 dp8393x_update_wt_regs(s);
415}
416
417static int dp8393x_can_receive(NetClientState *nc);
418
419static void dp8393x_do_receiver_enable(dp8393xState *s)
420{
421 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
422 if (dp8393x_can_receive(s->nic->ncs)) {
423 qemu_flush_queued_packets(qemu_get_queue(s->nic));
424 }
425}
426
427static void dp8393x_do_receiver_disable(dp8393xState *s)
428{
429 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
430}
431
432static void dp8393x_do_transmit_packets(dp8393xState *s)
433{
434 NetClientState *nc = qemu_get_queue(s->nic);
435 int width, size;
436 int tx_len, len;
437 uint16_t i;
438
439 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
440
441 while (1) {
442
443 size = sizeof(uint16_t) * 6 * width;
444 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
445 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
446 address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
447 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
448 tx_len = 0;
449
450
451 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
452 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
453 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
454 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
455 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
456 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
457
458
459 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
460 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
461 } else {
462 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
463 }
464
465 for (i = 0; i < s->regs[SONIC_TFC]; ) {
466
467 len = s->regs[SONIC_TFS];
468 if (tx_len + len > sizeof(s->tx_buffer)) {
469 len = sizeof(s->tx_buffer) - tx_len;
470 }
471 address_space_rw(&s->as, dp8393x_tsa(s),
472 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
473 tx_len += len;
474
475 i++;
476 if (i != s->regs[SONIC_TFC]) {
477
478 size = sizeof(uint16_t) * 3 * width;
479 address_space_rw(&s->as,
480 dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
481 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
482 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
483 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
484 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
485 }
486 }
487
488
489 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
490
491
492 } else {
493
494 tx_len -= 4;
495 }
496
497 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
498
499 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
500 if (nc->info->can_receive(nc)) {
501 s->loopback_packet = 1;
502 nc->info->receive(nc, s->tx_buffer, tx_len);
503 }
504 } else {
505
506 qemu_send_packet(nc, s->tx_buffer, tx_len);
507 }
508 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
509
510
511 dp8393x_put(s, width, 0,
512 s->regs[SONIC_TCR] & 0x0fff);
513 size = sizeof(uint16_t) * width;
514 address_space_rw(&s->as,
515 dp8393x_ttda(s),
516 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
517
518 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
519
520 size = sizeof(uint16_t) * width;
521 address_space_rw(&s->as,
522 dp8393x_ttda(s) +
523 sizeof(uint16_t) *
524 (4 + 3 * s->regs[SONIC_TFC]) * width,
525 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
526 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
527 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
528
529 break;
530 }
531 }
532 }
533
534
535 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
536 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
537 dp8393x_update_irq(s);
538}
539
540static void dp8393x_do_halt_transmission(dp8393xState *s)
541{
542
543}
544
545static void dp8393x_do_command(dp8393xState *s, uint16_t command)
546{
547 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
548 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
549 return;
550 }
551
552 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
553
554 if (command & SONIC_CR_HTX)
555 dp8393x_do_halt_transmission(s);
556 if (command & SONIC_CR_TXP)
557 dp8393x_do_transmit_packets(s);
558 if (command & SONIC_CR_RXDIS)
559 dp8393x_do_receiver_disable(s);
560 if (command & SONIC_CR_RXEN)
561 dp8393x_do_receiver_enable(s);
562 if (command & SONIC_CR_STP)
563 dp8393x_do_stop_timer(s);
564 if (command & SONIC_CR_ST)
565 dp8393x_do_start_timer(s);
566 if (command & SONIC_CR_RST)
567 dp8393x_do_software_reset(s);
568 if (command & SONIC_CR_RRRA) {
569 dp8393x_do_read_rra(s);
570 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
571 }
572 if (command & SONIC_CR_LCAM)
573 dp8393x_do_load_cam(s);
574}
575
576static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
577{
578 dp8393xState *s = opaque;
579 int reg = addr >> s->it_shift;
580 uint16_t val = 0;
581
582 switch (reg) {
583
584 case SONIC_WT0:
585 case SONIC_WT1:
586 dp8393x_update_wt_regs(s);
587 val = s->regs[reg];
588 break;
589
590 case SONIC_CAP2:
591 case SONIC_CAP1:
592 case SONIC_CAP0:
593 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
594 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
595 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
596 }
597 break;
598
599 default:
600 val = s->regs[reg];
601 }
602
603 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
604
605 return s->big_endian ? val << 16 : val;
606}
607
608static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
609 unsigned int size)
610{
611 dp8393xState *s = opaque;
612 int reg = addr >> s->it_shift;
613 uint32_t val = s->big_endian ? data >> 16 : data;
614
615 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);
616
617 switch (reg) {
618
619 case SONIC_CR:
620 dp8393x_do_command(s, val);
621 break;
622
623 case SONIC_CAP2:
624 case SONIC_CAP1:
625 case SONIC_CAP0:
626 case SONIC_SR:
627 case SONIC_MDT:
628 DPRINTF("writing to reg %d invalid\n", reg);
629 break;
630
631 case SONIC_DCR:
632 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
633 s->regs[reg] = val & 0xbfff;
634 } else {
635 DPRINTF("writing to DCR invalid\n");
636 }
637 break;
638 case SONIC_DCR2:
639 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
640 s->regs[reg] = val & 0xf017;
641 } else {
642 DPRINTF("writing to DCR2 invalid\n");
643 }
644 break;
645
646 case SONIC_TCR:
647 s->regs[reg] = val & 0xf000;
648 break;
649
650 case SONIC_RCR:
651 s->regs[reg] = val & 0xffe0;
652 break;
653
654 case SONIC_IMR:
655 s->regs[reg] = val & 0x7fff;
656 dp8393x_update_irq(s);
657 break;
658
659 case SONIC_ISR:
660 val &= s->regs[reg];
661 s->regs[reg] &= ~val;
662 if (val & SONIC_ISR_RBE) {
663 dp8393x_do_read_rra(s);
664 }
665 dp8393x_update_irq(s);
666 break;
667
668 case SONIC_RSA:
669 case SONIC_REA:
670 case SONIC_RRP:
671 case SONIC_RWP:
672 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
673 s->regs[reg] = val & 0xfffc;
674 } else {
675 s->regs[reg] = val & 0xfffe;
676 }
677 break;
678
679 case SONIC_CRCT:
680 case SONIC_FAET:
681 case SONIC_MPT:
682 s->regs[reg] = val ^ 0xffff;
683 break;
684
685 default:
686 s->regs[reg] = val;
687 }
688
689 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
690 dp8393x_set_next_tick(s);
691 }
692}
693
694static const MemoryRegionOps dp8393x_ops = {
695 .read = dp8393x_read,
696 .write = dp8393x_write,
697 .impl.min_access_size = 4,
698 .impl.max_access_size = 4,
699 .endianness = DEVICE_NATIVE_ENDIAN,
700};
701
702static void dp8393x_watchdog(void *opaque)
703{
704 dp8393xState *s = opaque;
705
706 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
707 return;
708 }
709
710 s->regs[SONIC_WT1] = 0xffff;
711 s->regs[SONIC_WT0] = 0xffff;
712 dp8393x_set_next_tick(s);
713
714
715 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
716 dp8393x_update_irq(s);
717}
718
719static int dp8393x_can_receive(NetClientState *nc)
720{
721 dp8393xState *s = qemu_get_nic_opaque(nc);
722
723 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
724 return 0;
725 return 1;
726}
727
728static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
729 int size)
730{
731 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
732 int i;
733
734
735 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
736 return 0;
737 }
738
739
740 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
741 return SONIC_RCR_MC;
742 }
743
744
745 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
746 return SONIC_RCR_BC;
747 }
748
749
750 for (i = 0; i < 16; i++) {
751 if (s->regs[SONIC_CE] & (1 << i)) {
752
753 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
754 return 0;
755 }
756 }
757 }
758
759 return -1;
760}
761
762static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
763 size_t pkt_size)
764{
765 dp8393xState *s = qemu_get_nic_opaque(nc);
766 int packet_type;
767 uint32_t available, address;
768 int width, rx_len, padded_len;
769 uint32_t checksum;
770 int size;
771
772 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
773 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
774
775 if (s->last_rba_is_full) {
776 return pkt_size;
777 }
778
779 rx_len = pkt_size + sizeof(checksum);
780 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
781 width = 2;
782 padded_len = ((rx_len - 1) | 3) + 1;
783 } else {
784 width = 1;
785 padded_len = ((rx_len - 1) | 1) + 1;
786 }
787
788 if (padded_len > dp8393x_rbwc(s) * 2) {
789 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);
790 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
791 dp8393x_update_irq(s);
792 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
793 goto done;
794 }
795
796 packet_type = dp8393x_receive_filter(s, buf, pkt_size);
797 if (packet_type < 0) {
798 DPRINTF("packet not for netcard\n");
799 return -1;
800 }
801
802
803 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
804
805 size = sizeof(uint16_t) * 1 * width;
806 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
807 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
808 (uint8_t *)s->data, size, 0);
809 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
810 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
811
812 return -1;
813 }
814
815
816
817 size = sizeof(uint16_t) * width;
818 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
819 dp8393x_put(s, width, 0, 0);
820 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
821 (uint8_t *)s->data, size, 1);
822
823
824 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
825 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
826 }
827
828
829 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
830 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
831
832
833 checksum = cpu_to_le32(crc32(0, buf, pkt_size));
834
835
836 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
837 address = dp8393x_crba(s);
838 address_space_rw(&s->as, address,
839 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, pkt_size, 1);
840 address += pkt_size;
841
842
843 address_space_rw(&s->as, address,
844 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, sizeof(checksum), 1);
845 address += sizeof(checksum);
846
847
848 if (rx_len < padded_len) {
849 size = padded_len - rx_len;
850 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
851 (uint8_t *)"\xFF\xFF\xFF", size, 1);
852 address += size;
853 }
854
855 s->regs[SONIC_CRBA1] = address >> 16;
856 s->regs[SONIC_CRBA0] = address & 0xffff;
857 available = dp8393x_rbwc(s);
858 available -= padded_len >> 1;
859 s->regs[SONIC_RBWC1] = available >> 16;
860 s->regs[SONIC_RBWC0] = available & 0xffff;
861
862
863 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
864 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
865 }
866 s->regs[SONIC_RCR] |= packet_type;
867 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
868 if (s->loopback_packet) {
869 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
870 s->loopback_packet = 0;
871 }
872
873
874 DPRINTF("Write status at %08x\n", dp8393x_crda(s));
875 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]);
876 dp8393x_put(s, width, 1, rx_len);
877 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]);
878 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]);
879 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]);
880 size = sizeof(uint16_t) * 5 * width;
881 address_space_rw(&s->as, dp8393x_crda(s),
882 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
883
884
885 size = sizeof(uint16_t) * width;
886 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
887 MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
888 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
889 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
890
891 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
892 } else {
893
894 size = sizeof(uint16_t) * width;
895 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
896 dp8393x_put(s, width, 0, 0);
897 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
898 (uint8_t *)s->data, size, true);
899
900
901 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
902 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
903 }
904
905 dp8393x_update_irq(s);
906
907 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
908 ((s->regs[SONIC_RSC] + 1) & 0x00ff);
909
910done:
911
912 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
913 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
914
915 s->last_rba_is_full = true;
916 } else {
917
918 dp8393x_do_read_rra(s);
919 }
920 }
921
922 return pkt_size;
923}
924
925static void dp8393x_reset(DeviceState *dev)
926{
927 dp8393xState *s = DP8393X(dev);
928 timer_del(s->watchdog);
929
930 memset(s->regs, 0, sizeof(s->regs));
931 s->regs[SONIC_SR] = 0x0004;
932 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
933 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
934 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
935 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
936 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
937 s->regs[SONIC_IMR] = 0;
938 s->regs[SONIC_ISR] = 0;
939 s->regs[SONIC_DCR2] = 0;
940 s->regs[SONIC_EOBC] = 0x02F8;
941 s->regs[SONIC_RSC] = 0;
942 s->regs[SONIC_CE] = 0;
943 s->regs[SONIC_RSC] = 0;
944
945
946 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
947
948 dp8393x_update_irq(s);
949}
950
951static NetClientInfo net_dp83932_info = {
952 .type = NET_CLIENT_DRIVER_NIC,
953 .size = sizeof(NICState),
954 .can_receive = dp8393x_can_receive,
955 .receive = dp8393x_receive,
956};
957
958static void dp8393x_instance_init(Object *obj)
959{
960 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
961 dp8393xState *s = DP8393X(obj);
962
963 sysbus_init_mmio(sbd, &s->mmio);
964 sysbus_init_mmio(sbd, &s->prom);
965 sysbus_init_irq(sbd, &s->irq);
966}
967
968static void dp8393x_realize(DeviceState *dev, Error **errp)
969{
970 dp8393xState *s = DP8393X(dev);
971 int i, checksum;
972 uint8_t *prom;
973 Error *local_err = NULL;
974
975 address_space_init(&s->as, s->dma_mr, "dp8393x");
976 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
977 "dp8393x-regs", 0x40 << s->it_shift);
978
979 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
980 object_get_typename(OBJECT(dev)), dev->id, s);
981 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
982
983 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
984
985 memory_region_init_ram(&s->prom, OBJECT(dev),
986 "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
987 if (local_err) {
988 error_propagate(errp, local_err);
989 return;
990 }
991 memory_region_set_readonly(&s->prom, true);
992 prom = memory_region_get_ram_ptr(&s->prom);
993 checksum = 0;
994 for (i = 0; i < 6; i++) {
995 prom[i] = s->conf.macaddr.a[i];
996 checksum += prom[i];
997 if (checksum > 0xff) {
998 checksum = (checksum + 1) & 0xff;
999 }
1000 }
1001 prom[7] = 0xff - checksum;
1002}
1003
1004static const VMStateDescription vmstate_dp8393x = {
1005 .name = "dp8393x",
1006 .version_id = 0,
1007 .minimum_version_id = 0,
1008 .fields = (VMStateField []) {
1009 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
1010 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
1011 VMSTATE_END_OF_LIST()
1012 }
1013};
1014
1015static Property dp8393x_properties[] = {
1016 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
1017 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
1018 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
1019 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
1020 DEFINE_PROP_END_OF_LIST(),
1021};
1022
1023static void dp8393x_class_init(ObjectClass *klass, void *data)
1024{
1025 DeviceClass *dc = DEVICE_CLASS(klass);
1026
1027 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1028 dc->realize = dp8393x_realize;
1029 dc->reset = dp8393x_reset;
1030 dc->vmsd = &vmstate_dp8393x;
1031 dc->props = dp8393x_properties;
1032
1033 dc->user_creatable = false;
1034}
1035
1036static const TypeInfo dp8393x_info = {
1037 .name = TYPE_DP8393X,
1038 .parent = TYPE_SYS_BUS_DEVICE,
1039 .instance_size = sizeof(dp8393xState),
1040 .instance_init = dp8393x_instance_init,
1041 .class_init = dp8393x_class_init,
1042};
1043
1044static void dp8393x_register_types(void)
1045{
1046 type_register_static(&dp8393x_info);
1047}
1048
1049type_init(dp8393x_register_types)
1050