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20#include "qemu/osdep.h"
21#include "sysemu/reset.h"
22#include "qapi/error.h"
23#include "qemu/log.h"
24#include "qemu/module.h"
25#include "target/ppc/cpu.h"
26#include "hw/ppc/ppc.h"
27#include "hw/ppc/pnv.h"
28#include "hw/ppc/pnv_core.h"
29#include "hw/ppc/pnv_xscom.h"
30#include "hw/ppc/xics.h"
31#include "hw/qdev-properties.h"
32
33static const char *pnv_core_cpu_typename(PnvCore *pc)
34{
35 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
36 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
37 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
38 const char *cpu_type = object_class_get_name(object_class_by_name(s));
39 g_free(s);
40 return cpu_type;
41}
42
43static void pnv_core_cpu_reset(PowerPCCPU *cpu, PnvChip *chip)
44{
45 CPUState *cs = CPU(cpu);
46 CPUPPCState *env = &cpu->env;
47 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
48
49 cpu_reset(cs);
50
51
52
53
54
55 env->gpr[3] = PNV_FDT_ADDR;
56 env->nip = 0x10;
57 env->msr |= MSR_HVB;
58
59 pcc->intc_reset(chip, cpu);
60}
61
62
63
64
65#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
66#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
67
68static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
69 unsigned int width)
70{
71 uint32_t offset = addr >> 3;
72 uint64_t val = 0;
73
74
75 switch (offset) {
76 case PNV_XSCOM_EX_DTS_RESULT0:
77 val = 0x26f024f023f0000ull;
78 break;
79 case PNV_XSCOM_EX_DTS_RESULT1:
80 val = 0x24f000000000000ull;
81 break;
82 default:
83 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
84 addr);
85 }
86
87 return val;
88}
89
90static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
91 unsigned int width)
92{
93 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
94 addr);
95}
96
97static const MemoryRegionOps pnv_core_power8_xscom_ops = {
98 .read = pnv_core_power8_xscom_read,
99 .write = pnv_core_power8_xscom_write,
100 .valid.min_access_size = 8,
101 .valid.max_access_size = 8,
102 .impl.min_access_size = 8,
103 .impl.max_access_size = 8,
104 .endianness = DEVICE_BIG_ENDIAN,
105};
106
107
108
109
110
111#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
112#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
113
114static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
115 unsigned int width)
116{
117 uint32_t offset = addr >> 3;
118 uint64_t val = 0;
119
120
121 switch (offset) {
122 case PNV_XSCOM_EX_DTS_RESULT0:
123 val = 0x26f024f023f0000ull;
124 break;
125 case PNV_XSCOM_EX_DTS_RESULT1:
126 val = 0x24f000000000000ull;
127 break;
128 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
129 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
130 val = 0x0;
131 break;
132 default:
133 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
134 addr);
135 }
136
137 return val;
138}
139
140static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
141 unsigned int width)
142{
143 uint32_t offset = addr >> 3;
144
145 switch (offset) {
146 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
147 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
148 break;
149 default:
150 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
151 addr);
152 }
153}
154
155static const MemoryRegionOps pnv_core_power9_xscom_ops = {
156 .read = pnv_core_power9_xscom_read,
157 .write = pnv_core_power9_xscom_write,
158 .valid.min_access_size = 8,
159 .valid.max_access_size = 8,
160 .impl.min_access_size = 8,
161 .impl.max_access_size = 8,
162 .endianness = DEVICE_BIG_ENDIAN,
163};
164
165static void pnv_core_cpu_realize(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
166{
167 CPUPPCState *env = &cpu->env;
168 int core_pir;
169 int thread_index = 0;
170 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
171 Error *local_err = NULL;
172 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
173
174 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
175 if (local_err) {
176 error_propagate(errp, local_err);
177 return;
178 }
179
180 pcc->intc_create(chip, cpu, &local_err);
181 if (local_err) {
182 error_propagate(errp, local_err);
183 return;
184 }
185
186 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
187
188
189
190
191
192
193 pir->default_value = core_pir + thread_index;
194
195
196 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
197}
198
199static void pnv_core_reset(void *dev)
200{
201 CPUCore *cc = CPU_CORE(dev);
202 PnvCore *pc = PNV_CORE(dev);
203 int i;
204
205 for (i = 0; i < cc->nr_threads; i++) {
206 pnv_core_cpu_reset(pc->threads[i], pc->chip);
207 }
208}
209
210static void pnv_core_realize(DeviceState *dev, Error **errp)
211{
212 PnvCore *pc = PNV_CORE(OBJECT(dev));
213 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
214 CPUCore *cc = CPU_CORE(OBJECT(dev));
215 const char *typename = pnv_core_cpu_typename(pc);
216 Error *local_err = NULL;
217 void *obj;
218 int i, j;
219 char name[32];
220 Object *chip;
221
222 chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
223 if (!chip) {
224 error_propagate_prepend(errp, local_err,
225 "required link 'chip' not found: ");
226 return;
227 }
228 pc->chip = PNV_CHIP(chip);
229
230 pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
231 for (i = 0; i < cc->nr_threads; i++) {
232 PowerPCCPU *cpu;
233
234 obj = object_new(typename);
235 cpu = POWERPC_CPU(obj);
236
237 pc->threads[i] = POWERPC_CPU(obj);
238
239 snprintf(name, sizeof(name), "thread[%d]", i);
240 object_property_add_child(OBJECT(pc), name, obj, &error_abort);
241 object_property_add_alias(obj, "core-pir", OBJECT(pc),
242 "pir", &error_abort);
243
244 cpu->machine_data = g_new0(PnvCPUState, 1);
245
246 object_unref(obj);
247 }
248
249 for (j = 0; j < cc->nr_threads; j++) {
250 pnv_core_cpu_realize(pc->threads[j], pc->chip, &local_err);
251 if (local_err) {
252 goto err;
253 }
254 }
255
256 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
257 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
258 pc, name, PNV_XSCOM_EX_SIZE);
259
260 qemu_register_reset(pnv_core_reset, pc);
261 return;
262
263err:
264 while (--i >= 0) {
265 obj = OBJECT(pc->threads[i]);
266 object_unparent(obj);
267 }
268 g_free(pc->threads);
269 error_propagate(errp, local_err);
270}
271
272static void pnv_core_cpu_unrealize(PowerPCCPU *cpu, PnvChip *chip)
273{
274 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
275 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
276
277 pcc->intc_destroy(chip, cpu);
278 cpu_remove_sync(CPU(cpu));
279 cpu->machine_data = NULL;
280 g_free(pnv_cpu);
281 object_unparent(OBJECT(cpu));
282}
283
284static void pnv_core_unrealize(DeviceState *dev, Error **errp)
285{
286 PnvCore *pc = PNV_CORE(dev);
287 CPUCore *cc = CPU_CORE(dev);
288 int i;
289
290 qemu_unregister_reset(pnv_core_reset, pc);
291
292 for (i = 0; i < cc->nr_threads; i++) {
293 pnv_core_cpu_unrealize(pc->threads[i], pc->chip);
294 }
295 g_free(pc->threads);
296}
297
298static Property pnv_core_properties[] = {
299 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
300 DEFINE_PROP_END_OF_LIST(),
301};
302
303static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
304{
305 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
306
307 pcc->xscom_ops = &pnv_core_power8_xscom_ops;
308}
309
310static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
311{
312 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
313
314 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
315}
316
317static void pnv_core_class_init(ObjectClass *oc, void *data)
318{
319 DeviceClass *dc = DEVICE_CLASS(oc);
320
321 dc->realize = pnv_core_realize;
322 dc->unrealize = pnv_core_unrealize;
323 dc->props = pnv_core_properties;
324}
325
326#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
327 { \
328 .parent = TYPE_PNV_CORE, \
329 .name = PNV_CORE_TYPE_NAME(cpu_model), \
330 .class_init = pnv_core_##family##_class_init, \
331 }
332
333static const TypeInfo pnv_core_infos[] = {
334 {
335 .name = TYPE_PNV_CORE,
336 .parent = TYPE_CPU_CORE,
337 .instance_size = sizeof(PnvCore),
338 .class_size = sizeof(PnvCoreClass),
339 .class_init = pnv_core_class_init,
340 .abstract = true,
341 },
342 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
343 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
344 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
345 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
346};
347
348DEFINE_TYPES(pnv_core_infos)
349
350
351
352
353
354#define P9X_EX_NCU_SPEC_BAR 0x11010
355
356static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
357 unsigned int width)
358{
359 uint32_t offset = addr >> 3;
360 uint64_t val = -1;
361
362 switch (offset) {
363 case P9X_EX_NCU_SPEC_BAR:
364 case P9X_EX_NCU_SPEC_BAR + 0x400:
365 val = 0;
366 break;
367 default:
368 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
369 offset);
370 }
371
372 return val;
373}
374
375static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
376 unsigned int width)
377{
378 uint32_t offset = addr >> 3;
379
380 switch (offset) {
381 case P9X_EX_NCU_SPEC_BAR:
382 case P9X_EX_NCU_SPEC_BAR + 0x400:
383 break;
384 default:
385 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
386 offset);
387 }
388}
389
390static const MemoryRegionOps pnv_quad_xscom_ops = {
391 .read = pnv_quad_xscom_read,
392 .write = pnv_quad_xscom_write,
393 .valid.min_access_size = 8,
394 .valid.max_access_size = 8,
395 .impl.min_access_size = 8,
396 .impl.max_access_size = 8,
397 .endianness = DEVICE_BIG_ENDIAN,
398};
399
400static void pnv_quad_realize(DeviceState *dev, Error **errp)
401{
402 PnvQuad *eq = PNV_QUAD(dev);
403 char name[32];
404
405 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
406 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
407 eq, name, PNV9_XSCOM_EQ_SIZE);
408}
409
410static Property pnv_quad_properties[] = {
411 DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
412 DEFINE_PROP_END_OF_LIST(),
413};
414
415static void pnv_quad_class_init(ObjectClass *oc, void *data)
416{
417 DeviceClass *dc = DEVICE_CLASS(oc);
418
419 dc->realize = pnv_quad_realize;
420 dc->props = pnv_quad_properties;
421}
422
423static const TypeInfo pnv_quad_info = {
424 .name = TYPE_PNV_QUAD,
425 .parent = TYPE_DEVICE,
426 .instance_size = sizeof(PnvQuad),
427 .class_init = pnv_quad_class_init,
428};
429
430static void pnv_core_register_types(void)
431{
432 type_register_static(&pnv_quad_info);
433}
434
435type_init(pnv_core_register_types)
436
