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20#include "qemu/osdep.h"
21#include "qemu/log.h"
22#include "qemu/module.h"
23#include "sysemu/hw_accel.h"
24#include "target/ppc/cpu.h"
25#include "hw/sysbus.h"
26
27#include "hw/ppc/fdt.h"
28#include "hw/ppc/pnv.h"
29#include "hw/ppc/pnv_xscom.h"
30
31#include <libfdt.h>
32
33
34#define PRD_P8_IPOLL_REG_MASK 0x01020013
35#define PRD_P8_IPOLL_REG_STATUS 0x01020014
36#define PRD_P9_IPOLL_REG_MASK 0x000F0033
37#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
38
39
40#define P8_PBA_BAR0 0x2013f00
41#define P8_PBA_BAR2 0x2013f02
42#define P8_PBA_BARMASK0 0x2013f04
43#define P8_PBA_BARMASK2 0x2013f06
44#define P9_PBA_BAR0 0x5012b00
45#define P9_PBA_BAR2 0x5012b02
46#define P9_PBA_BARMASK0 0x5012b04
47#define P9_PBA_BARMASK2 0x5012b06
48
49static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
50{
51
52
53
54
55 if (cs) {
56 PowerPCCPU *cpu = POWERPC_CPU(cs);
57 CPUPPCState *env = &cpu->env;
58
59
60
61
62
63 cpu_synchronize_state(cs);
64 env->spr[SPR_HMER] |= hmer_bits;
65 }
66}
67
68static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
69{
70 addr &= (PNV_XSCOM_SIZE - 1);
71
72 if (pnv_chip_is_power9(chip)) {
73 return addr >> 3;
74 } else {
75 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
76 }
77}
78
79static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
80{
81 switch (pcba) {
82 case 0xf000f:
83 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
84 case 0x18002:
85 return 0;
86
87 case P9_PBA_BAR0:
88 return PNV9_HOMER_BASE(chip);
89 case P8_PBA_BAR0:
90 return PNV_HOMER_BASE(chip);
91
92 case P9_PBA_BARMASK0:
93 return PNV9_HOMER_SIZE;
94 case P8_PBA_BARMASK0:
95 return PNV_HOMER_SIZE;
96
97 case P9_PBA_BAR2:
98 return PNV9_OCC_COMMON_AREA(chip);
99 case P8_PBA_BAR2:
100 return PNV_OCC_COMMON_AREA(chip);
101
102 case P9_PBA_BARMASK2:
103 return PNV9_OCC_COMMON_AREA_SIZE;
104 case P8_PBA_BARMASK2:
105 return PNV_OCC_COMMON_AREA_SIZE;
106
107 case 0x1010c00:
108 case 0x1010c03:
109
110
111 case PRD_P8_IPOLL_REG_MASK:
112 case PRD_P8_IPOLL_REG_STATUS:
113 case PRD_P9_IPOLL_REG_MASK:
114 case PRD_P9_IPOLL_REG_STATUS:
115
116
117 case 0x0090018:
118 case 0x0090012:
119 case 0x0090013:
120
121
122 case 0x2020007:
123 case 0x2020009:
124 case 0x202000f:
125 return 0;
126 case 0x2013f01:
127 case 0x2013f03:
128 case 0x2013f05:
129 case 0x2013f07:
130 return 0;
131 case 0x2013028:
132 case 0x201302a:
133 case 0x2013801:
134 case 0x2013802:
135
136
137 case 0x2010841:
138 case 0x2010842:
139 case 0x201082a:
140 case 0x2010828:
141 case 0x4010841:
142 case 0x4010842:
143 case 0x401082a:
144 case 0x4010828:
145 return 0;
146 default:
147 return -1;
148 }
149}
150
151static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
152{
153
154 switch (pcba) {
155 case 0xf000f:
156 case 0x1010c00:
157 case 0x1010c01:
158 case 0x1010c02:
159 case 0x1010c03:
160 case 0x1010c04:
161 case 0x1010c05:
162
163 case 0x0090018:
164 case 0x0090012:
165 case 0x0090013:
166
167
168 case 0x2020007:
169 case 0x2020009:
170 case 0x202000f:
171
172 case 0x2013028:
173 case 0x201302a:
174 case 0x2013801:
175 case 0x2013802:
176
177
178 case 0x2010841:
179 case 0x2010842:
180 case 0x201082a:
181 case 0x2010828:
182 case 0x4010841:
183 case 0x4010842:
184 case 0x401082a:
185 case 0x4010828:
186
187
188 case PRD_P8_IPOLL_REG_MASK:
189 case PRD_P8_IPOLL_REG_STATUS:
190 case PRD_P9_IPOLL_REG_MASK:
191 case PRD_P9_IPOLL_REG_STATUS:
192 return true;
193 default:
194 return false;
195 }
196}
197
198static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
199{
200 PnvChip *chip = opaque;
201 uint32_t pcba = pnv_xscom_pcba(chip, addr);
202 uint64_t val = 0;
203 MemTxResult result;
204
205
206 val = xscom_read_default(chip, pcba);
207 if (val != -1) {
208 goto complete;
209 }
210
211 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
212 MEMTXATTRS_UNSPECIFIED, &result);
213 if (result != MEMTX_OK) {
214 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
215 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
216 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
217 return 0;
218 }
219
220complete:
221 xscom_complete(current_cpu, HMER_XSCOM_DONE);
222 return val;
223}
224
225static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
226 unsigned width)
227{
228 PnvChip *chip = opaque;
229 uint32_t pcba = pnv_xscom_pcba(chip, addr);
230 MemTxResult result;
231
232
233 if (xscom_write_default(chip, pcba, val)) {
234 goto complete;
235 }
236
237 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
238 MEMTXATTRS_UNSPECIFIED, &result);
239 if (result != MEMTX_OK) {
240 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
241 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
242 addr, pcba, val);
243 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
244 return;
245 }
246
247complete:
248 xscom_complete(current_cpu, HMER_XSCOM_DONE);
249}
250
251const MemoryRegionOps pnv_xscom_ops = {
252 .read = xscom_read,
253 .write = xscom_write,
254 .valid.min_access_size = 8,
255 .valid.max_access_size = 8,
256 .impl.min_access_size = 8,
257 .impl.max_access_size = 8,
258 .endianness = DEVICE_BIG_ENDIAN,
259};
260
261void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
262{
263 SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
264 char *name;
265
266 name = g_strdup_printf("xscom-%x", chip->chip_id);
267 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
268 chip, name, size);
269 sysbus_init_mmio(sbd, &chip->xscom_mmio);
270
271 memory_region_init(&chip->xscom, OBJECT(chip), name, size);
272 address_space_init(&chip->xscom_as, &chip->xscom, name);
273 g_free(name);
274}
275
276static const TypeInfo pnv_xscom_interface_info = {
277 .name = TYPE_PNV_XSCOM_INTERFACE,
278 .parent = TYPE_INTERFACE,
279 .class_size = sizeof(PnvXScomInterfaceClass),
280};
281
282static void pnv_xscom_register_types(void)
283{
284 type_register_static(&pnv_xscom_interface_info);
285}
286
287type_init(pnv_xscom_register_types)
288
289typedef struct ForeachPopulateArgs {
290 void *fdt;
291 int xscom_offset;
292} ForeachPopulateArgs;
293
294static int xscom_dt_child(Object *child, void *opaque)
295{
296 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
297 ForeachPopulateArgs *args = opaque;
298 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
299 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
300
301 if (xc->dt_xscom) {
302 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
303 }
304 }
305 return 0;
306}
307
308static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
309static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
310
311int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
312{
313 uint64_t reg[2];
314 int xscom_offset;
315 ForeachPopulateArgs args;
316 char *name;
317
318 if (pnv_chip_is_power9(chip)) {
319 reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
320 reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
321 } else {
322 reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
323 reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
324 }
325
326 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
327 xscom_offset = fdt_add_subnode(fdt, root_offset, name);
328 _FDT(xscom_offset);
329 g_free(name);
330 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
331 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
332 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
333 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
334
335 if (pnv_chip_is_power9(chip)) {
336 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
337 sizeof(compat_p9))));
338 } else {
339 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
340 sizeof(compat_p8))));
341 }
342
343 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
344
345 args.fdt = fdt;
346 args.xscom_offset = xscom_offset;
347
348 object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
349 return 0;
350}
351
352void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
353{
354 memory_region_add_subregion(&chip->xscom, offset << 3, mr);
355}
356
357void pnv_xscom_region_init(MemoryRegion *mr,
358 struct Object *owner,
359 const MemoryRegionOps *ops,
360 void *opaque,
361 const char *name,
362 uint64_t size)
363{
364 memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
365}
366
