1/* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_DEFS_H 20#define CPU_DEFS_H 21 22#ifndef NEED_CPU_H 23#error cpu.h included from common code 24#endif 25 26#include "qemu/host-utils.h" 27#include "qemu/thread.h" 28#ifdef CONFIG_TCG 29#include "tcg-target.h" 30#endif 31#ifndef CONFIG_USER_ONLY 32#include "exec/hwaddr.h" 33#endif 34#include "exec/memattrs.h" 35#include "hw/core/cpu.h" 36 37#include "cpu-param.h" 38 39#ifndef TARGET_LONG_BITS 40# error TARGET_LONG_BITS must be defined in cpu-param.h 41#endif 42#ifndef NB_MMU_MODES 43# error NB_MMU_MODES must be defined in cpu-param.h 44#endif 45#ifndef TARGET_PHYS_ADDR_SPACE_BITS 46# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 47#endif 48#ifndef TARGET_VIRT_ADDR_SPACE_BITS 49# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 50#endif 51#ifndef TARGET_PAGE_BITS 52# ifdef TARGET_PAGE_BITS_VARY 53# ifndef TARGET_PAGE_BITS_MIN 54# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 55# endif 56# else 57# error TARGET_PAGE_BITS must be defined in cpu-param.h 58# endif 59#endif 60 61#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 62 63/* target_ulong is the type of a virtual address */ 64#if TARGET_LONG_SIZE == 4 65typedef int32_t target_long; 66typedef uint32_t target_ulong; 67#define TARGET_FMT_lx "%08x" 68#define TARGET_FMT_ld "%d" 69#define TARGET_FMT_lu "%u" 70#elif TARGET_LONG_SIZE == 8 71typedef int64_t target_long; 72typedef uint64_t target_ulong; 73#define TARGET_FMT_lx "%016" PRIx64 74#define TARGET_FMT_ld "%" PRId64 75#define TARGET_FMT_lu "%" PRIu64 76#else 77#error TARGET_LONG_SIZE undefined 78#endif 79 80#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 81 82/* use a fully associative victim tlb of 8 entries */ 83#define CPU_VTLB_SIZE 8 84 85#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 86#define CPU_TLB_ENTRY_BITS 4 87#else 88#define CPU_TLB_ENTRY_BITS 5 89#endif 90 91#define CPU_TLB_DYN_MIN_BITS 6 92#define CPU_TLB_DYN_DEFAULT_BITS 8 93 94# if HOST_LONG_BITS == 32 95/* Make sure we do not require a double-word shift for the TLB load */ 96# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 97# else /* HOST_LONG_BITS == 64 */ 98/* 99 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 100 * 2**34 == 16G of address space. This is roughly what one would expect a 101 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 102 * Skylake's Level-2 STLB has 16 1G entries. 103 * Also, make sure we do not size the TLB past the guest's address space. 104 */ 105# define CPU_TLB_DYN_MAX_BITS \ 106 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 107# endif 108 109typedef struct CPUTLBEntry { 110 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 111 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 112 go directly to ram. 113 bit 3 : indicates that the entry is invalid 114 bit 2..0 : zero 115 */ 116 union { 117 struct { 118 target_ulong addr_read; 119 target_ulong addr_write; 120 target_ulong addr_code; 121 /* Addend to virtual address to get host address. IO accesses 122 use the corresponding iotlb value. */ 123 uintptr_t addend; 124 }; 125 /* padding to get a power of two size */ 126 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 127 }; 128} CPUTLBEntry; 129 130QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 131 132/* The IOTLB is not accessed directly inline by generated TCG code, 133 * so the CPUIOTLBEntry layout is not as critical as that of the 134 * CPUTLBEntry. (This is also why we don't want to combine the two 135 * structs into one.) 136 */ 137typedef struct CPUIOTLBEntry { 138 /* 139 * @addr contains: 140 * - in the lower TARGET_PAGE_BITS, a physical section number 141 * - with the lower TARGET_PAGE_BITS masked off, an offset which 142 * must be added to the virtual address to obtain: 143 * + the ram_addr_t of the target RAM (if the physical section 144 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 145 * + the offset within the target MemoryRegion (otherwise) 146 */ 147 hwaddr addr; 148 MemTxAttrs attrs; 149} CPUIOTLBEntry; 150 151/* 152 * Data elements that are per MMU mode, minus the bits accessed by 153 * the TCG fast path. 154 */ 155typedef struct CPUTLBDesc { 156 /* 157 * Describe a region covering all of the large pages allocated 158 * into the tlb. When any page within this region is flushed, 159 * we must flush the entire tlb. The region is matched if 160 * (addr & large_page_mask) == large_page_addr. 161 */ 162 target_ulong large_page_addr; 163 target_ulong large_page_mask; 164 /* host time (in ns) at the beginning of the time window */ 165 int64_t window_begin_ns; 166 /* maximum number of entries observed in the window */ 167 size_t window_max_entries; 168 size_t n_used_entries; 169 /* The next index to use in the tlb victim table. */ 170 size_t vindex; 171 /* The tlb victim table, in two parts. */ 172 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 173 CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; 174 /* The iotlb. */ 175 CPUIOTLBEntry *iotlb; 176} CPUTLBDesc; 177 178/* 179 * Data elements that are per MMU mode, accessed by the fast path. 180 * The structure is aligned to aid loading the pair with one insn. 181 */ 182typedef struct CPUTLBDescFast { 183 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 184 uintptr_t mask; 185 /* The array of tlb entries itself. */ 186 CPUTLBEntry *table; 187} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 188 189/* 190 * Data elements that are shared between all MMU modes. 191 */ 192typedef struct CPUTLBCommon { 193 /* Serialize updates to f.table and d.vtable, and others as noted. */ 194 QemuSpin lock; 195 /* 196 * Within dirty, for each bit N, modifications have been made to 197 * mmu_idx N since the last time that mmu_idx was flushed. 198 * Protected by tlb_c.lock. 199 */ 200 uint16_t dirty; 201 /* 202 * Statistics. These are not lock protected, but are read and 203 * written atomically. This allows the monitor to print a snapshot 204 * of the stats without interfering with the cpu. 205 */ 206 size_t full_flush_count; 207 size_t part_flush_count; 208 size_t elide_flush_count; 209} CPUTLBCommon; 210 211/* 212 * The entire softmmu tlb, for all MMU modes. 213 * The meaning of each of the MMU modes is defined in the target code. 214 * Since this is placed within CPUNegativeOffsetState, the smallest 215 * negative offsets are at the end of the struct. 216 */ 217 218typedef struct CPUTLB { 219 CPUTLBCommon c; 220 CPUTLBDesc d[NB_MMU_MODES]; 221 CPUTLBDescFast f[NB_MMU_MODES]; 222} CPUTLB; 223 224/* This will be used by TCG backends to compute offsets. */ 225#define TLB_MASK_TABLE_OFS(IDX) \ 226 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 227 228#else 229 230typedef struct CPUTLB { } CPUTLB; 231 232#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 233 234/* 235 * This structure must be placed in ArchCPU immediately 236 * before CPUArchState, as a field named "neg". 237 */ 238typedef struct CPUNegativeOffsetState { 239 CPUTLB tlb; 240 IcountDecr icount_decr; 241} CPUNegativeOffsetState; 242 243#endif 244