1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "exec/memory.h"
5#include "sysemu/dma.h"
6
7
8#include "hw/isa/isa.h"
9
10#include "hw/pci/pcie.h"
11
12extern bool pci_available;
13
14
15
16#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
17#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
18#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19#define PCI_FUNC(devfn) ((devfn) & 0x07)
20#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
21#define PCI_BUS_MAX 256
22#define PCI_DEVFN_MAX 256
23#define PCI_SLOT_MAX 32
24#define PCI_FUNC_MAX 8
25
26
27#include "hw/pci/pci_ids.h"
28
29
30
31
32#define PCI_DEVICE_ID_IBM_440GX 0x027f
33#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
34
35
36#define PCI_VENDOR_ID_HITACHI 0x1054
37#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
38
39
40#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
41#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
42#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
43#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
44#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
45
46
47#define PCI_DEVICE_ID_REALTEK_8029 0x8029
48
49
50#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
51
52
53#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
54
55
56#define PCI_VENDOR_ID_QEMU 0x1234
57#define PCI_DEVICE_ID_QEMU_VGA 0x1111
58#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
59
60
61#define PCI_VENDOR_ID_VMWARE 0x15ad
62#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64#define PCI_DEVICE_ID_VMWARE_NET 0x0720
65#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69
70
71#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72#define PCI_DEVICE_ID_INTEL_82557 0x1229
73#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
74
75
76#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78#define PCI_SUBDEVICE_ID_QEMU 0x1100
79
80#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
88#define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
89
90#define PCI_VENDOR_ID_REDHAT 0x1b36
91#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
92#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
93#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
94#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
95#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
96#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
97#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
98#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
99#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
100#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
101#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
102#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
103#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
104#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
105#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
106#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
107
108#define FMT_PCIBUS PRIx64
109
110typedef uint64_t pcibus_t;
111
112struct PCIHostDeviceAddress {
113 unsigned int domain;
114 unsigned int bus;
115 unsigned int slot;
116 unsigned int function;
117};
118
119typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
120 uint32_t address, uint32_t data, int len);
121typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
122 uint32_t address, int len);
123typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
124 pcibus_t addr, pcibus_t size, int type);
125typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
126
127typedef struct PCIIORegion {
128 pcibus_t addr;
129#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
130 pcibus_t size;
131 uint8_t type;
132 MemoryRegion *memory;
133 MemoryRegion *address_space;
134} PCIIORegion;
135
136#define PCI_ROM_SLOT 6
137#define PCI_NUM_REGIONS 7
138
139enum {
140 QEMU_PCI_VGA_MEM,
141 QEMU_PCI_VGA_IO_LO,
142 QEMU_PCI_VGA_IO_HI,
143 QEMU_PCI_VGA_NUM_REGIONS,
144};
145
146#define QEMU_PCI_VGA_MEM_BASE 0xa0000
147#define QEMU_PCI_VGA_MEM_SIZE 0x20000
148#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
149#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
150#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
151#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
152
153#include "hw/pci/pci_regs.h"
154
155
156#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
157
158
159#define PCI_CONFIG_HEADER_SIZE 0x40
160
161#define PCI_CONFIG_SPACE_SIZE 0x100
162
163#define PCIE_CONFIG_SPACE_SIZE 0x1000
164
165#define PCI_NUM_PINS 4
166
167
168enum {
169 QEMU_PCI_CAP_MSI = 0x1,
170 QEMU_PCI_CAP_MSIX = 0x2,
171 QEMU_PCI_CAP_EXPRESS = 0x4,
172
173
174#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
175 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
176
177
178#define QEMU_PCI_CAP_SERR_BITNR 4
179 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
180
181#define QEMU_PCI_SHPC_BITNR 5
182 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
183#define QEMU_PCI_SLOTID_BITNR 6
184 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
185
186#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
187 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
188
189#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
190 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
191#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
192 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
193};
194
195#define TYPE_PCI_DEVICE "pci-device"
196#define PCI_DEVICE(obj) \
197 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
198#define PCI_DEVICE_CLASS(klass) \
199 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
200#define PCI_DEVICE_GET_CLASS(obj) \
201 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
202
203
204#define INTERFACE_PCIE_DEVICE "pci-express-device"
205
206
207#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
208
209typedef struct PCIINTxRoute {
210 enum {
211 PCI_INTX_ENABLED,
212 PCI_INTX_INVERTED,
213 PCI_INTX_DISABLED,
214 } mode;
215 int irq;
216} PCIINTxRoute;
217
218typedef struct PCIDeviceClass {
219 DeviceClass parent_class;
220
221 void (*realize)(PCIDevice *dev, Error **errp);
222 PCIUnregisterFunc *exit;
223 PCIConfigReadFunc *config_read;
224 PCIConfigWriteFunc *config_write;
225
226 uint16_t vendor_id;
227 uint16_t device_id;
228 uint8_t revision;
229 uint16_t class_id;
230 uint16_t subsystem_vendor_id;
231 uint16_t subsystem_id;
232
233
234
235
236
237
238 bool is_bridge;
239
240
241 const char *romfile;
242} PCIDeviceClass;
243
244typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
245typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
246 MSIMessage msg);
247typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
248typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
249 unsigned int vector_start,
250 unsigned int vector_end);
251
252enum PCIReqIDType {
253 PCI_REQ_ID_INVALID = 0,
254 PCI_REQ_ID_BDF,
255 PCI_REQ_ID_SECONDARY_BUS,
256 PCI_REQ_ID_MAX,
257};
258typedef enum PCIReqIDType PCIReqIDType;
259
260struct PCIReqIDCache {
261 PCIDevice *dev;
262 PCIReqIDType type;
263};
264typedef struct PCIReqIDCache PCIReqIDCache;
265
266struct PCIDevice {
267 DeviceState qdev;
268 bool partially_hotplugged;
269
270
271 uint8_t *config;
272
273
274
275 uint8_t *cmask;
276
277
278 uint8_t *wmask;
279
280
281 uint8_t *w1cmask;
282
283
284 uint8_t *used;
285
286
287 int32_t devfn;
288
289
290
291
292 PCIReqIDCache requester_id_cache;
293 char name[64];
294 PCIIORegion io_regions[PCI_NUM_REGIONS];
295 AddressSpace bus_master_as;
296 MemoryRegion bus_master_container_region;
297 MemoryRegion bus_master_enable_region;
298
299
300 PCIConfigReadFunc *config_read;
301 PCIConfigWriteFunc *config_write;
302
303
304 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
305 bool has_vga;
306
307
308 uint8_t irq_state;
309
310
311 uint32_t cap_present;
312
313
314 uint8_t msix_cap;
315
316
317 int msix_entries_nr;
318
319
320 uint8_t *msix_table;
321 uint8_t *msix_pba;
322
323 MemoryRegion msix_exclusive_bar;
324
325 MemoryRegion msix_table_mmio;
326 MemoryRegion msix_pba_mmio;
327
328 unsigned *msix_entry_used;
329
330 bool msix_function_masked;
331
332 int32_t version_id;
333
334
335 uint8_t msi_cap;
336
337
338 PCIExpressDevice exp;
339
340
341 SHPCDevice *shpc;
342
343
344 char *romfile;
345 bool has_rom;
346 MemoryRegion rom;
347 uint32_t rom_bar;
348
349
350 PCIINTxRoutingNotifier intx_routing_notifier;
351
352
353 MSIVectorUseNotifier msix_vector_use_notifier;
354 MSIVectorReleaseNotifier msix_vector_release_notifier;
355 MSIVectorPollNotifier msix_vector_poll_notifier;
356
357
358 char *failover_pair_id;
359};
360
361void pci_register_bar(PCIDevice *pci_dev, int region_num,
362 uint8_t attr, MemoryRegion *memory);
363void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
364 MemoryRegion *io_lo, MemoryRegion *io_hi);
365void pci_unregister_vga(PCIDevice *pci_dev);
366pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
367
368int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
369 uint8_t offset, uint8_t size,
370 Error **errp);
371
372void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
373
374uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
375
376
377uint32_t pci_default_read_config(PCIDevice *d,
378 uint32_t address, int len);
379void pci_default_write_config(PCIDevice *d,
380 uint32_t address, uint32_t val, int len);
381void pci_device_save(PCIDevice *s, QEMUFile *f);
382int pci_device_load(PCIDevice *s, QEMUFile *f);
383MemoryRegion *pci_address_space(PCIDevice *dev);
384MemoryRegion *pci_address_space_io(PCIDevice *dev);
385
386
387
388
389
390int pci_bar(PCIDevice *d, int reg);
391
392typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
393typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
394typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
395
396#define TYPE_PCI_BUS "PCI"
397#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
398#define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
399#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
400#define TYPE_PCIE_BUS "PCIE"
401
402bool pci_bus_is_express(PCIBus *bus);
403
404void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
405 const char *name,
406 MemoryRegion *address_space_mem,
407 MemoryRegion *address_space_io,
408 uint8_t devfn_min, const char *typename);
409PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
410 MemoryRegion *address_space_mem,
411 MemoryRegion *address_space_io,
412 uint8_t devfn_min, const char *typename);
413void pci_root_bus_cleanup(PCIBus *bus);
414void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
415 void *irq_opaque, int nirq);
416void pci_bus_irqs_cleanup(PCIBus *bus);
417int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
418
419static inline int pci_swizzle(int slot, int pin)
420{
421 return (slot + pin) % PCI_NUM_PINS;
422}
423int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
424PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
425 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
426 void *irq_opaque,
427 MemoryRegion *address_space_mem,
428 MemoryRegion *address_space_io,
429 uint8_t devfn_min, int nirq,
430 const char *typename);
431void pci_unregister_root_bus(PCIBus *bus);
432void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
433PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
434bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
435void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
436void pci_device_set_intx_routing_notifier(PCIDevice *dev,
437 PCIINTxRoutingNotifier notifier);
438void pci_device_reset(PCIDevice *dev);
439
440PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
441 const char *default_model,
442 const char *default_devaddr);
443
444PCIDevice *pci_vga_init(PCIBus *bus);
445
446static inline PCIBus *pci_get_bus(const PCIDevice *dev)
447{
448 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
449}
450int pci_bus_num(PCIBus *s);
451static inline int pci_dev_bus_num(const PCIDevice *dev)
452{
453 return pci_bus_num(pci_get_bus(dev));
454}
455
456int pci_bus_numa_node(PCIBus *bus);
457void pci_for_each_device(PCIBus *bus, int bus_num,
458 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
459 void *opaque);
460void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
461 void (*fn)(PCIBus *bus, PCIDevice *d,
462 void *opaque),
463 void *opaque);
464void pci_for_each_bus_depth_first(PCIBus *bus,
465 void *(*begin)(PCIBus *bus, void *parent_state),
466 void (*end)(PCIBus *bus, void *state),
467 void *parent_state);
468PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
469
470
471static inline
472void pci_for_each_bus(PCIBus *bus,
473 void (*fn)(PCIBus *bus, void *opaque),
474 void *opaque)
475{
476 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
477}
478
479PCIBus *pci_device_root_bus(const PCIDevice *d);
480const char *pci_root_bus_path(PCIDevice *dev);
481PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
482int pci_qdev_find_device(const char *id, PCIDevice **pdev);
483void pci_bus_get_w64_range(PCIBus *bus, Range *range);
484
485void pci_device_deassert_intx(PCIDevice *dev);
486
487typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
488
489AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
490void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
491
492static inline void
493pci_set_byte(uint8_t *config, uint8_t val)
494{
495 *config = val;
496}
497
498static inline uint8_t
499pci_get_byte(const uint8_t *config)
500{
501 return *config;
502}
503
504static inline void
505pci_set_word(uint8_t *config, uint16_t val)
506{
507 stw_le_p(config, val);
508}
509
510static inline uint16_t
511pci_get_word(const uint8_t *config)
512{
513 return lduw_le_p(config);
514}
515
516static inline void
517pci_set_long(uint8_t *config, uint32_t val)
518{
519 stl_le_p(config, val);
520}
521
522static inline uint32_t
523pci_get_long(const uint8_t *config)
524{
525 return ldl_le_p(config);
526}
527
528
529
530
531
532
533
534
535static inline void
536pci_set_quad(uint8_t *config, uint64_t val)
537{
538 stq_le_p(config, val);
539}
540
541static inline uint64_t
542pci_get_quad(const uint8_t *config)
543{
544 return ldq_le_p(config);
545}
546
547static inline void
548pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
549{
550 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
551}
552
553static inline void
554pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
555{
556 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
557}
558
559static inline void
560pci_config_set_revision(uint8_t *pci_config, uint8_t val)
561{
562 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
563}
564
565static inline void
566pci_config_set_class(uint8_t *pci_config, uint16_t val)
567{
568 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
569}
570
571static inline void
572pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
573{
574 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
575}
576
577static inline void
578pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
579{
580 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
581}
582
583
584
585
586
587
588
589static inline uint8_t
590pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
591{
592 uint8_t val = pci_get_byte(config);
593 pci_set_byte(config, val & ~mask);
594 return val & mask;
595}
596
597static inline uint8_t
598pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
599{
600 uint8_t val = pci_get_byte(config);
601 pci_set_byte(config, val | mask);
602 return val & mask;
603}
604
605static inline uint16_t
606pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
607{
608 uint16_t val = pci_get_word(config);
609 pci_set_word(config, val & ~mask);
610 return val & mask;
611}
612
613static inline uint16_t
614pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
615{
616 uint16_t val = pci_get_word(config);
617 pci_set_word(config, val | mask);
618 return val & mask;
619}
620
621static inline uint32_t
622pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
623{
624 uint32_t val = pci_get_long(config);
625 pci_set_long(config, val & ~mask);
626 return val & mask;
627}
628
629static inline uint32_t
630pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
631{
632 uint32_t val = pci_get_long(config);
633 pci_set_long(config, val | mask);
634 return val & mask;
635}
636
637static inline uint64_t
638pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
639{
640 uint64_t val = pci_get_quad(config);
641 pci_set_quad(config, val & ~mask);
642 return val & mask;
643}
644
645static inline uint64_t
646pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
647{
648 uint64_t val = pci_get_quad(config);
649 pci_set_quad(config, val | mask);
650 return val & mask;
651}
652
653
654static inline void
655pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
656{
657 uint8_t val = pci_get_byte(config);
658 uint8_t rval = reg << ctz32(mask);
659 pci_set_byte(config, (~mask & val) | (mask & rval));
660}
661
662static inline uint8_t
663pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
664{
665 uint8_t val = pci_get_byte(config);
666 return (val & mask) >> ctz32(mask);
667}
668
669static inline void
670pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
671{
672 uint16_t val = pci_get_word(config);
673 uint16_t rval = reg << ctz32(mask);
674 pci_set_word(config, (~mask & val) | (mask & rval));
675}
676
677static inline uint16_t
678pci_get_word_by_mask(uint8_t *config, uint16_t mask)
679{
680 uint16_t val = pci_get_word(config);
681 return (val & mask) >> ctz32(mask);
682}
683
684static inline void
685pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
686{
687 uint32_t val = pci_get_long(config);
688 uint32_t rval = reg << ctz32(mask);
689 pci_set_long(config, (~mask & val) | (mask & rval));
690}
691
692static inline uint32_t
693pci_get_long_by_mask(uint8_t *config, uint32_t mask)
694{
695 uint32_t val = pci_get_long(config);
696 return (val & mask) >> ctz32(mask);
697}
698
699static inline void
700pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
701{
702 uint64_t val = pci_get_quad(config);
703 uint64_t rval = reg << ctz32(mask);
704 pci_set_quad(config, (~mask & val) | (mask & rval));
705}
706
707static inline uint64_t
708pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
709{
710 uint64_t val = pci_get_quad(config);
711 return (val & mask) >> ctz32(mask);
712}
713
714PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
715 const char *name);
716PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
717 bool multifunction,
718 const char *name);
719PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
720PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
721
722void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
723
724qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
725void pci_set_irq(PCIDevice *pci_dev, int level);
726
727static inline void pci_irq_assert(PCIDevice *pci_dev)
728{
729 pci_set_irq(pci_dev, 1);
730}
731
732static inline void pci_irq_deassert(PCIDevice *pci_dev)
733{
734 pci_set_irq(pci_dev, 0);
735}
736
737
738
739
740
741static inline void pci_irq_pulse(PCIDevice *pci_dev)
742{
743 pci_irq_assert(pci_dev);
744 pci_irq_deassert(pci_dev);
745}
746
747static inline int pci_is_express(const PCIDevice *d)
748{
749 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
750}
751
752static inline int pci_is_express_downstream_port(const PCIDevice *d)
753{
754 uint8_t type;
755
756 if (!pci_is_express(d) || !d->exp.exp_cap) {
757 return 0;
758 }
759
760 type = pcie_cap_get_type(d);
761
762 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
763}
764
765static inline uint32_t pci_config_size(const PCIDevice *d)
766{
767 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
768}
769
770static inline uint16_t pci_get_bdf(PCIDevice *dev)
771{
772 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
773}
774
775uint16_t pci_requester_id(PCIDevice *dev);
776
777
778static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
779{
780 return &dev->bus_master_as;
781}
782
783static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
784 void *buf, dma_addr_t len, DMADirection dir)
785{
786 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
787 return 0;
788}
789
790static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
791 void *buf, dma_addr_t len)
792{
793 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
794}
795
796static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
797 const void *buf, dma_addr_t len)
798{
799 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
800}
801
802#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
803 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
804 dma_addr_t addr) \
805 { \
806 return ld##_l##_dma(pci_get_address_space(dev), addr); \
807 } \
808 static inline void st##_s##_pci_dma(PCIDevice *dev, \
809 dma_addr_t addr, uint##_bits##_t val) \
810 { \
811 st##_s##_dma(pci_get_address_space(dev), addr, val); \
812 }
813
814PCI_DMA_DEFINE_LDST(ub, b, 8);
815PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
816PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
817PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
818PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
819PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
820PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
821
822#undef PCI_DMA_DEFINE_LDST
823
824static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
825 dma_addr_t *plen, DMADirection dir)
826{
827 void *buf;
828
829 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
830 return buf;
831}
832
833static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
834 DMADirection dir, dma_addr_t access_len)
835{
836 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
837}
838
839static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
840 int alloc_hint)
841{
842 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
843}
844
845extern const VMStateDescription vmstate_pci_device;
846
847#define VMSTATE_PCI_DEVICE(_field, _state) { \
848 .name = (stringify(_field)), \
849 .size = sizeof(PCIDevice), \
850 .vmsd = &vmstate_pci_device, \
851 .flags = VMS_STRUCT, \
852 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
853}
854
855#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
856 .name = (stringify(_field)), \
857 .size = sizeof(PCIDevice), \
858 .vmsd = &vmstate_pci_device, \
859 .flags = VMS_STRUCT|VMS_POINTER, \
860 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
861}
862
863MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
864
865#endif
866