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21#ifndef QEMU_PCIE_H
22#define QEMU_PCIE_H
23
24#include "hw/pci/pci_regs.h"
25#include "hw/pci/pcie_regs.h"
26#include "hw/pci/pcie_aer.h"
27#include "hw/hotplug.h"
28
29typedef enum {
30
31 PCI_EXP_HP_IND_RESERVED = PCI_EXP_SLTCTL_IND_RESERVED,
32 PCI_EXP_HP_IND_ON = PCI_EXP_SLTCTL_IND_ON,
33 PCI_EXP_HP_IND_BLINK = PCI_EXP_SLTCTL_IND_BLINK,
34 PCI_EXP_HP_IND_OFF = PCI_EXP_SLTCTL_IND_OFF,
35} PCIExpressIndicator;
36
37typedef enum {
38
39
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45
46
47 PCI_EXP_HP_EV_ABP = PCI_EXP_SLTCTL_ABPE,
48
49 PCI_EXP_HP_EV_PDC = PCI_EXP_SLTCTL_PDCE,
50
51 PCI_EXP_HP_EV_CCI = PCI_EXP_SLTCTL_CCIE,
52
53
54 PCI_EXP_HP_EV_SUPPORTED = PCI_EXP_HP_EV_ABP |
55 PCI_EXP_HP_EV_PDC |
56 PCI_EXP_HP_EV_CCI,
57
58
59
60} PCIExpressHotPlugEvent;
61
62struct PCIExpressDevice {
63
64 uint8_t exp_cap;
65
66 uint8_t pm_cap;
67
68
69 bool hpev_notified;
70
71
72
73
74
75
76 uint16_t aer_cap;
77 PCIEAERLog aer_log;
78
79
80 uint16_t ats_cap;
81
82
83 uint16_t acs_cap;
84};
85
86#define COMPAT_PROP_PCP "power_controller_present"
87
88
89int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type,
90 uint8_t port, Error **errp);
91int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
92 uint8_t type, uint8_t port);
93int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
94void pcie_cap_exit(PCIDevice *dev);
95int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset);
96void pcie_cap_v1_exit(PCIDevice *dev);
97uint8_t pcie_cap_get_type(const PCIDevice *dev);
98void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
99uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
100
101void pcie_cap_deverr_init(PCIDevice *dev);
102void pcie_cap_deverr_reset(PCIDevice *dev);
103
104void pcie_cap_lnkctl_init(PCIDevice *dev);
105void pcie_cap_lnkctl_reset(PCIDevice *dev);
106
107void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
108void pcie_cap_slot_reset(PCIDevice *dev);
109void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
110void pcie_cap_slot_write_config(PCIDevice *dev,
111 uint16_t old_slt_ctl, uint16_t old_slt_sta,
112 uint32_t addr, uint32_t val, int len);
113int pcie_cap_slot_post_load(void *opaque, int version_id);
114void pcie_cap_slot_push_attention_button(PCIDevice *dev);
115
116void pcie_cap_root_init(PCIDevice *dev);
117void pcie_cap_root_reset(PCIDevice *dev);
118
119void pcie_cap_flr_init(PCIDevice *dev);
120void pcie_cap_flr_write_config(PCIDevice *dev,
121 uint32_t addr, uint32_t val, int len);
122
123
124void pcie_cap_arifwd_init(PCIDevice *dev);
125void pcie_cap_arifwd_reset(PCIDevice *dev);
126bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev);
127
128
129uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
130void pcie_add_capability(PCIDevice *dev,
131 uint16_t cap_id, uint8_t cap_ver,
132 uint16_t offset, uint16_t size);
133void pcie_sync_bridge_lnk(PCIDevice *dev);
134
135void pcie_acs_init(PCIDevice *dev, uint16_t offset);
136void pcie_acs_reset(PCIDevice *dev);
137
138void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
139void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
140void pcie_ats_init(PCIDevice *dev, uint16_t offset);
141
142void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
143 Error **errp);
144void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
145 Error **errp);
146void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
147 Error **errp);
148void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
149 DeviceState *dev, Error **errp);
150#endif
151