LXR qemu/include/hw/ppc/xics.h

   1/*
   2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3 *
   4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5 *
   6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 *
  26 */
  27
  28#ifndef XICS_H
  29#define XICS_H
  30
  31#include "exec/memory.h"
  32#include "hw/qdev-core.h"
  33
  34#define XICS_IPI        0x2
  35#define XICS_BUID       0x1
  36#define XICS_IRQ_BASE   (XICS_BUID << 12)
  37
  38/*
  39 * We currently only support one BUID which is our interrupt base
  40 * (the kernel implementation supports more but we don't exploit
  41 *  that yet)
  42 */
  43typedef struct ICPStateClass ICPStateClass;
  44typedef struct ICPState ICPState;
  45typedef struct PnvICPState PnvICPState;
  46typedef struct ICSStateClass ICSStateClass;
  47typedef struct ICSState ICSState;
  48typedef struct ICSIRQState ICSIRQState;
  49typedef struct XICSFabric XICSFabric;
  50
  51#define TYPE_ICP "icp"
  52#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  53
  54#define TYPE_PNV_ICP "pnv-icp"
  55#define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
  56
  57#define ICP_CLASS(klass) \
  58     OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  59#define ICP_GET_CLASS(obj) \
  60     OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
  61
  62struct ICPStateClass {
  63    DeviceClass parent_class;
  64
  65    DeviceRealize parent_realize;
  66};
  67
  68struct ICPState {
  69    /*< private >*/
  70    DeviceState parent_obj;
  71    /*< public >*/
  72    CPUState *cs;
  73    ICSState *xirr_owner;
  74    uint32_t xirr;
  75    uint8_t pending_priority;
  76    uint8_t mfrr;
  77    qemu_irq output;
  78
  79    XICSFabric *xics;
  80};
  81
  82#define ICP_PROP_XICS "xics"
  83#define ICP_PROP_CPU "cpu"
  84
  85struct PnvICPState {
  86    ICPState parent_obj;
  87
  88    MemoryRegion mmio;
  89    uint32_t links[3];
  90};
  91
  92#define TYPE_ICS "ics"
  93#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
  94
  95#define ICS_CLASS(klass) \
  96     OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
  97#define ICS_GET_CLASS(obj) \
  98     OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
  99
 100struct ICSStateClass {
 101    DeviceClass parent_class;
 102
 103    DeviceRealize parent_realize;
 104};
 105
 106struct ICSState {
 107    /*< private >*/
 108    DeviceState parent_obj;
 109    /*< public >*/
 110    uint32_t nr_irqs;
 111    uint32_t offset;
 112    ICSIRQState *irqs;
 113    XICSFabric *xics;
 114};
 115
 116#define ICS_PROP_XICS "xics"
 117
 118static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 119{
 120    return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
 121}
 122
 123struct ICSIRQState {
 124    uint32_t server;
 125    uint8_t priority;
 126    uint8_t saved_priority;
 127#define XICS_STATUS_ASSERTED           0x1
 128#define XICS_STATUS_SENT               0x2
 129#define XICS_STATUS_REJECTED           0x4
 130#define XICS_STATUS_MASKED_PENDING     0x8
 131#define XICS_STATUS_PRESENTED          0x10
 132#define XICS_STATUS_QUEUED             0x20
 133    uint8_t status;
 134/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 135#define XICS_FLAGS_IRQ_LSI             0x1
 136#define XICS_FLAGS_IRQ_MSI             0x2
 137#define XICS_FLAGS_IRQ_MASK            0x3
 138    uint8_t flags;
 139};
 140
 141#define TYPE_XICS_FABRIC "xics-fabric"
 142#define XICS_FABRIC(obj)                                     \
 143    INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
 144#define XICS_FABRIC_CLASS(klass)                                     \
 145    OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
 146#define XICS_FABRIC_GET_CLASS(obj)                                   \
 147    OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
 148
 149typedef struct XICSFabricClass {
 150    InterfaceClass parent;
 151    ICSState *(*ics_get)(XICSFabric *xi, int irq);
 152    void (*ics_resend)(XICSFabric *xi);
 153    ICPState *(*icp_get)(XICSFabric *xi, int server);
 154} XICSFabricClass;
 155
 156ICPState *xics_icp_get(XICSFabric *xi, int server);
 157
 158/* Internal XICS interfaces */
 159void icp_set_cppr(ICPState *icp, uint8_t cppr);
 160void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
 161uint32_t icp_accept(ICPState *ss);
 162uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 163void icp_eoi(ICPState *icp, uint32_t xirr);
 164void icp_reset(ICPState *icp);
 165
 166void ics_write_xive(ICSState *ics, int nr, int server,
 167                    uint8_t priority, uint8_t saved_priority);
 168void ics_set_irq(void *opaque, int srcno, int val);
 169
 170static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
 171{
 172    return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK);
 173}
 174
 175void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 176void icp_pic_print_info(ICPState *icp, Monitor *mon);
 177void ics_pic_print_info(ICSState *ics, Monitor *mon);
 178
 179void ics_resend(ICSState *ics);
 180void icp_resend(ICPState *ss);
 181
 182Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
 183                   Error **errp);
 184void icp_destroy(ICPState *icp);
 185
 186/* KVM */
 187void icp_get_kvm_state(ICPState *icp);
 188int icp_set_kvm_state(ICPState *icp, Error **errp);
 189void icp_synchronize_state(ICPState *icp);
 190void icp_kvm_realize(DeviceState *dev, Error **errp);
 191
 192void ics_get_kvm_state(ICSState *ics);
 193int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
 194int ics_set_kvm_state(ICSState *ics, Error **errp);
 195void ics_synchronize_state(ICSState *ics);
 196void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
 197
 198#endif /* XICS_H */
 199